Commit Graph

23538 Commits

Author SHA1 Message Date
Patrick Rudolph ac24d3c311 sconfig: Add SMBIOS type 9 entries
Add the new field 'smbios_slot_desc', which takes 2 to 4 arguments.
The field is valid for PCI devices and only compiled if SMBIOS table
generation is enabled.

smbios_slot_desc arguments:
1. slot type
2. slot lenth
3. slot designation (optional)
4. slot data width (optional)

Example:

    device pci 1c.1 on
        smbios_slot_desc "21" "3" "MINI-PCI-FULL" "8"
    end # PCIe Port #2 Integrated Wireless LAN

Tested on Lenovo T520.

Change-Id: If95aae3c322d3da47637613b9a872ba1f7af9080
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-05-07 16:04:56 +00:00
Dan Elkouby 1a93058448 sb/intel/bd82x6x: Fix flashconsole after lockdown
SMM final locks the SPI BAR, which causes flashconsole to hang.
Re-init it like SMM does with CONFIG_SPI_FLASH_SMM.

Change-Id: Ib802d7ee32f1fb0a68a84b0280480dcaefa9831f
Signed-off-by: Dan Elkouby <streetwalkermc@gmail.com>
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-07 16:04:07 +00:00
Maxim Polyakov 3ba380797b soc/intel/skylake: remove PrimaryDisplay check
Checking the PrimaryDisplay parameter (added by patch with Change
Id Ie3f9362676105e41c69139a094dbb9e8b865689f) isn`t required. The
display connected to PEG works  even if IGD is primary for output
image and at the same time this device is disabled

Tested on Asrock H110M-DVS with NVIDIA GTX 1060 GPU
Payload: tianocore edk2-stable201811-216-g51be9d0

Change-Id: I5615597881a151bb004676d914fbf40874ac1f68
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32615
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-07 16:03:01 +00:00
Maxim Polyakov d7d0b04d3a soc/skl/memmap: calculate mem size even if IGD undefined in devtree
The DRAM base memory should be calculated even if IGD isn`t defined
in the board device tree

Tested on Asrock H110M-DVS

Change-Id: I3da51473e6c06da803bd969a4a6dff792c18f962
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-07 16:02:32 +00:00
Elyes HAOUAS 551a75923e sb/{ICH7,NM10,PCH}: Use common watchdog_off function
Change-Id: I704780b6ae7238560dcb72fc027addc1089e0674
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: David Guckian
2019-05-07 16:01:35 +00:00
Jiaxin Yu 30bc9f415d google/kukui: Support sound in boot process
Configure and enable GPIO for speaker amp max98357a.

BUG=b:117254418
TEST=Build pass and verified on kukui p1 board
BRANCH=None

Change-Id: I97655702dff402245326d2eff71fae0e336df9f5
Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-05-07 16:00:31 +00:00
Nico Huber 3c0d23b6ab intel/fsp1_1: Drop remnants of `pei_data`
`pei_data` was a struct with blob parameters from pre-FSP times.
Somehow, it sneaked into upstream FSP1.1 support (probably because
early board ports were written for a different blob). When added
upstream, its usage was already perverted. It was declared at SoC
level but mostly used to pass mainboard data from mainboard code
to itself and FSP data from FSP code to itself. Now that no board/
SoC code uses it anymore, we can finally drop it.

Change-Id: Ib0bc402703188539cf2254bdc395cca9dd32d863
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-07 15:59:10 +00:00
Nico Huber 0ebdf2ac75 mb/purism/librem_skl: Refactor to get rid of `pei_data`
The SoC specific `struct pei_data` was filled with values that were
never consumed anywhere again. So just merge the used code into
`romstage.c` where it's effectively used.

Change-Id: I499b3cfcdd5400ea132749555d433a2d8a9471a3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-07 15:58:39 +00:00
Nico Huber feb50f15cc mb/google/glados: Refactor to get rid of `pei_data`
The SoC specific `struct pei_data` was filled with values that were
later only consumed by the mainboard code again. Avoid jumping through
this hoop and fill FSP UPDs directly.

Change-Id: I040f4a55b4f4bad3f6072920e5e2eceded4cb9bb
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-07 15:58:32 +00:00
Nico Huber 85f0b051ba mb/google/cyan: Refactor to get rid of `pei_data`
The SoC specific `struct pei_data` was filled with values that were
later only consumed by the mainboard code again. Avoid jumping through
this hoop and fill FSP UPDs directly.

The provided solution locates the SPD data in CBFS again to fill SMBIOS
tables. This is not perfect. OTOH, this code isn't mainboard specific
and doesn't belong here anyway.

Change-Id: Ib6103d5b9550846fe17c926631a013ff80b9598f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-07 15:58:05 +00:00
Nico Huber ec562161cd soc/intel/bsw: Move memory init values into `romstage.h`
`chip.h` is usually used as devicetree interface.

Change-Id: Ied30927d68927b86758a84ccf3f5fbd8cce632f1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32592
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-07 15:57:51 +00:00
Nico Huber f98f8ebb8c mb/intel/saddlebrook: Refactor to get rid of `pei_data`
The SoC specific `struct pei_data` was filled with values that were
later only consumed by the mainboard code again. Avoid jumping through
this hoop and fill FSP UPDs directly.

Change-Id: I399dd89f85ccea43fdf90bd895e71324f4b409cc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-07 15:57:15 +00:00
Nico Huber 9b5b9e46b9 mb/intel/kunimitsu: Refactor to get rid of `pei_data`
The SoC specific `struct pei_data` was filled with values that were
later only consumed by the mainboard code again. Avoid jumping through
this hoop and fill FSP UPDs directly.

Change-Id: Ibc013ccea9f83ef29f22fe2da4c0d12096308636
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-07 15:57:05 +00:00
Nico Huber 66318aad07 intel/fsp1_1: Move MRC cache pointers into `romstage_params`
These are part of a common concept and not SoC specific.

Change-Id: I9cb218d7825bd06a138f7f5d9e2b68e86077a3ec
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-05-07 15:55:50 +00:00
Nico Huber 16895c529c intel/fsp1_1: Drop `boot_mode` from `pei_data`
It was only used locally.

Change-Id: Iaaad760e8ceca62655f5448c30846cf11959e8e1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-05-07 15:53:26 +00:00
Nico Huber a842d3ee6a intel/fsp1_1: Drop unused, weak raminit()
Change-Id: I5d155df1d589fc8d7462f46e87275bd6efae0a7f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-05-07 15:52:36 +00:00
Elyes HAOUAS 66b35bad88 mb/lenovo/x60: Use system_reset()
Change-Id: I4515d8d14629741f3bf49e9459d7d57c18d321ce
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-07 15:52:07 +00:00
Elyes HAOUAS 1bc7b6e135 {gm45,pineview,sandybridge,x4x}: Use {full,system}_reset() function
Use already defined system_reset() and full_reset() functions.

Change-Id: Ic29fab70cf7f23d49c3eeeb97c984c523f973972
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-07 15:52:01 +00:00
Evgeny Zinoviev ba092a9ab6 mb/apple/macbookair4_2: Correct internal video port selection
The MacBook Air 4,2 uses eDP, according to the schematics.

Change-Id: Ifc98eab343fd89b8512e92e01fddf34ef8447d5f
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32606
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-07 15:51:30 +00:00
Eric Lai 0c0a9810c7 mb/google/sarien: Turn off camera power when s0ix
Turn off camera power when s0ix for power saving.

BUG=b:129177593
TEST= measure camera power comsumption is 0mV under s0ix

Change-Id: I5a9b7ec1e95cc9931d8d5f2dc1254805c9d0ffed
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-05-06 17:31:11 +00:00
Eric Lai 8c0acc5515 mb/google/sarien: Fine tune SD card D3 cold timing
A13 and A15 need to set low before H12 reset. Change
the program sequence for fit HW requirement.

BUG=b:131876963
TEST=boot up and check SD card functional

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I2f1752070f24833aaaab75dea8493caf2ed7f157
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-05-06 15:59:55 +00:00
Joel Kitching 1a6b5c23a1 vboot: remove use of GoogleBinaryBlockHeader
Remove use of deprecated GoogleBinaryBlockHeader struct, and
replace with vb2_gbb_header.

BUG=b:124141368, chromium:954774
TEST=make clean && make test-abuild
BRANCH=none

Change-Id: Iee3bd877cb1791a689efdeabda324f43f7d0c6f2
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-05-06 12:40:31 +00:00
Elyes HAOUAS 45b824d694 src: Remove unused include <halt.h>
Change-Id: I2f142cc80692e60eb0f81f57339a247f6ef4a524
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-06 10:39:01 +00:00
Patrick Rudolph a06fa32daf arch/x86: Remove unused file
The file is no longer used by any code. Remove it.

Change-Id: I73f06cac11201dc37218d352ab995cf4f012c36a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-05-06 10:36:40 +00:00
Matthew Garrett 78b58a4996 drivers/intel/fsp2_0: Fix fsp post-init validation
Part of this checks whether tolum_base and cbmem_top are the same - however,
cbmem_top hasn't been initialised at the point where this call occurs.
Change the ordering to fix that.

Signed-off-by: Matthew Garrett <mjg59@google.com>
Change-Id: Ib89e0513bdc35c3751a9d4c2a2789a2836046789
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-05-06 10:35:25 +00:00
Karthikeyan Ramasubramanian 6629b4bbf8 soc/intel/apollolake: Reset GPI IS & IE registers at ramstage
Reset GPI Interrupt status and enable registers from ramstage instead of
bootblock so that it applies to devices in field.

BUG=b:130593883
BRANCH=octopus
TEST=Ensure that the Interrupt status & enable registers are reset
during the boot up when the system is brought out of G3, S5 & S3. Ensure
that the system boots fine to ChromeOS.

Change-Id: Ib11b580ceb23bd1fe789f549b667a8ced2d859a1
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32534
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-06 10:34:52 +00:00
Eric Lai 7f1e9dbf3a soc/intel/cannonlake/acpi: Add board level s0ix call back
Add board level s0ix call back. Since some driver doesn't
care _ON/_OFF method. Add a control method for s0ix usage.

BUG=b:129177593
TEST=NA

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I404f388b19355ae89b36d1fb07f9fb4f97eb3b2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-06 10:34:35 +00:00
Felix Singer e59ae107c2 soc/apollolake: Add ramstage hook
A hook for romstage is already existing but not for ramstage.

It's very useful for debugging as it allows to run code
for testing purposes by the mainboard. Also, it allows to
run configuration code or configure FSP options, which
don't have a devicetree option.

Change-Id: I9edc543943c5cbc696fc6c615cb77ef68294c980
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-06 10:34:10 +00:00
Marshall Dawson 1bc04e3c3e soc/amd/stoneyridge: Correct bugs in lpc.c
Remove the bridge enable step of accessing D14F0x64.  This method for
enabling the bridge appears to be last present in the SB700 device.
Beginning in the SB800 (and all FCH, SoC devices), the enable is in
PMxEC[0].  Since the bridge is enabled in bootblock to allow port 80h,
there is no need to maintain it in ramstage.

Correct the device used for misc. configuration of the LPC bridge.
The #defined value removed is 14.0 but the settings are in 14.3.

TEST=Boot Grunt, check console and dmesg for errors and warnings
BUG=b:131862871

Change-Id: I078be974dc3c78c94cb7c0832518f21bac029ff2
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-05-06 10:33:03 +00:00
Marshall Dawson e09caf6428 soc/amd/stoneyridge: Move acpi_fill_mcfg to northbridge
Relocate the function to the more appropriate file.

Change-Id: I92a3e8d0461ae228f6c01567db159e2458de5f6b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-05-06 10:32:42 +00:00
Julius Werner 7c712bbb6c Fix code that would trip -Wtype-limits
This patch fixes up all code that would throw a -Wtype-limits warning.
This sometimes involves eliminating unnecessary checks, adding a few odd
but harmless casts or just pragma'ing out the warning for a whole file
-- I tried to find the path of least resistance. I think the overall
benefit of the warning outweighs the occasional weirdness.

Change-Id: Iacd37eb1fad388d9db7267ceccb03e6dcf1ad0d2
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32537
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-06 10:32:15 +00:00
Julius Werner 9d3fa7a229 spd_bin: Do not depend CONFIG_DIMM_MAX on CONFIG_GENERIC_SPD_BIN
I can't claim that I really understand what this code does, but it looks
like there are platforms that use code from lib/spd_bin.c without
enabling CONFIG_GENERIC_SPD_BIN. Some functions in that file contain
references to CONFIG_DIMM_MAX, so that option probably shouldn't depend
on CONFIG_GENERIC_SPD_BIN.

Change-Id: I041c52b6bd255e9a9920e5a101165ba5fc5fa6f3
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32548
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-06 10:31:38 +00:00
Matt DeVillier 6a4a026e13 purism/librem_skl: remove 13v3 target, clean up Kconfig
Remove the Librem 13v3 as a separate board; instead build a
single firmware image for the 13 v2/v3 boards.

Clean up Kconfig options:
- remove entries for 13v3 board
- fold entries into a single line where possible
- remove redundant MAINBOARD_VERSION option (will default to 1.0)
- remove unused microcode length/location (only needed for FSP CAR)

Test: build/boot Librem 13 v2/v3 boards with same image

Change-Id: Ic09b8ec5c576f4c4c48ef30ee3f60a4c2c286cd3
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-06 10:30:27 +00:00
Elyes HAOUAS 32f48a2d56 mb/google: Remove unused 'include <smbios.h>'
Change-Id: Ib96c317391745fa5afea785e3c7441124b3fc252
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-05-06 10:30:05 +00:00
Jacob Garber fb0fa7643e sb/amd/rs780: Use 32 bit variable to avoid truncation
The {read,write}_index functions expect a 32 bit value, as
do the bitwise operations.

Found-by: Coverity Scan #1229584
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: Idc2bc46c899d5a4e8b089644dca076a88d97dd7c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-05-06 10:29:28 +00:00
Frans Hendriks 5471be69b9 soc/intel/braswell/Makefile.inc: Remove commented-out line
cpu_microcode_bins is commented out.
Remove this line.

BUG=NA
TEST=Portwell PQ7-M107

Change-Id: Ic398d232bea84a765fce940ef876916a873e561f
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32510
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-06 10:29:13 +00:00
Marius Genheimer 4998becda3 soc/skylake: Add missing PCH IDs
Added IDs for:
- H170
- Z170
- Q170
- Q150
- B150

Used documents:
- 332690-005EN

Tested on Gigabyte GA-Z170N-WIFI

Change-Id: If20a2b764afa02785a97948893dbc5b5f60aff60
Signed-off-by: Marius Genheimer <mail@f0wl.cc>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32517
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-06 10:29:02 +00:00
Patrick Rudolph 72a9091a0e sb/intel/bd82x6x: Use common/rcba.h
Make use of:
* southbridge/intel/common/rcba.h
* southbridge/intel/common/pmbase.c
* defines in pch.h

Get rid of dependency to DEFAULT_RCBA.

Tested on Lenovo T520 (Intel Sandy Bridge).
Still boots to OS, no errors visible in dmesg.

Change-Id: I879fce6a5bb80499e1986e618a1422a7aaa3a0c0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32066
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-06 10:28:42 +00:00
Tristan Shieh 0dd6b55a7e google/kukui: Raise the CPU frequency
Run CPU at the highest freqency (1989MHz) to speed up the boot time.

BUG=b:80501386
BRANCH=none
Test=Boots correctly on Kukui

Change-Id: I703ffcb99367f87e6792a72485f5634e0505e5ac
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32466
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-06 10:28:09 +00:00
Tristan Shieh b75f493ed7 mediatek/mt8183: Wait 200us for voltages to settle
When we increase voltages, it takes 200us for voltages to stablize.

BUG=b:80501386
BRANCH=none
Test=Boots correctly on Kukui

Change-Id: I5f32035693b6084dbe763411c612ae5d1f7c9e48
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-05-06 10:27:53 +00:00
Tim Wawrzynczak 3fe7c44d50 mainboard/google/hatch: Enable PEN_EJECT_L as wake & notify source.
Updated GPP_A8 to be a GPI and SCI source, to support both wake and
notifications.

BUG=b:128941098
BRANCH=none
TEST=Compiles, simulated pen eject with PCH_INT_L signal.  Both evtest
and waking from s0ix confirm this works.  The output of /proc/interrupts
confirms the correct interrupt is triggered.

Change-Id: I080fb3cbfb3e2f55209ca31824b00ca820d70f78
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-06 10:27:28 +00:00
Tim Wawrzynczak 939440c48b soc/intel/cannonlake: Add GPIO dual-route support.
Select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT in Kconfig

BUG=none
BRANCH=none
TEST=compiles

Change-Id: If5f59ea50c13bd1f279637e281468e6d0312dbab
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32486
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-06 10:27:17 +00:00
Tim Wawrzynczak 95f8884c95 soc/intel/common: Add new PAD_CFG macro.
Added macro named PAD_CFG_GPI_GPIO_DRIVER_SCI, for pads that need to be
configured as GPI, GPIO Driver mode, and SCI interrupt.

Also remove PAD_IRQ_CFG_DUAL_ROUTE macro (subsumed by
PAD_CFG_GPI_IRQ_WAKE).

BUG=none
BRANCH=none
TEST=Compiles

Change-Id: I0332c64e2fa62ce29c772444606adbfdf9c9afc4
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32485
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-06 10:27:07 +00:00
Frans Hendriks 683e77e479 drivers/intel/fsp1_1/cache_as_ram.inc: Reduce max line length to 80
Cosmetic change to reduce line length to 80 max.

BUG=NA
TEST=Build Portwell PQ7-M107

Change-Id: Ib537592c0a6a3fffc85622e6b74ad5ec8041e7dc
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-06 10:26:50 +00:00
Kyösti Mälkki 85b2ed5438 soc/amd/common: Introduce module_dispatch()
This change removes all the separate entrypoint dispatch
functions as they all share the same pattern.

Furthermore, none of the function definitions under vendorcode
binaryPI/AGESA.c file have proper declarations, the ones compiler
picks up from AGESA.h are for the internal implementations and
with sanely organized headerfiles would not be exposed outside
the build of AGESA at all.

Change-Id: I0b72badc007565740c93b58743cfd048e8b42775
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31485
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-06 10:26:25 +00:00
Frans Hendriks 43fc38943d mainboard/intel/strago/acpi: Serialize _CRS method
IASL reports warning 'Control Method should be made Serialized'.
Change _CRS method to Serialized.

BUG=N/A
TEST=Build Intel Strago

Change-Id: I63a7e1caab19360a9a5831458311d5a83fdf52d1
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-06 10:26:11 +00:00
Werner Zeh 42065f8f94 mb/siemens/mc_apl2: Limit SD-Card speed to DDR50
Due to PCB limitations the SD-Card interface is not able to operate
with the highest frequency reliably. The OS driver will switch to
the highest mode if a SD-Card is attached which supports this high
frequency mode. In order to work around this PCB limitation disable the
high frequency modes in the controller capabilities (SDR104 and HS400
mode) and leave SDR50 and DDR50 enabled.

Change-Id: Ia5fed5fb70b027de34170b49620927614a00fb7a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-06 04:35:08 +00:00
Elyes HAOUAS 29a1a0857a mb/msi/ms7707: Remove MAINBOARD_PCI_SUBSYSTEM_{DEVICE_ID,VENDOR_ID}
References to MAINBOARD_PCI_SUBSYSTEM_{DEVICE_ID,VENDOR_ID} were removed.

Change-Id: I70ef22aac165a19663749f76449907482b761316
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-05 10:47:58 +00:00
Matt DeVillier 73c312fce5 src/Kconfig: remove duplicate entry for drivers/fsp1_0/Kconfig
The entry for drivers/intel/fsp1_0/Kconfig was added under the
chipset menu before addtional FSP versions were added, and the
drivers/*/*/Kconfig entry added to support them. This results
in the fsp1_0 Kconfig items being duplicated in the Chipset and
Generic Drivers menus.

Remove the chipset entry since it's no longer needed.

Test: select FSP 1.0 mainboard (e.g. intel/minnowmax) in menuconfig,
observe FSP 1.0 Kconfig entries listed only under Generic Drivers menu.

Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: If1e78fb9259b1a46d308db829881eb3b3d17cf40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32565
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-04 20:12:44 +00:00
Frans Hendriks e6bf51fb22 {soc, southbridge} : Correct typo in comment
BUG=N/A
TEST=N/A

Change-Id: I1b207e0b77bac8860ba7501378297c1f3604141c
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32453
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-03 22:39:14 +00:00
Frans Hendriks a88041c043 mainboard/google/cyan/acpi: Serialize _CRS method
IASL reports warning 'Control Method should be made Serialized'.
Change _CRS method to Serialized.

BUG=N/A
TEST=Build Google Banon and Google Cyan

Change-Id: Iffa097a2100cfa91efa3b617311500b83f839bce
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2019-05-03 22:38:38 +00:00
T Michael Turney bd0b51c0be sdm845: Add QCLib to RomStage to perform IP init
CB acts as I/O handler for QCLib (e.g. DDR training data)
This interface allows bi-directional data flow between
CB and QCLib
Tested and working interfaces:
 DDR Training data
 QCLib serial console output
 DDR Information (base & size)
 limits cfg data
TEST=build & run

Change-Id: I073186674a1a593547d1ee1d15c7cd4fd8ad5bc1
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-05-03 21:59:16 +00:00
T Michael Turney 101098c41a sdm845: Combine BB with QC-Sec for ROM boot
TEST=build & run

Change-Id: I222a56f1c9b74856a1e1ff8132bab5e041672c5d
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25207
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-03 21:59:05 +00:00
Matt DeVillier 61309e39b3 drivers/fsp 1.1: clean up Kconfig options
Now that support has been added for using the public FSP
repo for Braswell platform, clean up Kconfig options and
set sane defaults when using it.

The following changes have been made:
 - add option to use the 3rdparty/fsp repo for Braswell platform
 - reorder FSP 1.1 Kconfig entries for improved flow/readability
 - set the default path for the FSP binary based on use of FSP
   repo and platform
 - set the CBFS location for the FSP binary based on platform

Change-Id: Ie2f732bf0ac4d4551908caa56360b8bb2869b4c7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-03 20:15:29 +00:00
Matt DeVillier fd7440d231 soc/intel/braswell: add default option to use public FSP
The current Braswell FSP 1.1 header in vendorcode/intel, for
which there is no publicly available FSP binary, contains silicon
init UPDs which are not found in the publicly available header/binary
in the FSP Github repo. This prevents new boards from being added
which use the public Braswell FSP header/binary.

To resolve this, move the UPDs not found in the public header from
the soc's chip.c to ramstage.c for the boards which use them. Add
a Kconfig option to use the current non-public FSP header and
select it for boards which need it (google/cyan variants); set the
public FSP option as the default. Use the Kconfig option to set
FSP_HEADER_PATH to ensure the correct header is used.

Test: build google/cyan and intel/strago using non-public and
public FSP header/binaries respectively.

Change-Id: I43cf18b98c844175a87b61fdbe4b0b24484e5702
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-03 20:13:59 +00:00
Nathan_chen b242de5bfc mb/google/arcada: Add settings for noise mitgation
Enable acoustic noise mitgation for arcada platform,
the slow slew rates for Ia and Gt are fast time dived by 8.

BUG=b:131144464
TEST=waveform test and hardware validation result pass.

Signed-off-by: nathan chen <nathan_chen@wistron.corp-partner.google.com>
Change-Id: I395b2fc527705ab207325cfd7147e6af5f300fce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-05-03 16:29:40 +00:00
Gaggery Tsai aa0929d101 mb/google/poppy/variant/atlas: enable USB acpi
Main objective for this change is to export the bluetooth reset
gpio to the kernel for use in an rf-kill operation.
To do so, we enable USB acpi and define all of the USB2 devices,
which includes bluetooth's reset gpio information.

BUG=b:122540489
BRANCH=None
TEST=emerge-atlas coreboot chromeos-bootimage
     $cat sys/firmware/acpi/tables/SSDT > /tmp/ssdt.dat &
     retrieve ssdt.dat from DUT &
     $iasl -d ./ssdt.dat & check the HS03 node is with "reset-gpio"
     under _DSD object

Change-Id: I411ef707782655361bd1b8ac2b914b8ae64defeb
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Caveh Jalali <caveh@google.com>
2019-05-03 16:29:34 +00:00
Joel Kitching 82d73e2d5a nb/intel/haswell: correct a typo in Kconfig
Change-Id: I115e065ce11946b85571e7233203be68c1789d70
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-05-03 14:32:06 +00:00
Chandana Kishori Chiluveru c0fe0b28a9 sdm845: Add USB support on cheza platform
This patch adds code to initialize two USB DWC3.0 controllers
and its associated QUSB V2 10nm PHYs to the SDM845 SOC, and uses them to
initialize USB3.0 on the cheza mainboard.

Synopsis controller initialization and configuration sequences taken from
USB 3.0 HPG chapter 2.2 and refer PHY HPG chapter 10.2 for QUSB phy
programming.

Includes Super speed mode support.

TEST=USB keypad and mass-storage device enumeration tested with this patch

Change-Id: I475a7757239acb8ef22a4d61afd59b304a7f0acc
Signed-off-by: Chandana Kishori Chiluveru <cchiluve@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-05-02 23:06:06 +00:00
T Michael Turney 7a3e46d767 qualcomm: Add QCLib interface support to common/
Change-Id: I38d086c379a3c2f54d1603a2fed5b33860f7f4d7
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-05-02 23:05:55 +00:00
T Michael Turney 32851c6df7 sdm845: Select VBOOT_MIGRATE_WORKING_DATA, now required
Change-Id: Idebbbd89de05d949e6f953aa49d8662d64383d1a
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-05-02 23:05:45 +00:00
Subrata Banik 4d6cfc82ed mainboard/intel/icelake_rvp: Add support to read board ID from EC
This patch selects EC_ACPI kconfig to identify Intel Ice Lake
RVP board by querying EC.

Change-Id: I0082e04ef1b21d533e40d232209ee630f748aec6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2019-05-02 06:58:04 +00:00
Subrata Banik 42f9f14a61 soc/intel/icelake: Correct the GPE DWx mapping for GPIO groups
This implementation corrects the GPE DWx mapping for GPIO groups.
The assignments is done in GPIO MISCFG register for all GPIO communities.
And configures the which GPIO communities get register as Tier1.

Change-Id: I9c306d46e5194944def26c24cdb95f5ebada42b8
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2019-05-02 06:03:21 +00:00
Subrata Banik ffb83bee26 soc/intel/icelake: Select FSP_M_XIP
This patch ports CB:32275 changes from CNL to ICL.

Ice Lake require that FSP-M component should be
XIP. This change selects FSP_M_XIP so that the right arguments are
passed into cbfstool when adding this component.

Change-Id: Icc5550f1f94957fa1b28c8bba6fc0efee98e233e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32507
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-02 06:03:15 +00:00
Subrata Banik 67524b57af soc/intel/icelake: Move power_state functions to pmutil.c
This patch ports CB:31787 and CB:31908 changes from CNL to ICL.

This change moves soc_fill_power_state and soc_prev_sleep_state to
pmutil.c. It allows the functions to be used across romstage and smm.

Also fix GEN_PMCON bit checks as below:
ICL PCH has PWR_FLR, SUS_PWR_FLR and HOST_RST_STS bits in GEN_PMCON_A
and so this change updates the check for these bits to use GEN_PMCON_A
instead of GEN_PMCON_B.

Change-Id: Ib7ab95b7bbcc97a076d27a11db2105f7b976b521
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32506
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-02 06:03:06 +00:00
Subrata Banik 83fe4c4e47 soc/intel/{broadwell, skylake}: Remove unused pch_log_state() declaration
This patch removes unused pch_log_state() function declaration from pch.h
because elog.c has static implementation of pch_log_state().

Change-Id: Ib0f3831dc3b60af2ee432a76866e401a51b96fb7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32505
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-02 06:02:59 +00:00
Subrata Banik 5489341e63 soc/intel/icelake: Add chipset event logging
This patch ports CB:30718 and CB:31908 changes from CNL to ICL.

Add logging of chipset events on boot into the flash event log.
This was tested on a google/dragonegg board to ensure that events
like "System Reset" are added to the log as expected.

Also fix GEN_PMCON bit checks as below:
ICL PCH has PWR_FLR, SUS_PWR_FLR and HOST_RST_STS bits in GEN_PMCON_A
and so this change updates the check for these bits to use GEN_PMCON_A
instead of GEN_PMCON_B.

Change-Id: I25ec32e81f8801f8d5e69c6095ffed73d75dded6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2019-05-02 06:02:52 +00:00
Subrata Banik ff9104eae3 soc/intel/icelake: Clear PMCON status bits
This patch ports CB:31902 changes from CNL to ICL.

The prev_sleep_state value was showing 5 even after warm reboot, once the
SUS_PWR_FLR bit is being set. This bit was not being cleared.
Hence clearing the PMCON status bits.

Change-Id: Ia07aa17b4491216a277c36edfe6ed2aa489287c6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32503
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-02 06:02:40 +00:00
Martin Kepplinger d32a493091 x86emu: add console.h header to fix compilation
Commit 351e3e5 ("src: Use include <console/console.h> when appropriate")
has broken the build here, see below, so we include console.h here again.

In file included from src/device/oprom/x86emu/x86emui.h:65,
                  from src/device/oprom/x86emu/debug.c:40:
src/device/oprom/x86emu/debug.c: In function 'x86emu_dump_regs':
src/device/oprom/x86emu/debug.h:46:22: error: implicit declaration of function 'printk'; did you mean 'printf'?
[-Werror=implicit-function-declaration]
  #define printf(x...) printk(BIOS_DEBUG, x)
                       ^~~~~~
src/device/oprom/x86emu/debug.c:366:5: note: in expansion of macro 'printf'
      printf("\tAX=%04x  ", M.x86.R_AX );
      ^~~~~~

Fixes: 351e3e5 ("src: Use include <console/console.h> when appropriate")
Change-Id: I75d0b7c08bfa6dcb07778bbb762223b62cfc3da7
Signed-off-by: Martin Kepplinger <martink@posteo.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-05-02 05:00:33 +00:00
Eric Lai 43a3c513f8 mb/google/sarien: Disable S5 wake on LAN by default
Chromebook doesn't require support wake on LAN in S5.
Disable it by default for power saving.

BUG=b:131571666
TEST= check LAN indicator is off under S5

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia90c9d2f3ea9b3580e9a7bbfb47c917dd51e3c03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-05-01 20:07:48 +00:00
Matt DeVillier 7144702f83 google/cyan,intel/strago: increase default CBFS size
a 1M CBFS size is inadequate when adding the FSP binary to
image due to default FSP location in CBFS, so bump to 2M
to ensure autobuilds succeed.

Change-Id: I0683bea43cc71fad32bc42bfbd72f3913256d53c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-01 18:51:22 +00:00
John Zhao 37b26261cc arch/x86/acpi: Update VT-d DMA remapping structure flags setting
DMA remapping structure flags settings are Bit 0: INTR_REMAP, Bit 1:
X2APIC_OPT_OUT, Bit 2: DMA_CTRL_PLATFORM_OPT_IN_FLAG, Bits 3-7:
Reserved (0).

BUG=b:130351429
TEST=Image built and kernel booted to kernel.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Iaf4764a9062756cadc335d1932b0da8628797f5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32516
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-01 18:33:55 +00:00
Furquan Shaikh 4c8726574c soc/intel/common: Set RX_DISABLE for pads configured as NC
For GPIO pads that are configured as no-connect (PAD_NC), setting it
as GPI (with Rx enabled) leads to GPE0_STS being set
incorrectly. Though this is not an issue in practice (GPE0_EN is not
set, so no events triggered), it can confuse users when debugging GPE
related issues.

This change configures PAD_NC to have Rx disabled along with Tx to
ensure that it does not end up setting GPE0_STS bits for unwanted
GPIO pads.

P.S.: IOSSTATE config does not have a TxDRxD setting, so leaving that
configuration as is.

BUG=b:129235068
TEST=Verified that GPE0_STS bits are not set for pads that are marked
as PAD_NC.

Change-Id: I726cc7b86a94e7449352cd8a8806d4d775c593dc
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2019-05-01 02:18:31 +00:00
Max Blau 517eda5ca4 mainboard: Add MSI MS-7707
* MSI MS-7707 V1.1 (Medion OEM Akoya P4385D MSN10014555)
* SandyBridge Intel P67 (BD82x6x)
* Winbond 25Q32BV (4MB)
* Fintek F71808A
* Intel 82579V Gigabit
* NEC uPD720200 USB 3.0 Host Controller
* IME 7.0.4.1197

Working:
* PCIe gfx adapter
* PS/2 Keyboard
* USB3.0
* Ethernet
* S0/S3/S5
* HWM

Change-Id: I999149bb95d553ed217b2288cc34bce4fe88abb3
Signed-off-by: Max Blau <tripleshiftone@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-01 00:10:21 +00:00
Max Blau 13bfd04a99 superio/fintek/f71808a: Add more optional ramstage registers
Add more registers and make them optional, so they keep untouched/
their default if omitted.

Change-Id: I5d8008176d2972976b387c558658b8e70b50af8e
Signed-off-by: Max Blau <tripleshiftone@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-05-01 00:09:57 +00:00
Marty E. Plummer 22e605c2c0 rockchip: rk3399: increase memory for fit payload.
Increase ramstage to 2M, required to actually embed the 7.2mb uImage
into the coreboot.rom, increase the postram cbfs cache in order for the
fit image to be loadable (without this increase the fit payload is found
but not loaded)

Change-Id: Iee0ed9f7958588ceda54bb32253c84cac68abea2
Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-30 22:38:10 +00:00
Joel Kitching 6672bd8e6b vboot: refactor OPROM code
The name OPROM is somewhat inaccurate, since other steps to bring
up display and graphics are needed depending on mainboard/SoC.
This patch cleans up OPROM code nomenclature, and works towards
the goal of deprecating vboot1:

* Rename CONFIG_VBOOT_OPROM_MATTERS to
  CONFIG_VBOOT_MUST_REQUEST_DISPLAY and clarify Kconfig
  description
* Remove function vboot_handoff_skip_display_init
* Remove use of the VbInit oflag VB_INIT_OUT_ENABLE_DISPLAY
* Add |flags| field to vboot_working_data struct
* Create VBOOT_FLAG_DISPLAY_REQUESTED and set in vboot_handoff

BUG=b:124141368, b:124192753, chromium:948529
TEST=make clean && make test-abuild
TEST=build and flash eve device; attempt loading dev/rec modes
BRANCH=none

Change-Id: Idf111a533c3953448b4b9084885a9a65a2432a8b
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-30 21:47:25 +00:00
Naveen Manohar 2b8789bb3b mb/google/hatch: Modify IRQ configuration to enable RT5682 headset INT
Patch corrects IRQ and GPIO configuration for RT5682 codec's Jack INT.
Switching IOAPIC to GpioInt because ACPI Interrupt() doesn't support
jack triggering on both edges.

BUG=b:130180492
TEST=build and boot on a CML EVT board.
Use evtest & verify headset jack detection functions as expected.

Change-Id: Ia9bf8d554b54554f9ac1e78fd44a508964c8a14d
Signed-off-by: Naveen Manohar <naveen.m@intel.com>
Suggested-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32474
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-30 20:36:33 +00:00
Elyes HAOUAS 46c5807d29 sb/intel/bd82x6x: Use system_reset()
Use already defined system_reset() function.

Change-Id: I6e5aff96e06830931acf700593d3e1689857efdc
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-04-29 16:01:36 +00:00
Elyes HAOUAS 5db9871a5e ich7/i945: Use system_reset()
Use already defined system_reset() function.

Change-Id: Ieff4271c4a09d564d5f3415d8bc2c3843c8460f2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-29 16:01:09 +00:00
Elyes HAOUAS d07048a7f9 src/mb: Use system_reset()
Use already defined system_reset() function.

Change-Id: I68ff4cffa2bfab6a15299795c3e1837fc9b85806
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-29 15:59:13 +00:00
Elyes HAOUAS 363b77177e nb/intel/pineview: Use system_reset()
Use already defined system_reset() function.

Change-Id: I32c731de0c30940d15fd01fec6f10b3b33c04370
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-29 15:58:43 +00:00
Elyes HAOUAS d45f33804d nb/intel/nehalem: Use system_reset() and full_reset()
Use already defined system_reset() and full_reset() functions.

Change-Id: Ib7e399b5186aa704d0388c4a4b18480f2e3799f3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-29 15:58:34 +00:00
Elyes HAOUAS 82d4642805 nb/intel/haswell: Use system_reset()
Use already defined system_reset() function.

Change-Id: I436f62c4402736fb74c59d8b359d0b3963f0e659
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-29 15:58:24 +00:00
Elyes HAOUAS b559b3c785 nb/x4x: Use system_reset() and full_reset()
Use already defined system_reset() and full_reset() functions.

Change-Id: I0a05f3ac5c5340a509024de2b444960f498c3e99
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-29 15:58:13 +00:00
Julius Werner cee06c458a rockchip/rk3399: Select VBOOT_MIGRATE_WORKING_DATA
Trusted Firmware places some components in SRAM on RK3399 and therefore
restricts accesses to SRAM to the secure world. This makes the vboot
working data inaccessible to normal world payloads, so we need to
migrate it into CBMEM.

Change-Id: Ic7c95790f2f118ccbdd897550f13b5f987bdd831
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
2019-04-29 12:28:57 +00:00
Tristan Shieh 3d96f60409 mediatek: Add function to raise the CPU frequency
Implement mt_pll_raise_ca53_freq() in MT8183 to raise the CPU frequency.
Move the function declaration to common header.

BUG=b:80501386
BRANCH=none
Test=Boots correctly on Kukui

Change-Id: Ide8d767486d68177fa2bfbcc5b559879eca1bcda
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-29 12:27:24 +00:00
Tristan Shieh d95425c51a mediatek/mt8183: Set CPU frequency to 1417MHz
With the default CPU voltage (0.8v), CPU frequency should be 1417Mhz at
most. We have to raise CPU frequency to 1989MHz after increasing CPU
voltage to 1.05v in romstage.

BUG=b:80501386
BRANCH=none
Test=Boots correctly on Kukui

Change-Id: I4c3e0fa27ccda8e0efe422b6ab503a1efb1697e9
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-29 12:26:02 +00:00
Joel Kitching 4114aa8375 vboot: specify NEED_VB20_INTERNALS when needed
NEED_VB20_INTERNALS should always be specified when peeking
into vboot internal data structures.

BUG=b:124141368, chromium:956474
TEST=make clean && make test-abuild
BRANCH=none

Change-Id: I5a47a28350fd5a68efeff0d06ca150c1ae145412
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-29 12:24:17 +00:00
Duncan Laurie 053de0d812 mb/google/sarien: Update GBB flags
Disable the GBB flag forcing manual recovery now that we can read
the manual recovery from H1.

Enable the GBB flag to skip EC software sync, since images built
from coreboot.org do not include the EC binaries by default.

Change-Id: I0e1d6304e3e29eda68c7b807cf0774275c37d710
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-29 12:23:40 +00:00
Nico Huber 9a1d057f5f Revert "soc/intel/common/block: add VMX support"
This reverts commit 9aae51ad11.

Proper code in cpu/intel/common/ shall be used instead.

Change-Id: I4a5d558b03497d106083eece10c5b34e0e7cbb2d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29683
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-29 12:22:58 +00:00
Jett Rink c426be6ae2 arcada: add internal pull to ISH UART RX
We do not want the RX signal to be floating on the board as that could
cause the ISH to remain in a higher power state (because there is logic
to keep the ISH in an higher power state when there is an active UART).

Add an internal 20K pull up on the RX line. In normal configuration this
will burn an additional 544uW.

BRANCH=R75
BUG=b:131241969
TEST=verify that ISH console still works with rework

Change-Id: Ifc9621bcafe4c86edfa9cd6d58b307254d3a81ca
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-04-29 12:21:53 +00:00
Maxim Polyakov 5806665059 soc/skl: set IGD resources only if device is enabled
If the Intel IGD device pci 02.0 is disabled or undefined in
the device tree, then internal graphics pre-allocated memory
and GFX-VT MMIO memory for virtualization won`t be allocated
in the SoC address space.

Thus, patch resolves the FSP-S hang problem on Skylake/ Kaby
Lake processors when the IGD device is disabled. This should
provide to run FSP 2.0-based coreboot on these CPUs families
without integrated graphics card.

The following boards were used for testing:

- Asrock H110M-DVS board (desktop i5-6600) & NVIDIA GTX 1060
  as external GPU.

  Virtualization and GFX 3D acceleration with nouveau driver
  still works well  (tested on VirtualBox 5.1.38 with Ubuntu
  18.04.1 as guest and host OS)

- Intel KBL-R U RVP board (mobile i5-8350u) without GFX.

Payload: tianocore edk2-stable201811-216-g51be9d0.

Change-Id: Id7a0cba582d83e3fe7e8d20342ee219cdd369a53
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32467
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-29 12:20:43 +00:00
Jiaxin Yu 5a69491a01 mediatek/mt8183: Init audio related clock
Enable audio clock, intbus clock, infra clock and mtkaif
26m clock.Needed by audio playback in firmware.

BUG=b:117254418
BRANCH=none
TEST=Build pass and verified on kukui p1 board

Change-Id: I88060d9796cc23ad7f524943f36869e1ec85073d
Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-04-29 12:19:49 +00:00
Gaggery Tsai da79f5c91d mb/google/sarien: Add psys_pmax setting to 136W
This patch adds the setting of psys_pmax to 136W. According to the
design, Rpsys is 11.8Kohm. Here is the equation to come out the
Psys_pmax value: Psys_pmax * 1.493uA/W * 11.8Kohm / 2 = 1.2V
Hence, Psys_pmax is 136W.

BUG=b:124792558
BRANCH=None
TEST=emerge-sarien coreboot chromeos-bootimage & Ensure the value is
     passed to FSP by enabling FSP log & Boot into the OS

Change-Id: Id3f6be5f0c2346a7763195a992c0ae45faede056
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-04-29 12:19:18 +00:00
Karthikeyan Ramasubramanian f81c589ad2 soc/intel/apollolake/bootblock: Clear the GPI IS & IE registers
Clear the GPI Interrupt Status & Enable registers to prevent any
interrupt storms due to GPI.

BUG=b:130593883
BRANCH=octopus
TEST=Ensure that the Interrupt status & enable registers are reset
during the boot up when the system is brought out of G3, S5 & S3. Ensure
that the system boots fine to ChromeOS.

Change-Id: Ia3b9d3bf08472219348e20b53bae470c589039fb
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-29 12:18:54 +00:00
Karthikeyan Ramasubramanian 3391a31cf9 soc/intel/common: Add support to clear GPI IS & IE registers
Add support to reset the GPI Interrupt Status & Enable registers so that
the system does not experience any interrupt storm from a GPI when it
comes out of one of the sleep states.

BUG=b:130593883
BRANCH=None
TEST=Ensure that the Interrupt status & enable registers are reset
during the boot up. Ensure that the system boots fine to ChromeOS.

Change-Id: I99f36d88cbab8bb75f12ab1a4d06437f837841cb
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-29 12:18:44 +00:00
Karthikeyan Ramasubramanian c126084bc5 soc/intel: Add GPI interrupt config register offset info
Add the offset information for GPI interrupt status and enable register
in the pad_community structure. Populate the concerned information for
individual SoCs. This offset information is required to clear the
interrupt configuration during the bootup.

BUG=b:130593883
BRANCH=None
TEST=Ensure that the interrupt configuration are cleared during bootup.
Ensured that the system boots to ChromeOS.

Change-Id: I8af877a734e8d49b700d720b736da8764985a8f8
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-29 12:18:27 +00:00
Elyes HAOUAS c056729bfd nb/intel/sandybridge: Use system_reset()
Use already defined system_reset() function.

Change-Id: Ic4716a3bb1dc6c6b29a028fc0ab28f9195f08416
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-04-29 11:57:45 +00:00
Frans Hendriks bac27d5ebb soc/intel/braswell: Move LPE ACPI code to mainboard
The ACPI code of LPE device is included regardless of the
availability of the LPE controller.
Linux remains requesting the status of device LPEA even if
this device is disabled.

Include ACPI LPE controller code at Braswell mainboards with
LPE enabled.

BUG=N/A
TEST=Linux 4.17+ on Portwell PQ7-M107

Change-Id: Ic8acf9ea9e9b0ba9b272e20beb2023b7a4716a73
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-04-29 08:35:20 +00:00
Paul Fagerburg a1b187ab29 mb/google/hatch/variants/baseboard: remove unused dqs_map
The dqs_map array is used only for LPDDR3 and LPDDR4. It is not used for
DDR4, and so it can be removed from the baseboard memory initialization
code.

BRANCH=none
BUG=b:129706819
TEST=ensure the firmware builds without error; I don't have hardware
available to test this just yet.

Change-Id: I07fac3097d68f37b4630d3f0010f987da2f03bd7
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32484
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-29 03:47:48 +00:00
Paul Fagerburg d3d41b348d mb/google/hatch/variants/kohaku: Add support for LPDDR3 configurations
First configuration supported is 8 GB system memory:
4 x 2 GB (K4E6E304ED-EGCG).

BRANCH=none
BUG=b:129706819
TEST=ensure the firmware builds without error; I don't have hardware
available to test this just yet.

Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: Ibd92d585118ff75492e8a7188dcdb2a286836d56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-29 03:47:29 +00:00
Paul Fagerburg cb42f4d467 soc/intel/cannonlake: Modify dq_map to provide for 6 entries
Intel's DQ_DQS_RComp_Info_Utility generates data for 6 entries. MRC will
return errors if we don't have all 6 entries in the map.

BRANCH=none
BUG=b:131103736
TEST=ensure the firmware builds without error; I don't have hardware
available to test this just yet.

Change-Id: I20a768de0e4440d7dde7b717794c4e2d0c62819c
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-29 03:45:53 +00:00
Lukasz Siudut e54c15aa72 mb/ocp/monolake: add TPM and IPMI support
Changes includes:

- enable TPM1 + add entry in devicetree
- configure LPC IO to make IPMI work + add entry in devicetree
- introduce DSDT and SMBIOS entries for IPMI to make it detectable
  by ipmi_si driver

Signed-off-by: Lukasz Siudut <lsiudut@fb.com>
Change-Id: Ia975643064075f1f861f4ead6f24ed71f345ea04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-04-28 00:26:38 +00:00
Duncan Laurie a2e7ee729e mb/google/sarien: Enable LTR for PCIe NVMe root port
Enable LTR for NVMe so it can use ASPM L1.2.

BUG=b:127593309
TEST=build and boot on sarien and check L1 substate with lspci
before: L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2- ASPM_L1.1+
after:  L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+

Change-Id: I9842beda6767f758556747f83cfcedbd00612698
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com>
2019-04-26 20:07:54 +00:00
John Zhao 76e70675d9 ACPI: Add RHSA and ANDD structures for DMAR table
Remapping Hardware Status Affinity (RHSA) structure is applicable for
platforms supporting non-uniform memory. An ACPI Name-space Device
Declaration (ANDD) structure uniquely represents an ACPI name-space
enumerated device capable of issuing DMA requests in the platform.
Add RHSA and ANDD structures support for DMAR table generation.

BUG=b:130351429
TEST=Image built and booted to kernel

Change-Id: I042925a7c03831061870d9bca03f11bf25aeb3e7
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-26 18:03:52 +00:00
Nico Huber 44c6cf67c3 soc/intel/apl/acpi: Do not report 8259 PICs
The IRQ tables don't support this path, so we shouldn't report presence
of the legacy PICs. As the _PIC method is optional and we ignore the
passed parameter anyway, drop it.

Change-Id: I51301a600e16f74fde00fdcb4595e1f47a52e207
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
2019-04-26 16:58:47 +00:00
Elyes HAOUAS c3385070d6 soc/{amd,intel}/chip: Use local include for chip.h
Change-Id: Ic1fcbf4b54b7d0b5cda04ca9f7fc145050c867b8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-26 16:49:13 +00:00
Nico Huber 9df72e0471 x86/acpi: Add Kconfig to toggle 8259 reporting
Change-Id: If3c9783ebc41c103c915788139d91644b805f397
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-04-26 16:43:17 +00:00
Duncan Laurie 3be4c7ba64 Revert "mb/google/arcada: Add settings for noise mitgation"
This reverts commit 77fb3632a4.

Reason for revert: This change inadvertently added a submodule.

Change-Id: I6cc2a3cd9d88986a2599a5ff2e5a066b1396a8c0
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32472
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-26 14:38:49 +00:00
Gaggery Tsai 56d66ae854 mb/google/poppy/variants/atlas: Revise AC/DC loadline
This patch revises the AC/DC loadline settings because some major
layout changes between proto and evt boards.

BUG=b:130740639
BRANCH=None
TEST=emerge-atlas coreboot chromeos-bootimage and boot to the OS.

Change-Id: Iea12c621e7fab427a0de8f43f0290bf01d0c5a09
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
2019-04-26 09:20:37 +00:00
Raul E Rangel a11553dabd soc/amd/stoneyridge: Generate MCFG table
BUG=crbug:948241
TEST=Booted and decompiled the table
[000h 0000   4]                    Signature : "MCFG"
[004h 0004   4]                 Table Length : 0000003C
[008h 0008   1]                     Revision : 01
[009h 0009   1]                     Checksum : 15
[00Ah 0010   6]                       Oem ID : "COREv4"
[010h 0016   8]                 Oem Table ID : "COREBOOT"
[018h 0024   4]                 Oem Revision : 00000000
[01Ch 0028   4]              Asl Compiler ID : "CORE"
[020h 0032   4]        Asl Compiler Revision : 00000000

[024h 0036   8]                     Reserved : 0000000000000000

[02Ch 0044   8]                 Base Address : 00000000F8000000
[034h 0052   2]         Segment Group Number : 0000
[036h 0054   1]             Start Bus Number : 00
[037h 0055   1]               End Bus Number : 40
[038h 0056   4]                     Reserved : 00000000

Change-Id: I46dc1959971af4685a7ffd285429175d6882ae86
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-04-26 01:55:12 +00:00
Arthur Heymans 74f9fe6e58 cpu/intel/car/non-evict: Select NO_FIXED_XIP_ROM_SIZE
CPU's featuring a non eviction mode cache the whole ROM.
Therefore XIP stages don't need to follow some alignment constraints.

Change-Id: I4a30f31baa0f90279c0690ceb6aefea6de461bd9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-04-25 15:56:28 +00:00
Elyes HAOUAS 5417c84f7d soc/cavium/common/bootblock: Remove unused variables
Change-Id: I4835ca3e20f2e53598bfc77b633aca946d3fde9c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-04-25 15:55:27 +00:00
Elyes HAOUAS d84e20b33c src/lib/selfboot: Remove unused variables
Change-Id: I8d80084095912c30bfd8fc100bf27b522485a08a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-04-25 15:55:21 +00:00
Elyes HAOUAS 6ee9ee4cab drivers/spi/sst: Remove unused variables
Change-Id: Ic6eb9c7dbfc5fde97f0f45f09431c617cb850c38
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-04-25 15:55:10 +00:00
Elyes HAOUAS 05c0455699 device/dram/ddr3: Remove unused variable
'param' variable is unused because 'printram' function only expands to
something in debug builds (not default ones).

Change-Id: I0cdf34cbb9aaed5045db5294eeefeaac642aeb1a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32428
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-25 15:55:02 +00:00
Elyes HAOUAS d5d433e07f src/southbridge/intel: Remove unused variables
Change-Id: I3b5092aa076b9693f78c86ffb9b99805696bb0bb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-04-25 15:54:38 +00:00
Elyes HAOUAS f4ed5dc7f4 src/southbridge/amd: Remove unused variables
Change-Id: I143f3395a385e170cce0979707d6a7f61107f40b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-04-25 15:54:35 +00:00
Elyes HAOUAS a4a9ad58ba src/soc/intel: Remove unused variables
Change-Id: Ie81377a31e6527c5fd5aaea99f08527912e870a0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-04-25 15:54:30 +00:00
Elyes HAOUAS 358ec83d03 northbridge/via/vx900: Remove unused variables
The `printram` function only expands to a value only in debug builds.
This isn't done in default builds.

Change-Id: Ic88c4cc730ae2d0d0718c7f71260cd2b45a3ddcd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-04-25 15:54:24 +00:00
Elyes HAOUAS 0f49dd26ad src/northbridge/intel: Remove unused variables
Change-Id: Idd339e324b833d2d024edb45e33c3d74af4473e8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-04-25 15:54:07 +00:00
Elyes HAOUAS d768e919ae src/northbridge/amd: Remove unused variables
Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-04-25 15:54:01 +00:00
Matt DeVillier 73b0136fa3 3rdparty/fsp: Update submodule pointer to upstream master
Update submodule pointer to pull in newly-updated Braswell FSP.

Adjust FSP_FD_PATH for soc/cannonlake due to filename case change.

Change-Id: I02ee0d32fd4c04cd4971eff20fc5a7de3f9b07ec
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-04-25 15:52:53 +00:00
Tim Wawrzynczak 7391fd8084 mb/google/hatch/: FPMCU not rebooted when DUT reboots
Add FP_RST_ODL to early GPIO table, configured as low, so that the FPMCU
will get reset when coreboot enters bootblock.

BUG=b:130229952
BRANCH=none
TEST=Compiles (no Hatch device w/FP to test)

Change-Id: I8a8d8cc2c560f6518337f7500575fdc2265b6347
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-04-25 15:52:32 +00:00
Tristan Corrick 478a1212ef mb/supermicro/x10slm-f: Do SIO setup in bootblock
Lynx Point switched to doing mainboard-specific super I/O setup in the
bootblock with commit d893a2635f ("sb/intel/lynxpoint: Enable LPC/SIO
setup in bootblock"). The X10SLM+-F was added while that commit was in
review, and hence did not receive the necessary changes to SIO setup.

This patch has not been tested on hardware.

Change-Id: I7a648ec967dea2113cbbde1a93c1963ca6dd3c88
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-04-25 15:52:03 +00:00
Philip Chen 5849b14705 mb/google/hatch: Pull up GPP_C13 for hatch and hatch_whl
On EC end, we want to change this pin from push-pull to open-drain.
And since there is no external pull-up resistor on the board, we'll
have to configure this pin as internal-pull-up on AP end.

BUG=b:129306003
TEST=None

Change-Id: Ibc1f89fc25773220db009c6571400b01390dd756
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-25 15:48:17 +00:00
Marty E. Plummer 0987e43aa0 src/Kconfig: increase heap size if using flattened image tree
FIT support takes more heap memory than most coreboot payloads.

Change-Id: Id17f25e94d97e937b0e9a9cee3dd1a8aef1d525d
Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-24 20:42:52 +00:00
Tim Wawrzynczak c60a830e44 mb/google/kohaku: Update overridetree.cb
Add common SoC config.
Disable PCIe WiFi.
Add digitizer.
Turn off native SD card interface.
No WWAN.

Add DA7219 driver to Kconfig.

BUG=b:130310626
BRANCH=none
TEST=compiles (no Hatch ref or Kohaku device to test)

Change-Id: I17d5ba6ce4ec412384e4a1678474b8d26499ba40
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-24 17:12:38 +00:00
Tim Wawrzynczak 40dee3d506 mb/google/hatch: Move SD card detect GPIO.
Not all Hatch variants utilize the SoC's native SD card support. Move
the support to board-specific variants instead of the base device tree.

BUG=none
BRANCH=none
TEST=compiles (no Hatch device to test with)

Change-Id: Iae24114aad2c4d042c25da6f8cb740ccc8960082
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32417
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-24 16:34:38 +00:00
Furquan Shaikh 131134288b mb/google/hatch/var/kohaku: Skip UART0 config in FSP
Similar to hatch(CB:32278), this change sets SerialIo
config for UART0 to PchSerialIoSkipInit to skip initialization in
FSP.

This change also adds a device to kohaku override tree to ensure that
the settings in it take effect.

BUG=b:130310626

Change-Id: Ia25b45811be26d55fc0019e4cd22eb7310b5a4c4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-04-24 16:23:38 +00:00
Nathan_chen 77fb3632a4 mb/google/arcada: Add settings for noise mitgation
Enable acoustic noise mitgation for arcada platform,
the slow slew rates for Ia and Gt are fast time dived by 8.

BUG=b:131144464
TEST=waveform test and hardware validation result pass.

Signed-off-by: nathan chen <nathan_chen@wistron.corp-partner.google.com>
Change-Id: I37315ecfa245fce3085e62d1566ff037d8aa8ab4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32403
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-24 15:53:26 +00:00
Keith Short bb4759c15d mb/google/sarien: Disable POWER_OFF_ON_CR50_UPDATE
Disable the POWER_OFF_ON_CR50_UPDATE option on sarien/arcada.  This is
needed so that platform properly boots after doing a Cr50 firmware
update when running on battery.

BUG=b:126632503
BRANCH=none
TEST=Build coreboot on sarien/arcada.
TEST=Perform Cr50 firmware update on Sarien, confirm the platform boots
normally after sending TURN_UPDATE_ON to the Cr50.

Change-Id: I0b687285eb95070eaffb68611a7d98eb8434ce2c
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-24 15:53:20 +00:00
Keith Short 97f8029ad4 security/tpm: Change POWER_OFF_ON_CR50_UPDATE so it can be disabled
Modify the POWER_OFF_ON_CR50_UPDATE Kconfig option so that specific
mainboard implementations can disable the option.

BUG=b:126632503
BRANCH=none
TEST=Build coreboot on sarien/arcada.
TEST=Perform Cr50 firmware update on Sarien, confirm the platform boots
normally after sending TURN_UPDATE_ON to the Cr50.

Change-Id: I3beefaae21de61e53ae232dbdc8ea9dbb2c78cd5
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-24 15:53:08 +00:00
Eric Lai 1a1fe6e384 mb/google/sarien: Add power control for Sarien touchscreen
This change will save touchscreen power leakage 2-3mW in S0iX and
increase T2 display time delay to meet display panel requirement.

BUG=b:129899315
TEST= Measure touchscreen power from Sarien during S0iX

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I48419132ba734f20ad5cf484c2dda609570a6dd0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32330
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-24 15:52:40 +00:00
Eric Lai 389f927751 mb/google/sarien: Remove touch VPD support and Melfas HID touch
Sarien will change Melfas from HID to I2C and change address from
0x10 to 0x34. So we don't need VPD to separate Elan and Melfas
anymore.

BUG=b:131194574
TEST=boot up and check no Melfas HID device exist

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ic002f61b226743e1c18dbdbc51ce8b733916d8a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32437
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-24 15:52:17 +00:00
Eric Lai 18060d7d92 mb/google/sarien: Disable touch by strap pin GPP_B4
We want to disable touch for non-touch sku. We can use
strap pin GPP_B4 to identify it is connected with touch
or not.

touch sku: GPP_B4 is low
non-touch sku: GPP_B4 is high

BUG=b:131132419
TEST=boot up and check no touch device exist

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: If6681262c25e4b01e061a8520e38905d40345509
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32438
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-24 15:51:22 +00:00
Tristan Shieh d228c1ef32 mediatek/mt8183: Set CPU frequency to 1989MHz
Set CPU frequency from 1100MHz to 1989MHz to improve booting time.

BUG=b:80501386
BRANCH=none
Test=Boots correctly on Kukui

Change-Id: Id41c7ea8905c4db2537a5c32f96eb7c6b2c008ea
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32397
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-24 10:22:17 +00:00
Tristan Shieh dcb2eef582 mediatek/mt8183: Set processor voltage to 1.05v
The maximum CPU frequency is 1417MHz with current processor voltage
(0.8v). Set processor voltage to 1.05v for higher CPU frequency.

BUG=b:80501386
BRANCH=none
Test=Boots correctly on Kukui

Change-Id: I24ecdac2c85d3f012d9235449c0d727d727dc185
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-04-24 10:22:12 +00:00
Lijian Zhao f9c9fa2df8 mb/google/sarien: Toggle SSD reset pin on DVT2
SSD reset pin had been added on DVT2, the power sequnence requires
toggle in boot stage.

BUG=b:130741066
TEST=Boot up with simulated DVT2 platform and confirm SSD can be
detected during warm reboot.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ie734875a49b8b61f8b813c473d30cbcaf4dd13d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32434
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-24 03:16:57 +00:00
Tony Huang 8725e5f639 mb/google/octopus: I2C clock tuning for bloog
Tune I2C params for I2C buses 5, 6, and 7 to ensure that the
frequency does not exceed 400KHz.

BUG=b:131132499, b:128998988
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage and measured frequency
under 400 KHz

Change-Id: Ie8cfba72a0654402ccb0274c00b44fbfa2deea21
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-24 00:55:32 +00:00
Tony Huang 283fdcfbc2 mb/google/octopus/variants/bloog: Add goodix touchscreen support
Add goodix touchscreen support

BUG=b:131082228
BRANCH=octopus
TEST=emerge-octopus coreboot and verify that touchscreen works on
bloog.

Change-Id: I0b3b481ca806b6452d67ace5dfe53f12a14ac3be
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2019-04-23 22:47:04 +00:00
Patrick Georgi c323963bed soc/qualcomm/qcs405: add console.h include
Change-Id: I556d00e8b06f631a5ca51ae2b5ba646e5f536480
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32422
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23 19:48:34 +00:00
Taniya Das 4b766393e2 qcs405: Add support of GPIO IRQ APIs
Add support of GPIO IRQ APIs.

Change-Id: I11715a93999012622a5e28455731cbe249ba8f2c
Signed-off-by: Shefali Jain <shefjain@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-23 18:01:06 +00:00
Taniya Das 3ee485741b qcs405: clock: Update SPI API
Update SPI enable/disable and configure clock
API for supporting all the blsp and qup for qcs405.

Change-Id: I39622571cb671f62312283a010129ceecb654f61
Signed-off-by: Shefali Jain <shefjain@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-23 18:00:52 +00:00
Patrick Georgi 27fbbcffc5 nb/intel/sandybridge: add pch.h include
Fixes src/northbridge/intel/sandybridge/raminit_mrc.c:286:3: error:
implicit declaration of function 'enable_usb_bar'

Change-Id: I48bf59c56b518477a3fc0d75902fc58df6b7def7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32400
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23 10:52:09 +00:00
Patrick Georgi 39c3d3951a soc/intel/cannonlake: add missing console.h include
Change-Id: Ic23eb57a4096d4301d7f9478d8e65aaeb233de7b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32399
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-04-23 10:52:02 +00:00
T Michael Turney 19fcc89fe0 lib/fmap: Add area read/write functions
Change-Id: I7669b8dc07b1aa5f00e7d8d0b1305b3de6c5949c
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-23 10:22:54 +00:00
Keith Short 00dbf449c9 coreboot: Run mainboard specific code before Cr50 reset
When coreboot checks the TPM and key-ladder state it issues a reboot of
the Cr50 with a delay parameter.  Older Cr50 code doesn't support the
delay parameter and reboots immediately, which prevented coreboot from
running the mainboard specific code needed for the AP to come back up.

This change calls mainboard_prepare_cr50_reset() prior to sending the
VENDOR_CC_IMMEDIATE_RESET command.

This change also fixes a false error message from the coreboot log that
indicated "Unexpected Cr50 TPM mode 3" when the Cr50 key ladder is
disabled.

BUG=b:130830178
BRANCH=none
TEST=build coreboot on sarien and grunt platforms.
TEST=Load Cr50 v3.15, run 'gsctool -a -m disable; reboot'.  Verify
corebot send the
VENDOR_CC_IMMEDIATE_RESET command and that the AP boots normally.
Verify event log shows "cr50 Reset Required"
TEST=Force Cr50 automatic update.  Verify event log shows "cr50 Update
Reset".

Change-Id: Ib05c9cfde8e87daffd4233114263de5b30822872
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-23 10:21:24 +00:00
Lijian Zhao c5d734b3f9 soc/intel/common/acpi: Add dynamic method around sleep
Declare plaform level hook method before and after system sleep for
possible power management related usage.

BUG=N/A
TEST=pass with make what-jenkins-does

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ie63711748b6dbb99d34910824f2059464543e162
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32366
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23 10:20:29 +00:00
Elyes HAOUAS 31438f73c0 cpu/intel/speedstep/acpi: Use get_ia32_fsb_x3() function
Change-Id: Ie8c5d5f7dd5b43becc144fd5e62d7de2f1ed3b80
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31432
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23 10:19:37 +00:00
Arthur Heymans 3c61304a9f arch/x86/car.ld: Make the vboot tpm log symbols conditional
Without VBOOT_MEASURED_BOOT there is no need for these symbols.

Change-Id: I96391b7817c79f760713c67bc469164b5514879e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-23 10:18:09 +00:00
Elyes HAOUAS 01912201a4 nb/intel/i945: Check if interleaved even if rank #4 size is zero
Tested config:
Interleaved (config; status before, after):
 DIMM{0 + 2}: ok, ok
 DIMM{0 + 3}: Nok, ok
 DIMM{1 + 2}: ok, ok
 DIMM{1 + 3}: Nok, ok
 DIMM{1 + 2 + 3}: ok, ok
 DIMM{0 + 2 + 3}: ok, ok
 DIMM{0 + 1 + 2}: ok, ok
 DIMM{0 + 1 + 3}: Nok, ok

Not Interleaved:
 DIMM{0 + 1 + 3}: Nok, Nok
 DIMM{0 + 1 + 2}: ok, ok (with single ranked)
 DIMM{0 + 1 + 2}: Nok, Nok (with only dual ranked)
 DIMM{0 + 2 + 3}: Nok, ok
 DIMM{1 + 2 + 3}: ok, ok

Change-Id: Ibf130a3d4b6f8fa816f7a5f06822a9b8807be3d4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-23 10:13:34 +00:00
Matt DeVillier d6d6771b97 sb/intel/bd82x6x: fix linking for non-native raminit case
Commit 45d4b17 [nb/intel/sandybridge: Move southbridge code to bd82x6x]
moved early_pch_init() to the southbridge, but failed to include
early_pch.c for the non-native raminit case, which now fails to link.
As all boards default to native raminit, this was missed by the autobuilder.

Adjust early_pch.c to be compiled regardles of ram init type used

Test: build/boot google/stout with MRC ram init selected

Change-Id: I50db30fda9a1099fb434c04ea97bcc38f8455233
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-04-23 10:13:14 +00:00
Elyes HAOUAS 420d7e009d ich7/i945: Use full_reset()
For full reset, use already defined full_reset() function.

Change-Id: Iec7dcf285f3cb1cdc8f48d348ff8496879625db5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-04-23 10:12:24 +00:00
Arthur Heymans d893a2635f sb/intel/lynxpoint: Enable LPC/SIO setup in bootblock
This allows for serial console during the bootblock and enables
console in general for the bootblock.

Change-Id: I5c6e107c267a7acb5bf9cbeb54eb5361af3b6db4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30315
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23 10:12:02 +00:00
Kyösti Mälkki 63bc18e328 soc/amd/common: Remove AmdReadEventLog()
Parameter passing is incorrect here, it should pass
complete StdHeader instead of attempting to fill
in HeapStatus that should be treated as a field private
to AGESA, based on where it is defined in the header
files.

Furthermore the while() loop did not evaluate the
return value. Feature can be brought back at a later
date after someone verifies it actually works correctly
across different stages.

Change-Id: Ib243b275f8700ecaeb330772c795d305c61899c5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31484
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23 10:10:45 +00:00
Kyösti Mälkki 6e512c4d7a soc/amd/common: Introduce agesa_execute_state()
Each entrypoint to AGESA goes through the same sequence
and have same the function signature.

To avoid introducing bunch of preprocessor magic, rename
all the agesawrapper_amdXXX() functions that are actual
entrypoints to AGESA API, make them static, and provide
a single exposed entry function agesa_execute_state().

Change-Id: I96ae1874132da3843aa42c2f4e8a59ec771d3893
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31483
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23 10:10:34 +00:00
Roy Mingi Park ba851170fb mb/google/sarein: Add power control for Arcada touchscreen
This change will save touchscreen power leakage 2-3mW in S0iX and
increase T2 display time delay to meet display panel requirement.

BUG=b:129899315
TEST= Measure touchscreen power from Arcada during S0iX

Change-Id: I4b8f3fdc0d107b080c5febe6fa5d29ea5d1ed0fc
Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-04-23 10:10:19 +00:00
Lijian Zhao e98a751823 smbios: Add memory type 9 system slot support
Add SMBIOS type 9 system slots into coreboot, the definiation is up to
date with SMBIOS spec 3.2

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ibcfa377c260083203c1daf5562e103001f76b257
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-23 10:09:35 +00:00
Kane Chen 3717256d5a soc/intel/cannonlake: Enable PlatformDebugConsent by Kconfig
This change is mainly to control PlatformDebugConsent FSP UPD.
PlatformDebugConsent is enabled if SOC_INTEL_CANNONLAKE_DEBUG_CONSENT != 0.
PlatformDebugConsent in FspmUpd.h has the details.

BUG=b:130203864
TEST=boot ok and PlatformDebugConsent can be controlled by Kconfig

Change-Id: Ib845b5e42bc78fb352a0c97c6301f2aeca522f29
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32297
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23 10:08:57 +00:00
Kane Chen f5e8b29be6 soc/intel/common: Add SOC_INTEL_DEBUG_CONSENT to control debug interface
SOC_INTEL_DEBUG_CONSENT config is generally to enable default debug
interface of SoC.

Ex: USB DBC, DCI debug interface on cnl, whl, cml.

Change-Id: I313d80d6c63fd37164c63f78e9e69d3cb4a5566b
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32337
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23 10:08:45 +00:00
Frans Hendriks 0556f6132b soc/intel/braswell/acpi/lpss.asl: Remove SPI1 and PWM asl code
Linux remains using SPI1 and PWM ASL even if these devices are disabled.
SPI1 and PWM are disabled by Intel FSP.
Remove ASL code.

BUG=N/A
TEST=Boot Ubuntu on Intel CherryHill CRB

Change-Id: Iec2ca7520081d00bf7a53d58ee054aa6f23e5606
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2019-04-23 10:07:38 +00:00
Elyes HAOUAS 34564ed154 ACPI: Clarify serial bus revision and specific revision
Serial bus revision [Byte 3] and serial bus specific revision [Byte 9]
are not the same.

Change-Id: I366f62e6aa0e9c0dfbc1ec17adeebc42a0e777eb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-04-23 10:06:35 +00:00
Patrick Rudolph da9302a2c4 nb/intel/sandybridge: Drop pch.h from sandybridge.h
Include pch.h in the source files instead in sandybridge.h.

Tested on Lenovo T520 (Intel Sandy Bridge).
Still boots to OS, no errors visible in dmesg.

Change-Id: I9e5b678e979a8d136d8d00b49486d0a882f77d81
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-04-23 10:06:01 +00:00
Aamir Bohra 78fbe3d831 soc/intel/cannonlake: Add null reference check for Cnvi and Xdci
Change-Id: I2e1011d9ac93ed764b6c2aa425928a972ec2aa43
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32322
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23 10:04:42 +00:00
Elyes HAOUAS cd4fe0f718 src: include <assert.h> when appropriate
Change-Id: Ib843eb7144b7dc2932931b9e8f3f1d816bcc1e1a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/26796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: David Guckian
2019-04-23 10:01:36 +00:00
Elyes HAOUAS 351e3e520b src: Use include <console/console.h> when appropriate
Change-Id: Iddba5b03fc554a6edc4b26458d834e47958a6b08
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: David Guckian
2019-04-23 10:01:21 +00:00
Elyes HAOUAS 20eaef024c src: Add missing include 'console.h'
Change-Id: Ie21c390ab04adb5b05d5f9760d227d2a175ccb56
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-04-23 10:00:39 +00:00
Elyes HAOUAS 7118701e96 sb/intel/i82801gx/lpc: Use {read,write}_pmbase32 and lpc_get_pmbase
Also use macros instead of magic numbers.

Change-Id: I00bd687c487894c72d4e4363774dbcdfaf62dd54
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-23 09:59:34 +00:00
Arthur Heymans 7a50554e29 src/mainboard/{foxconn/d41s,intel/d510mo}: Use pci_or_config
The pci_or_configx function makes the code shorter and more readable.

Change-Id: Ic1ba250f8ac9fb75cf3252aec18af80842bda7dd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-04-23 09:57:39 +00:00
Thejaswani Putta 6f5225c7e0 Klocwork: Fix the Null pointer derefernce found by klocwork
Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com>
Change-Id: I15973ac28e9645826986cf63d2160eedb83024e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32290
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23 09:56:37 +00:00
Sheng-Liang Pan 8b784004d3 mb/google/octopus: Add keyboard backlight support for Droid/Blorb
Droid/Blorb supports keyboard backlight feature, so enable the ASL code.

BUG=b:130330141
BRANCH=octopus
TEST=Build and boot to OS, verify that the string 'KBLT' is in the DSDT.

Change-Id: I74684e3905d34b61fa4b851798dbca018f986e5a
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-23 09:53:58 +00:00
Lijian Zhao 7f1a0e6b4c Revert "soc/intel/cannonlake: Enable coreboot MP PPI service for WHL/CML"
This reverts commit 41dad286d8. The change will make s0ix fail on Sarien/Arcada Platform.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I169bc6f41fba82fcf515267e8e1d08aa5ee2dce4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32391
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-22 21:35:45 +00:00
Hung-Te Lin 69eae2762f board/kukui: Support ADC value for NC
When the components like LCM ID are not installed (i.e., NC), ADC will
return some value with much larger variation from standard value (out of
the tolerance we set). To support that, we should check tolerance only
on non-NC voltages.

Also improve the error messages so we can see the ADC raw values
instead of simple assertion error (which makes debugging more difficult
since we have to build another firmware image just to print the values).

BUG=None
TEST=Booted on Kukui and got correct SKU ID for NC LCMID.
BRANCH=None

Change-Id: I8d00956e0e3b48ddbcaa505dd3ade24720c3b4ad
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32353
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-22 19:56:23 +00:00
Roy Mingi Park e3f5f2155a mb/google/sarien: Configure both GPP_H12 and GPP_H13 for SSD on Arcada
Currently, Arcada only supports D3hot during S0iX and there is leakage
power around 5~10mW depending on SSD vendors.
To support D3cold for SSD during S0iX, one MOSFET will be added on DVT2
and two GPIOs are required to be configured.
GPP_H13 is to control SSD_SCP_PWR_EN(power enable) and GPP_H12 is to
control SSD reset.

BUG=b:130741066
TEST=Measure SSD power during S0iX from Arcada(DVT2)

Change-Id: I868590e9e85d5df07930a3681884e3fc3a5c4d50
Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32361
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-22 18:00:13 +00:00
Arthur Heymans c94ba798d6 arch/x86/car.ld: Also check mrc.bin heap for Ivybridge
Sandy- and ivybridge use the same mrc.bin that has the heap in an
awkward location.

Change-Id: If985a48c6703c8a86d8051e67595cf0fd409d99a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-04-22 13:40:14 +00:00
Felix Singer 1db39a4466 drivers/intel/fsp2_0: Set basename for FSP binaries
Since there is no standardized naming scheme for the
FSP binaries, the option USE_FSP_REPO can't be used
on some platforms, because some of the filenames differ
and the build process awaits "Fsp_*.fd" as filename.

As a workaround, add the option -n to SplitFspBin.py,
which defines the basename.

Change-Id: Idc684ad00033ffafd1090fc32b23549ce9603b4f
Signed-off-by: Felix Singer <migy@darmstadt.ccc.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30930
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-21 23:35:45 +00:00
Arthur Heymans 77d5e7481b nb/intel/haswell: Add an option for where verstage starts
Previously Haswell used a romcc bootblock and starting verstage in
romstage was madatory but with C_ENVIRONMENT_BOOTBLOCK it is also
possible to have a separate verstage.

This selects using a separate verstage by default but still keeps the
option around to use verstage in romstage.

Also make sure mrc.bin is only added to the COREBOOT fmap region as it
requires to be run at a specific offset. This means that coreboot will
have to jump from a RW region to the RO region for that binary and
back to that RW region after that binary is done initializing the
memory.

Change-Id: I3b7b29f4a24c0fb830ff76fe31a35b6afcae4e67
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/26926
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-21 23:32:37 +00:00
Arthur Heymans 8e646e74b3 cpu/intel/haswell: Use C_ENVIRONMENT_BOOTBLOCK
This puts the cache-as-ram init in the bootblock.
Before setting up cache as ram the microcode updates are applied.

This removes the possibility for a normal/fallback setup although
implementing this should be quite easy.

Tested on Google peppy (Acer C720).

Setting up LPC in the bootblock to output console on SuperIOs is not
done in this patch, hence BOOTBLOCK_CONSOLE is not yet enabled by
default.

Change-Id: Ia96499a9d478127f6b9d880883ac41397b58dbea
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/26859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-04-21 23:31:26 +00:00
Arthur Heymans c4772b9fd7 cpu/x86: Move checking for MTRR's as a proxy for proper CPU reset
Checking for empty MTRR_DEF_TYPE_MSR as a proxy for proper CPU reset
is common across multiple platforms. Therefore place it in a common
location.

Change-Id: I81d82fb9fe27cd9de6085251fe1a5685cdd651fc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-21 23:29:29 +00:00
Marshall Dawson 6d3b7e6f62 soc/amd/stoneyridge: Fix gnvs aoac initialization
Correct the SD and SATA assignments.

TEST=Boot Grunt
BUG=b:130788333

Change-Id: Ib75e1dbb0cd7f90a8d297d11d3a7c3bad47a8d21
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2019-04-21 23:14:45 +00:00
Arthur Heymans b328209330 nb/intel/nehalem: Hide some raminit output messages
Hide some debug output behind CONFIG_DEBUG_RAM_SETUP. That way the
pre-ram console does not overflow.

Change-Id: Idc425f4d10443f6ee7f9b4da67eb6542069cc40c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-20 04:27:01 +00:00
Elyes HAOUAS 4c15ea5bab mb/facebook/watson: Don't use deprecated IS_ENABLED
Change-Id: Ia4b7311f30f8ec951d02d3c31c30cf8895ed0eb2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-20 04:22:46 +00:00
Tony Huang 6cd9e631b0 mb/google/octopus/variants/baseboard: Disable unused I2C 1
I2C 1 is not being used in any of the octopus variants, so disable it.

BUG=none
BRANCH=octopus
TEST=Verify on meep and bloog
     reboot and s0ix suspend successfully

Change-Id: I7ed5065cfd0b9780d13feb27cc78b8090d7a03a6
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-04-20 00:55:54 +00:00
Nathan_chen 5397f194cc mb/google/arcada: Set psys_pmax to 140W
arcada is designed to operate at max power of 140 Watt. Hence set psys_max to 140W.

BUG=b:124792558
TEST=Build and boot arcada.

Change-Id: I280dfb81b3e25c7619a68db487e2b18867f52fda
Signed-off-by: nathan chen <nathan_chen@wistron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-04-20 00:55:07 +00:00
Elyes HAOUAS 75380d3a16 src/mb/Kconfig: Fix PCI subsystem IDs
References to MAINBOARD_PCI_SUBSYSTEM_{DEVICE_ID,VENDOR_ID} were removed
in commits

 dbd3132 sb/intel/{i82801g/i/j,bd82x6x}: Make use of generic set_subsystem()
 00bb441 sb/intel/lynxpoint: Remove PCI bridge function

Change-Id: I72bba8406eea4a264e36cc9bcf467cf5cfbed379
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32107
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-19 17:48:15 +00:00
Patrick Rudolph 8f70267607 smbios: Fix copy paste error
As reported by Coverity Scan CID 1400679.

Change-Id: I526b78a0697b7eb3c3dc75974c3a3a714b3d343f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32313
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-19 06:19:13 +00:00
Tim Wawrzynczak 64a6bcaa4e kohaku: mb/hatch/gpio: Scrub Kohaku GPIOs.
Ensure Kohaku GPIO pins are configured correctly w/r/t Hatch. Implement the
base/override model for GPIOs (regular and early).  The 'hatch' baseboard
contains the base GPIOs, and variants can override individual pads.

BUG=b:129707481
BRANCH=none
TEST=Compiles for all variants.

Change-Id: Ie5c83a0538d367ea11e9499f21cea41891d7a78e
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-19 03:05:05 +00:00
Lijian Zhao 395f1e328d soc/intel/cannonlake: Add report for iGD 0x3ea1
Integrated graphics id 0x3ea1 reported as unknown in bootblock stage,
make it correct.

BUG=N/A
TEST=Boot up into sarien platform and check with serial log, it shows
IGD: device id 3ea1 (rev 02) is Whiskeylake ULT GT1.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I2c4c697b108be7fa74736514ca71469a1ca29c22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-04-19 01:40:45 +00:00
Lijian Zhao 357e552562 soc/intel/common: Inject SMBIOS type 16 table
Add SMBIOS type 16 table for physical memory array, there's two item had
been left over.ECC and max capacity, as of now we set it to fixed value
as all the platform support by Intel common code don't support ECC
memory and so far the biggest capacity is 32GB.

BUG=b:129485635
TEST=Boot up with Sarien platform and check with dmidecode, the
following is the result:
Handle 0x000D, DMI type 16, 23 bytes
Physical Memory Array
        Location: System Board Or Motherboard
        Use: System Memory
        Error Correction Type: None
        Maximum Capacity: 32 GB
        Error Information Handle: Not Provided
        Number Of Devices: 2

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: If9c5831956ef273c84d831a2b1572b3442eed961
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32286
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-19 01:40:37 +00:00
Lijian Zhao fc5a3c949d mb/google/sarien: Update SMBIOS type17
Match SMBIOS type 17 device locator with motherboard silk screen,using
"DIMM-A" and "DIMM-B" instead of "Channel-0-DIMM-0" and 
"Chaneel-1-DIMM-0".

TEST=Boot up with sarien platform and run dmidecode to check SMBIOS
type 17 have expected output.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ie2125c0381bd24d96f725f68cde93a53da8c94c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-04-19 01:39:15 +00:00
Lijian Zhao 10ea93c334 smbios: Add type 17 device/bank locator override
Current SMBIOS type 17 device and bank locator string is like
"Channel-x-Dimm-x" and "Bank-x", x is deciminal number. Give silicon or
mainboard vendor a chance to replace with something matches with
silkscreen.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I54f7282244cb25a05780a3cdb9d1f5405c600513
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-04-19 01:39:03 +00:00
Lijian Zhao 83ad5a998d acpi: Upgrade acpi generate header
Sync acpigen.h content to match with laetst acpica, the link is
https://github.com/acpica/acpica/blob/master/source/include/amlcode.h,
and revision is 20190405. The purspose of the change is just make spec
up to date.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: If5f5da70eb66472ddf5df0d72ca85de41faac128
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-19 01:38:22 +00:00
Lijian Zhao f3ea181d98 mb/google/sarien: Update GPIO GPP_C23 setting
GPIO pin GPP_C23 is used as level trigger but not edge trigger, also it
is not inverted, correct it here. According to board schematic, GPP_C23
connected with 3.3v pull up, so the pin is low active.

BUG=b:128554235
TEST=Boot up arcada platform with stylus keep on touching the screen,
the touch screen is still functional once in OS stage. Without change,
touch screen is not functional at same scenario.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I2bee664198057e3997dda181a16b9a0388067036
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32347
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-19 01:37:47 +00:00
Duncan Laurie b34de93153 ec/google/wilco: Support board_id with EC provided ID
The EC can return a board ID value similar to the Chrome EC.
In order to use this for the board version returned by SMBIOS
this commit implements the board_id() function for mainboards
that use this EC.

BUG=b:123261132
TEST=Check /sys/class/dmi/id/board_version to see that it
is reflecting the value that the EC provides.

Change-Id: I3fbe0dc886701f37d2424fe7a2867fd860fa1ec0
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32276
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-18 23:43:06 +00:00
Duncan Laurie 91237d29c9 mb/google/sarien: Enable board_id feature
Enable the Kconfig option to automatically read the board ID
and populate it into the SMBIOS tables.

BUG=b:123261132
TEST=verify current board id from the OS:
cat /sys/class/dmi/id/board_version
rev1

Change-Id: Id41631bfaa627ca9d5034e2ebe93f8ace2ffdad8
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32277
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-18 23:42:35 +00:00
Duncan Laurie 1c968c135c ec/google/wilco: Send "logo displayed" progress code
This progress code enables keyboard backlight control that
otherwise would only work 30 seconds after boot.  This code
is already defined but it was not being sent by coreboot.
It is run in the "post device" step between the other defined
progress codes.

BUG=b:130754032

Change-Id: Ica6c622e568cb236c17bf3edb6639d0177510846
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-04-18 23:42:26 +00:00
John Zhao db3f0e3ebd soc/intel/cnl: Generate DMAR ACPI table
The platform supports Virtualization Technology for Directed I/O.
Generate DMAR acpi table if VT-d feature is enabled.

BUG=b:130351429
TEST=Booted to kernel and verified the DMAR table contents.

Change-Id: I4e1ee5244c67affb13947436d81628c5dc665c9e
Signed-off-by: John Zhao <john.zhao@intel.com>
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-04-18 10:15:55 +00:00
Patrick Rudolph 45d4b17f5e nb/intel/sandybridge: Move southbridge code to bd82x6x
Move the southbridge code to bd82x6x folder similar to the lynxpoint
implementation.

Tested on Lenovo T520 (Intel Sandy Bridge).
Still boots to OS, no errors visible in dmesg.

Change-Id: I8afc9f966033f45823f5dfde279e0f66de165e93
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-18 09:57:51 +00:00
Wisley Chen cbf27fd899 mb/google/octopus: Set default configuration to low for gpio_178
Set default configuration to low for gpio_178, and can remove the
override setting for bobba/bloog/fleex/meep/phaser.

For ampton, Change-Id I64a67f73564188ad0548a1a770169ef2bca47453 (
mb/google/ampton: Fix polarity of EN_PP3300_WLAN_L signal.)
modified the pin setting.

TEST=verified that boot into OS on meep board.
suspend/resume, reboot, and no failure found.

Change-Id: I7668ff4817edfca5c6cea63db779fcea21c7af92
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32247
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-18 01:03:05 +00:00
Hung-Te Lin 5c1fadbf0f google/kukui: Get write protection status from WP GPIO
Write protection (get_write_protect_state) was hard-coded to 0 and
should be fixed to read from correct GPIO (PERIPHERAL_EN0 from
schematics).

BUG=b:130681408
TEST=make -j; boots on Kukui Rev2.
BRANCH=None

Change-Id: I75b98b1d587abe5e8cdf3df28ea661bc1ffa19f9
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Joel Kitching <kitching@google.com>
2019-04-17 18:08:40 +00:00
V Sowmya 0873e27720 soc/intel/common: Add the audio PCI device ID for Cometlake
This patch adds the PCI device ID for cometlake in dsp.c

Change-Id: Ia28e3b9d1dc27ffcf24dfb2ef1efa9ae9c4027c8
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2019-04-17 16:43:03 +00:00
Subrata Banik 0a9be33a8a soc/intel/common/timer: Calculate TSC frequency based on CPUID 0x15
This patch ensures to follow Intel SDM Vol 3B Sec 18.7.3 to
calculate nominal TSC frequency.

As per SDM recommendation:
For any processor in which CPUID.15H is enumerated and
MSR_PLATFORM_INFO[15:8] (which gives the scalable bus frequency) is
available, a more accurate frequency can be obtained by using CPUID.15H

This patch also adds header file to capture Intel  processor model number.

BUG=b:129839774
TEST=Boot ICL platform and calculate TSC frequency using below methods
1. TSC freq calculated based on MSR 0xCE
tsc: Detected 1600.000 MHz processor

2. TSC freq calculated based on CPUID 0x15
tsc: Detected 1612.800 MHz TSC

Method 2 actually reduce ~25ms of boot performance time.

Note: Method 2 is recommended from gen 6 processor onwards.

Change-Id: I9ff4b9159a94e61b7e634bd6095f7cc6d7df87c7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2019-04-17 15:05:08 +00:00
Tristan Shieh a76e6542d1 mediatek: Use the 64-bit timer
GPT4 is a 32-bit timer and the counter of GPT4 will overflow in about
330 seconds (0xffffffff / 13MHz). Timer and delay functions will not
work properly if the counter overflows. To fix that we should use the
64-bit timer (GPT6).

BUG=b:80501386
BRANCH=none
Test=emerge-elm coreboot; emerge-kukui coreboot

Change-Id: I9f080e47253a1b1bab4636a45cb86c8666a25302
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
2019-04-17 04:32:26 +00:00
Ronak Kanabar 250dfc0256 soc/intel/cannonlake: Configure Vmx support using Kconfig
Change VmxEnable UPD values based on Kconfig ENABLE_VMX
and remove it from Devicetree and chip.h

Remove Vmx dependency on Vt-d

Change-Id: I4180c2270038a28befd6ed53c9485905025a15ba
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32117
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-16 14:38:17 +00:00
Ronak Kanabar a432f38e81 soc/intel/cannonlake: Implement soc side VMX support
Implement required soc side API to enable VMX support using CPU_COMMON

BUG=b:124518711
TEST= read msr 0x3a and verify vmx is enabled (value should be 5).

Change-Id: I33dbffa6301afabd688080751ba3b85a43e00156
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-16 14:37:53 +00:00
Patrick Rudolph e2f0a5f76c sb/intel/bd82x6x: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB
Use common code to detect ACPI S3.

Tested on Lenovo T520 (Intel Sandy Bridge) with Change
I8afc9f966033f45823f5dfde279e0f66de165e93 applied as well.
Still boots to OS, no errors visible in dmesg and S3 resume is working.

Change-Id: I283a841575430f2f179997db8d2f08fa3978a0bb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-04-16 08:58:50 +00:00
Patrick Rudolph ad0b48222f sb/intel/i82801ix: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB
Use common code to detect ACPI S3.
Untested.

Change-Id: I618d4c25adb0d2b9bbd59a3b3b84beac78db1916
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-04-16 08:58:41 +00:00
Subrata Banik 41dad286d8 soc/intel/cannonlake: Enable coreboot MP PPI service for WHL/CML
This patch performs MP initialization by FSP using coreboot MP
PPI service.

BUG=b:74436746
TEST=Able to perform MP initialization on WHL and CML platform.

Change-Id: I530d50e5aacc3cb9b625df14a50d4c5923e3fb4d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2019-04-16 02:14:38 +00:00
Hung-Te Lin 59a407349b google/kukui: Include LCD module identifier (LCM ID) into SKU ID
Kukui is using MIPI display panel and needs some identifier to tell
payloads which LCD module is installed, and to select right kernel
device tree. Following Scarlet, the decision is to embed LCD module ID
as part of SKU ID.

The LCM ID is using a different voltage mapping table from the rest.
Considering the complexity in computation of SKU ID, it is better to
move the cache logic from get_index to caller.

Also revise the mapping table since ADC on 8183 only supports 12
levels.

BUG=b:129299873
TEST=make -j; boots on Kukui Rev2 unit.

Change-Id: Ib0c00bc8ce3c71c445c5c4561403ce8ef4dd5844
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32263
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-15 22:05:46 +00:00
Werner Zeh 52b0ba22e9 mb/siemens/mc_apl4: Remove usage of external RTC
The external RTC was removed on the mainboard as it is not needed.
Remove the usage of the driver for RX6110SA as well.

Change-Id: Ia476e58c0b0f343d4e9e4fa6039bf82b194a87d3
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
2019-04-15 11:05:45 +00:00
Werner Zeh a4e5236e89 mb/siemens/mc_apl1: Enable HDA in devicetree for all mainboard variants
With commit
'4074ce0cc7 (intel/apollolake: Add HDA to disable_dev function)'
FSP is now requested to switch off HDA PCI device if it is disabled in
devicetree. Doing so results in a warm restart. Normally this event
will be stored in CMOS RAM (if the descriptor is configured to do so)
and therefore no further resets are requested by FSP on the next boots
as long as CMOS RAM is kept alive.

The Siemens mainboards based on Apollo Lake do not have a CMOS battery
and therefore the CMOS is not backed up. This leads to reset requests
from FSP after PCI enumeration on every boot. To avoid this reset enable
HDA in devicetree for these mainboards. Though we do not have any usage
of HDA it should not be an issue that the HDA device is now enabled. The
benefit is though that no reset is requested anymore by FSP.

Change-Id: I637c7c01d73350700c6066fee74fecbb5b93b221
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32295
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-15 11:05:34 +00:00
Rizwan Qureshi 43bb6554a2 mb/google/hatch: Update sleep signal assertion widths
Based on the power rail discharge times measured on hatch,
update the assertions widths that have to be programmed in SoC.

BUG=b:129328209
TEST=warm/cold reboot and S3 are working fine on hatch.

Change-Id: I3c6dce0a942e6dcd9e55ef5e58a7e9e8d2b0a1e3
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-15 05:58:05 +00:00
peichao.wang 2efee9df85 mb/google/octopus: Add custom SAR values for Laser
Laser would prefer to use different SAR values. Since Laser
sku id is 5.

BUG=b:130381493
BRANCH=octopus
TEST=build

Change-Id: I5cce38a191edfb235e274db3c788c58b65e0ebe1
Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32296
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-15 03:38:05 +00:00
Nico Huber ed23fed3f3 sb/intel/common: Fix config name in a comment
This sneaked in after we made unknown arguments to CONFIG() an error.

Change-Id: Ia1de78ce1d3277c7b094c3283455f4b56f3a3fbb
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32314
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-13 15:38:01 +00:00
Patrick Rudolph 425e75a2db sb/intel/i82801gx: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB
Use common code to detect ACPI S3.

Tested on Thinkpad X60.

Change-Id: Ia759a9ed141efc8130860300f2a8961f0c084d70
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-04-13 14:49:31 +00:00
Patrick Rudolph a3caa2d3bb sb/intel/lynxpoint: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB
Use common code to detect ACPI S3.

Untested.

Change-Id: I87ac56e4ba1fb83761786d5f32a0fc308ee9718a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32039
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-13 14:49:19 +00:00
Patrick Rudolph 0168639b9a sb/intel/i82801jx: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB
Use common code to detect ACPI S3.

Untested.

Change-Id: I2264c087b317f70506817b5458295a17e83b1efc
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32038
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-13 14:49:01 +00:00
Patrick Rudolph 1ae592b468 sb/intel/common: Add common detect_s3_resume
Add a common detect_s3_resume function.
Will be used by other southbridge code.

TODO: Merge with soc/intel/common/*/pmclib

Tested on Lenovo T520 (Intel Sandy Bridge) with Change
I283a841575430f2f179997db8d2f08fa3978a0bb applied as well.
Still boots to OS, no errors visible in dmesg and S3 resume is working.

Change-Id: I88023af522afac8164f068b0fbe0eac601aef702
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-04-13 14:48:25 +00:00
Subrata Banik 6d569163ab soc/intel/cpulib: Remove redundent enable/disable functions
This patch removes multiple enable/disable function definitions and
make use of single function with argument to know feature status
(enable/disable).

Change-Id: I502cd2497b07e9de062df453ecbb9c11df692f5a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32282
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-13 03:25:46 +00:00
Subrata Banik 459df6697a soc/intel/cpulib: Factor out IA32_PERF_CTL (0x199) MSR code
This patch replaces multiple IA32_PERF_CTL programming with single
helper function.

TEST=Build and boot WHL and CML platform.

Change-Id: I212daa61aa11191dd832630461b517d3dbedd6e1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-04-13 03:25:35 +00:00
Eric Lai c47eda0e6b mb/google/hatch: Restore Goodix Touch Screen
Restore Goodix devicetree config because of the
missing Goodix config when moving from baseboard
devicetree to board level overridetree. And move
PENH from I2C#2 to I2C#1.

BUG=b:124460799
BRANCH=None
TEST=local build and tested with Goodix touch screen

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ic028c5d7b687a069d7f0510897bea91dca58e91f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-13 02:25:37 +00:00
Furquan Shaikh cef9879c3d soc/intel/cannonlake: Select FSP_M_XIP
Cannon Lake and family require that FSP-M component should be
XIP. This change selects FSP_M_XIP so that the right arguments are
passed into cbfstool when adding this component.

BUG=b:130306520
TEST=Verified that hatch boots fine to OS.

Change-Id: Ifd8a829ebdc7681c81ece4540aa38cdcea7b6fac
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-04-12 15:59:27 +00:00
Furquan Shaikh 29368167b5 mb/google/hatch: Use GPIO IRQ for sx9310 device
This change uses GPIO IRQ instead of IOAPIC for GPP_A0 pad which is
the interrupt line for sx9310. This is required because IRQ# used by
GPP_A0 is allocated for PIRQ which does not allow IRQ# sharing.

Additionally, this change also configures GPP_A6 for GPIO IRQ. GPP_A6
is currently unused in the devicetree.

BUG=b:129794308
TEST=Verified that there are no interrupt storms on GPP_A0.

Change-Id: Ibb510a647391c0d9cb854d23656bb4b1cb7756ab
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-04-12 02:15:32 +00:00
Furquan Shaikh aea9871a62 drivers/i2c/sx9310: Add support for GPIO IRQ
This change adds support for mainboards to use GPIO IRQ instead of
IOAPIC to accomodate for cases where IOAPIC routing might not be
available for certain pads.

BUG=b:129794308

Change-Id: I3e2bb4280303cea177cc0c803d29140731e2b44a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32273
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-12 02:14:51 +00:00
Furquan Shaikh 55208409bc mb/google/hatch: Configure reset config to PLTRST for IOAPIC pads
This change configures reset config for all pads routed to IOAPIC as
PLTRST. This is required to ensure that the internal logic of the GPIO
gets reset any time the platform enters S3 or powers off and avoids
any interrupt storms on boot-up.

BUG=b:129933011
TEST=Verified that there are no interrupt storms on boot-up from S5.

Change-Id: Ib790280c9f1410fa18746d4d7d2a5027afd7585b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-04-12 02:14:24 +00:00
Furquan Shaikh 09b01de336 soc/intel/cannonlake: Do not use XIP_ROM_SIZE
XIP_ROM_SIZE Kconfig option isn't used on Cannon Lake and
family. Thus, this change selects NO_FIXED_XIP_ROM_SIZE to indicate to
build system so that romstage can be placed in less rigid manner.

BUG=b:129802811

Change-Id: I5f3786396246c89b1039ba1b6b332a32e6a0345d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-12 02:14:07 +00:00
Furquan Shaikh 9007118f32 mb/google/hatch: Skip UART0 config in FSP
UART0 is already configured in coreboot, so this change sets SerialIo
config for UART0 to PchSerialIoSkipInit to skip initialization in FSP.

BUG=b:130325418

Change-Id: Ifc88f4fa11bff2144417d5194776c15f9f7b60ac
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Shelley Chen <shchen@google.com>
2019-04-12 02:13:13 +00:00
Frans Hendriks 31eac4d869 drivers/spi: Move M25Pxx commands to spi_winbond.h
Move Winbond M25PXX command values to spi_winbond.h
file.
The command values will be used for programming SPI
contoller of Intel Braswell, using this include file.

Update winbond.c file with coreboot header.

BUG=N/A
TEST=Facebook FBG-1701 with flashrom

Change-Id: I9c17c4ed7004209bd3c619d47a7474b0b7e17495
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-11 12:00:56 +00:00
Frans Hendriks 1385b7dd10 drivers/intel/fsp1_1: Configure UART after memory init
FSP code will default enable the onboard serial port.
When external serial port is used, this onboard port needs to be
disabled.

Add function mainboard_after_memory_init() function to perform
required actions to re-enabled output to external serial port.

BUG=N/A
TEST=LPC Post card on Intel Cherry Hill

Change-Id: Ibb6c9e4153b3de58791b211c7f4241be3bceae9d
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/28464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-11 11:57:55 +00:00
Maxim Polyakov dd11810367 mb/asrock/h110m: Add virtual LDN for SuperIO to DT
Adds virtual logical devices numbers for the Nuvoton (NCT6791D)
SuperIO to the devicetree.

Change-Id: I7df1633951c30fef14c62c89aaedebd3044b312f
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-04-11 11:37:10 +00:00
Hung-Te Lin 693709bbec google/kukui: Add variant 'Krane'
Add the new configuration 'Krane' that will need at least its own EC.
There's currently no difference in coreboot side.

BUG=b:130011505
TEST=make menuconfig; make -j # select board=Krane
BRANCH=None

Change-Id: Ibb2ec42b08f9a51b22c22f3fe99b203f5eb31627
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-11 11:36:24 +00:00
Elyes HAOUAS b217baa4ee nb/intel/i945: Fix ich7_setup_root_complex_topology
Element Self Description register (ESD) [23:16] is R/WO, so let
write the ESD.CID when we start ich7_setup_root_complex_topology.
This value is also used to program the R/WO 'Target Component ID'
registers of RPxD and HHD.
Once it is done, no need to rewrite on them as they become RO.
(For more information, please see ICH7 datasheet page 271.)

Tested done on 945G-M4 using printk before and after writing.
Before this change, writing on those registers had no effect:
ESD:  0x0104: 0x00000802
ULD:  0x0110: 0x00000001
ULBA: 0x0118: 0x00000000
RP1D: 0x0120: 0x01000003
RP2D: 0x0130: 0x02000003
RP3D: 0x0140: 0x03000002
RP4D: 0x0150: 0x04000002
HDD:  0x0160: 0x0f000002
RP5D: 0x0170: 0x05000002
RP6D: 0x0180: 0x06000002

Using this patche, those R/WO get the "right" values.
i.e., We can see RCBA32(ULBA) is now equal to (uintptr_t)DEFAULT_DMIBAR.
ESD:  0x0104: 0x00020802
ULD:  0x0110: 0x01010001
ULBA: 0x0118: 0xfed18000
RP1D: 0x0120: 0x01020003
RP2D: 0x0130: 0x02020003
RP3D: 0x0140: 0x03020002
RP4D: 0x0150: 0x04020002
HDD:  0x0160: 0x0f020002
RP5D: 0x0170: 0x05020002
RP6D: 0x0180: 0x06020002

Change-Id: I3f2199d6da22ce9995496c2a81363710edde81f3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30993
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-11 11:32:07 +00:00
Eric Lai 7fc25c013b mb/google/sarien: Reserve gpio pins for D3 cold control
Based on HW change, reserve gpio pins for D3 cold control.
A13,A15 for Card reader
H13 for M.2 SSD

BUG=b:123263562
TEST=N/A

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ib4245be8d77c015e56df7b1d53ef82722c51d656
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-04-11 11:28:09 +00:00
Roy Mingi Park 67d630945b mb/google/sarien: Change GPIOs to avoid leakage during S0iX
Three GPIOs are not being used and this change will save 2-3mW
power during S0iX and this power saving is only for Arcada

BUG=b:129990365
TEST= Measure total platform power during S0iX from Arcada

Change-Id: Ie0208bd6c7affb2e87fd76005b727ea7effdf434
Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-04-11 11:27:57 +00:00
Jacob Garber f74f6cbde5 nb/intel/{gm45,i945,x4x}: Correct array bounds checks
There will be an out of bounds read if the index is equal
to the array size. Fix the checks to exclude this case.

Found-by: Coverity Scan, CID 1347350, 1347351
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I5b4e8febb68dfd244faf597dfe5cdf509af7a2ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-11 11:27:41 +00:00
Aamir Bohra e05fe3166e soc/intel/cannonlake: Correct the GPE DWx mapping for GPIO groups
This implementation corrects the GPE DWx mapping for GPIO groups.
The assignments is done in GPIO MISCFG register for all GPIO communities.
And configures the which GPIO communities get register as Tier1.

BUG=b:121212459
TEST: Verified the GPIO MISCFG is getting set as per updated map.

Change-Id: I451997367025a6dc9e5931bd649524e935ad6aca
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32175
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-11 11:26:37 +00:00
Tim Wawrzynczak 7fd1845991 mb/google/ampton: Fix polarity of EN_PP3300_WLAN_L signal.
WiFi enable signal was configured and driven as active-high, but the signal is                            |To start the server in this Emacs process, stop the existing
actually active-low

BUG=b:130196983
BRANCH=none
TEST=Verified WiFi still works after boot, and also after a suspend/resume cycle.  Device powers down correctly using "poweroff".

Change-Id: I64a67f73564188ad0548a1a770169ef2bca47453
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32255
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-11 11:25:15 +00:00
Joel Kitching a751445de4 vboot: do not set VBSD_BOOT_FIRMWARE_WP_ENABLED flag
The value of "write protect" GPIO shall be read in depthcharge,
and the flag shall be set there instead.

BUG=b:124141368, b:124192753, chromium:1556855
TEST=Build locally
CQ-DEPEND=CL:1556855
BRANCH=none

Change-Id: I4d24a057b1385244a836a67c565ee6726a894fdc
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-11 11:23:33 +00:00
Joel Kitching ae0fb762a2 chromeos: clean up "recovery" and "write protect" GPIOs
The "write protect" GPIO's cached value is never actually
read after entering depthcharge.  Ensure the value from
get_write_protect_state() is being transferred accurately,
so that we may read this GPIO value in depthcharge without
resampling.

The cached value of the "recovery" GPIO is read only on certain
boards which have a physical recovery switch.  Correct some of
the values sent to boards which presumably never read the
previously incorrect value.  Most of these inaccuracies are from
non-inverted values on ACTIVE_LOW GPIOs.

BUG=b:124141368, b:124192753, chromium:950273
TEST=make clean && make test-abuild
BRANCH=none

Change-Id: Ic17a98768703d7098480a9233b752fe5b201bd51
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-11 11:23:26 +00:00
You-Cheng Syu 482eec0e1b google/kukui: Use internal CR50_IRQ pull-up
For Kukui CR50_IRQ pin, we're going to replace external pull-up with
internal pull-up. This change won't break older boards, so we can just
always do that when setting up GPIOs.

BUG=b:124821269
BRANCH=none
TEST=Waveform looks correct.

Change-Id: Ib1a90dce583a6aa0cec8ac8ba96d1362f50c16a8
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-04-11 11:22:11 +00:00
Kane Chen 38dbd68920 mb/google/octopus: Disable WLAN prior the entry of S5
ODM reported issues that some systems can't be shutdown to S5 very
occasionally.

ODM found issue is gone if they remove the WLAN card.
So, this change to disable WLAN before system enters S5.
This change is validated by ODM and it does help issue.

BUG=b:129377927

Change-Id: Ib8e81022b8c9b63bc75e5cc14121233222da7595
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32246
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Chen Wisley <wisley.chen@quantatw.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-11 11:21:58 +00:00
Elyes HAOUAS 5de93e9011 nb/amd/amdfam10/util.c: Use "CONFIG" only when appropriate
Change-Id: Idcdbbfa883c906db1ebb8d9bc7c9e277e7c0c949
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-11 11:21:42 +00:00
Andrea Barberio 4a5f7ece3f mb/ocp/monolake: Add board.fmd
Change-Id: I6095c3b30990b530c5bc4e2c808879252680e1d7
Signed-off-by: Andrea Barberio <barberio@fb.com>
Signed-off-by: David Hendricks <dhendrix@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-10 18:46:56 +00:00
Jacob Garber e0c181d487 nb/intel/sandybridge: Set uninitialized run length
If the entire array is zero, then the length of the
longest zero run is the length of the array itself.

Found-by: Coverity Scan, CID 1229715
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: Id23292087b14182448d70117915fb044e9c579f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-04-09 17:24:40 +00:00
You-Cheng Syu cc86d8921b google/kukui: Configure AP_IN_SLEEP_L correctly
This pin should be set to its alternative function SRCLKENA0 instead of
GPIO, so that SPM (a power management component of MT8183) can control
it.

BUG=b:113367227
BRANCH=none
TEST=1. Boot. Run 'powerinfo' in EC console and see power state in S0.
     2. Run 'powerd_dbus_suspend --wakeup_timeout=10', and then
        run 'powerinfo' in EC console and see power state in S3.
     3. Wait until AP resume.
     4. Run 'powerinfo' in EC console and see power state back to S0.

Change-Id: I0a7e34f95381dec17eb6d166d6552c12e021bd9a
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32120
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-09 17:23:59 +00:00
Philip Chen 61d365fafd mb/google/hatch: Support 16MiB fmap
Add a fmd file for 16MiB fmap, so that we can support
both 16MiB / 32MiB SPI flash ROM chips.

BUG=b:129464811
TEST=build hatch firmware image with 16MiB fmap and
verify fmap is updated by 'fuility dump_fmap'

Change-Id: Ifc0103c7fd0d99439f40a31d23422401a6dce826
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-09 17:23:33 +00:00
Patrick Rudolph 15589b4e56 arch/x86/smbios: Reference type 7
Fill in the handle to cache entries of type 7 in the type 4 structure.

Tested on Intel Sandy Bridge (Lenovo T520).
All 3 caches are referenced.

Change-Id: Idf876b0c21c65f72a945d26c5898074b140763f8
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-04-09 17:22:41 +00:00
Patrick Rudolph fc5b80943b arch/x86/smbios: Add type 7
The SMBIOS spec requires type 7 to be present.

Add the type 7 fields and enums for SMBIOS 3.1+ and fill it with the
"Deterministic Cache Parameters" as available on Intel and AMD.

As CPUID only provides partial information on caches, some fields are set to
unknown.
The following fields are supported:
* Cache Level
* Cache Size
* Cache Type
* Cache Ways of Associativity

Tested on Intel Sandy Bridge (Lenovo T520).
All 4 caches are displayed in dmidecode and show the correct information.

Change-Id: I80ed25b8f2c7b425136b2f0c755324a8f5d1636d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-04-09 17:22:24 +00:00
Patrick Rudolph 835ca8ee64 arch/x86/cpu: Add functions to determine CPU vendor
Add two functions to determine if CPU is made by a specific vendor.
Use Kconfig symbols to allow link time optimizations.

Change-Id: I1bd6c3b59cfd992f7ba507bc9f9269669920b24f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Julien Viard de Galbert <coreboot-review-ju@vdg.name>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-09 17:21:50 +00:00
Tim Wawrzynczak 5ce1698138 mb/google/hatch: Add ACPI support for BT reset functionality
Expose the Bluetooth BT_DISABLE_L signal in Hatch's devicetree,
on both USB2 port 5 and 10.

BUG=b:123293169
BRANCH=none
TEST=compiles, verified kernel is able to find the reset-gpio

Change-Id: I6e4d9786e44f12da71533b6740fdd390f3a57e40
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32216
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-09 17:20:59 +00:00
Nico Huber baa070a81f src: Fix remaining #include <timer.h>
Follow-up to add76f91d5 (src: Use #include <timer.h> when appropriate).

Change-Id: I7813daa0b73039ec76d33a16ce3ae0ce6cc7f2cc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-04-09 17:20:35 +00:00
David Hendricks c4f3972f2e mb/facebook/watson: Make turbo mode configurable (disabled by default)
Change-Id: Ief1eaab960c8fdab5bd5041b1a4f0c6ba1dd833f
Signed-off-by: David Hendricks <dhendrix@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32222
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-08 20:55:13 +00:00
Nico Huber 8c11d05a3e nb/amd/pi/agesawrapper: Drop stale comment about IS_ENABLED()
We decided to not care about compile-time errors. So drop the comment,
the code was updated already.

Change-Id: Ib115fa6e2c48bfde7f67c327d42b3fe0e7af8c1f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-04-08 18:54:25 +00:00
Nico Huber 8f7a53a968 commonlib/cbfs: Check for presence of CONFIG() macro
Check for CONFIG not IS_ENABLED, as we use the former now.

Change-Id: I7e1b67bc0894ca6f0149039054449656b58bcdd3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-08 18:52:38 +00:00
Nico Huber e732773c74 soc/amd/stoney: Don't use IS_ENABLED() for a constant
IS_ENABLED() was supposed for Kconfig options.

Change-Id: Ia40d64856cd89586133e54ff6e02c35d6b647059
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32225
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-08 18:50:32 +00:00
Nico Huber 1dde7ccfa8 Replace remaining IS_ENABLED(CONFIG_*) with CONFIG()
Another run of
  find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'

Change-Id: I3243197ab852a3fbc3eb2e2e782966a350b78af2
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-08 18:50:10 +00:00
Jacob Garber b70c77691b nb/intel/pineview: Correct lsbpos(0) and msbpos(0)
lsbpos and msbpos have incorrect behaviour when given 0.
lsbpos(0) returns 8, and msbpos(0) hangs. The latter is
because the check i >= 0 is always true for an unsigned
integer, causing it to loop indefinitely (this was flagged
by Coverity).

0 doesn't have a lsb or msb position, so we change both
functions to return -1 in this case to indicate an error.
The code already guards against calling these functions
with 0, but we make this more explicit to prevent errors
in the future.

Found-by: Coverity Scan, CID 1347356, 1347386
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: Ic5be50846cc545dcd48593e5ed3fd6068a6104cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-08 14:15:20 +00:00
Jacob Garber 0decccb666 soc/intel/baytrail: Correct array bounds check
If `gms == ARRAY_SIZE(gms_size_map)`, then we will have an
out of bounds read. Fix the check to exclude this case.
This was partially fixed in 04f68c1 (baytrail: fix range
check).

Found-by: Coverity Scan, CID 1229677 (OVERRUN)
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I8c8cd59df49beea066b46cde3cf00237816aff33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-08 14:13:39 +00:00
Jacob Garber 42660cdda7 nb/amd/pi, mb/amd/bettong: Fix null pointer checks
The dev pointers were being dereferenced before the null
check. Move the checks so they are done earlier.

Found-by: Coverity Scan, CID 1241851 (REVERSE_INULL)
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: Ie578787c3c26a1f3acb4567c135486667e88a888
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-04-08 14:12:59 +00:00
Maxim Polyakov a12e9b0666 soc/skl: Update SkipExtGfxScan in UPD from devtree
The SkipExtGfxScan option is defined in the device tree, but doesn`t
update the value in the UPD. It uses the default value - 0. This
means that the FSP will scan all external graphics devices, in spite
of the configuration in devicetree.cb for a specific board.

Patch updates SkipExtGfxScan options in UPD from devicetree.cb.
This change affects all boards with skl/kbl processor.

Change-Id: Ie88a41bdf31f7c3e88df6c70c82a1cbf866372c4
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-08 14:12:15 +00:00
Mario Scheithauer 7935b4a89b siemens/mc_apl5: Remove reduced clock rate for I2C0
There is no device on I2C0 which requires a lower clock rate.

Change-Id: Iaf01be5ea4839c54eb2f0ba95bca272970c24bdb
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-04-08 14:11:21 +00:00
Michał Żygowski 83bb2d44b5 src/soc/intel/fsp_baytrail/smm.c: add bootstate entry for locking SMI
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ia296a680217a38136c063cae6ed619df0c497795
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30753
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-08 14:11:04 +00:00
Frans Hendriks 8bd5c996ab {src,util}: Correct typo in comment and debug string
Correct typo in comment and debug string.

BUG=N/A
TEST=build

Change-Id: I0362bb8d7c883e7fcbc6a2fc2f9918251f0d8d6e
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29321
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-08 14:10:20 +00:00
Sumeet Pawnikar db3ba1bc18 mb/mainboard/google/sarien/variants: Set correct tcc_offset value
Set new tcc_offset value to 10 degree C. This configures the Thermal
Control Circuit (TCC) activation value to 90 degree C. It prevents
any abrupt thermal shutdown while running heavy workload. This helps
to take early thermal throttling action when CPU temperature goes
above 90 degree C.

Change-Id: Ica77264782b4a3f3e72e73e1b8cb8b2e464fb033
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-08 14:10:02 +00:00
Eric Lai a2b7be7496 mb/google/sarien: Add support for melfas touch panel
Add a support melfas touch panel with i2c address:0x34.

BUG=b:122019253
TEST=tested with new melfas touch panel and worked

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I27f5c47517d093c819cbbbcdafd85d74145887e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32169
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-08 14:09:33 +00:00
Aamir Bohra 84743a178a src/soc/intel/cannonlake: Remove ITSS IPC restore
Remove ITSS IPC restore for cannonlake, as it does not take effect
since the ITSS PCR registers are locked post FSP-S.

Change-Id: Ie39e0d43644cb7b03b6c3432f0965f1d76d1bc37
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-08 10:39:44 +00:00
Jacob Garber 4318a978a7 vc/amd/agesa/f14: Add missing break statement
We do not want to ASSERT(FALSE).

Found-by: Coverity Scan, CID 1241850 (MISSING_BREAK)
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: Ia08bb519cdb5ef5d2a79898706c7fac7e58adf3f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-04-07 03:27:52 +00:00
Jacob Garber 7eb8eed460 sb/intel/{common,i82801dx}: Improve TCO debug code
Report unhandled TCO bits (previously dead code). This
finishes the work done in 3e3b858 (sb/intel/ibexpeak:
Update debug code to match other chips).

Found-by: Coverity Scan, CID 1229598 (DEADCODE)
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I65df8f3363c62b364e096368a36ba5e9e8894c13
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32179
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-07 02:43:26 +00:00
Kyösti Mälkki d2cdfff63b device/pci: Rewrite PCI MMCONF with symbol reference
The effect of pointer aliasing on writes is that any data on CPU
registers that has been resolved from (non-const and non-volatile)
memory objects has to be discarded and resolved. In other words, the
compiler assumes that a pointer that does not have an absolute value
at build-time, and is of type 'void *' or 'char *', may write over
any memory object.

Using a unique datatype for MMIO writes makes the pointer to _not_
qualify for pointer aliasing with any other objects in memory. This
avoid constantly resolving the PCI MMCONF address, which is a derived
value from a 'struct device *'.

Change-Id: Id112aa5e729ffd8015bb806786bdee38783b7ea9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31752
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-07 02:31:36 +00:00
Elyes HAOUAS bf0970e762 src: Use include <delay.h> when appropriate
Change-Id: I23bc0191ca8fcd88364e5c08be7c90195019e399
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: David Guckian
2019-04-06 16:09:12 +00:00
Elyes HAOUAS 161eafb0fb mb/amd/bettong/mainboard: Drop unused include <agesawrapper.h>
Change-Id: I020c1b9558f6aec47b048fa575c64c619b8c592a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32013
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-06 16:07:58 +00:00
Elyes HAOUAS add76f91d5 src: Use #include <timer.h> when appropriate
Also, extra-lines added or removed and local includes moved down.

Change-Id: I5e739233f3742fd68d537f671642bb04886e3009
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32009
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-06 16:02:49 +00:00
Maxim Polyakov 16a1181615 mb/asrock/h110m: Add PEG Gen3 support
This patch adds support PCIe Gen 3 with 8GT/s link speed for PEG x16
slot. All parameters for FSP are set during initialization in
romstage. Now there is no need to additionally configure the FSP
before building the ROM image.

Tested on Intel Core i5-6600 processor with the following devices:
  - LP11000e Fibre Channel HBA (Gen2 x8);
  - PEX8734 PCIe Fabric/Switch (Gen3 x16);
  - NVIDIA GeForce GTX 1060 GPU (Gen3 x16).

GPU works with an nouveau and proprietary driver under Ubuntu 18.04.2
(4.15.0-46-generic GNU/Linux kernel). Discrete graphic card is used
as primary device for display output. Dynamic switching is not yet
supported.

Tianocore (edk2-stable201811-216-g51be9d0) is used as the payload.

Change-Id: Ia4f29df47d76de5069fe53120434cc7c2ab6f044
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31948
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-06 13:44:06 +00:00
Maxim Polyakov 0220d1e46a soc/intel/skylake: Set FSP options for PEG port
FSP options list (for each PEG port):
  - PegXEnable,
  - PegXMaxLinkWidth,
  - PegXMaxLinkSpeed,
  - PegXPowerDownUnusedLanes,
  - PegXGen3EqPh2Enable,
  - PegXGen3EqPh3Method.

Add PegMaxLinkWidth to chip.h. This option overrides the number of
active lines from the devicetree.cb for each enabled PEG port (for
example for boards that use x4 instead of x16 lines in PEG0). If the
PegMaxLinkWidth is not defined, the port uses the maximum possible
number of lines.

To enable or disable the corresponding PEG root port you need to add
to the devicetree.cb:

  device pci 01.0 on  end # enable PEG0 root port
  device pci 01.1 off end # do not configure PEG1

If PEG port is not defined in the devicetree, it will be disabled in
FSP.

It has been tested on ASRock H110M-DVS motherboard (Skylake i5-6600
CPU).

Change-Id: I23708f7060edf08739adf61fe61a419329907563
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32045
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-06 13:43:42 +00:00
Maxim Polyakov 0de6c50744 mb/asrock/h110m: Set PEG as primary GFX device
If an external graphics card is inserted in the PEG, it will be used
as the primary display device (as in the AMI BIOS)

Change-Id: Iea846179fc309c2b98093de37c05ceb332081f4f
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-06 13:12:41 +00:00
Maxim Polyakov 0bec504642 {mb,soc/intel/skylake}: remove unused InternalGfx
The InternalGfx option in devicetree.cb is not used to enable iGPU.
The patch removes this option from chip.h and mb/*/devicetree.cb
files for all boards with skl/kbl processor.

Change-Id: I41ecca3fdfb1d4b20ee634a13263ff481dcf440e
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-06 13:12:04 +00:00
Maxim Polyakov de08ae1080 soc/intel/skylake: Update GFX devtree options
This patch includes the following changes:

 1. Sets FSP options in romstage_fsp20.c to select primary GPU.
    List of options:
      - InternalGfx,
      - PrimaryDisplay.

 2. iGPU will be initialized if the corresponding PCI device is defined
    in the device tree as:

      device pci 02.0 on end

    In this case, it is not necessary to set the InternalGfx option to
    enable this device

 3. Primary_iGFX is used as the default value for all skl/kbl boards
    (since the PrimaryDisplay option isn`t defined in the devicetree.cb)

Change-Id: Ie3f9362676105e41c69139a094dbb9e8b865689f
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-06 13:11:25 +00:00
Frans Hendriks e75cb331df drivers/pc80/rtc/mc146818rtc.c: Reset RTC time on RTC power failure
RTC time contains invalid values on system without RTC battery.
Handle 'invalid' the same way as 'cmos_invalid'. This will reset CMOS date
when calling function enables 'invalid'.

BUG=N/A
TEST=Portwell PQ-M107 booting Linux Embedded

Change-Id: I5eae57d00f328400a8b03c28b7ecdbbc71522206
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29329
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-05 12:39:51 +00:00
Julius Werner d371cf3336 Make common macros double-evaluation safe
I just got hit by a double-evaluation bug again, it's time to attempt
to fix this once more. Unfortunately there are several issues that don't
make this easy:

 - bitfield variables don't support typeof()
 - local macro variables that shadow others trigger -Werror=shadow
 - sign warnings with integer literal and unsigned var in typeof-MIN()
 - ({ statement expressions }) can not be used outside functions
 - romcc doesn't support any of the fancy GCC/clang extensions

This patch tries to address all of them as far as possible with macro
magic. We don't have the technology to solve the bitfield and
non-function context issues yet (__builtin_choose_expr() still throws a
"no statement expression outside a function" error if it's only in the
branch that's not chosen, unfortunately), so we'll have to provide
alternative macros for use in those cases (and we'll avoid making
__ALIGN_MASK() double-evaluation safe for now, since it would be
annoying to do that there and having an alignment mask with side
effects seems very unlikely). romcc can continue using unsafe versions
since we're hopefully not writing a lot of new code for it. Sign
warnings can be avoided in literal/variable comparisons by always using
the type of the variable there. Shadowing is avoided by picking very
explicit local variable names and using a special __COUNTER__ solution
for MIN() and MAX() (the only ones of these you're likely to nest).

Also add DIV_ROUND_UP() to libpayload since it's a generally quite
useful thing to have.

Change-Id: Iea35156c9aa9f6f2c7b8f00991418b746f44315d
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-04 19:38:31 +00:00
Furquan Shaikh bac21f5b13 mb/google/hatch: Move I2C/SPI options to override tree
This change moves the I2C/SPI devices and configs which do not apply
to all variants to override tree. Currently, there are just two
variants. However, as we prepare to add more variants, these devices
need to be moved out of the base devicetree.

BUG=b:129728235
TEST=Verified that I2C/SPI devices are present in static.c for hatch
and hatch_whl.

Change-Id: I9426f6bf5f8514de5f1889e22e57105749fd92de
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32138
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-04 17:41:57 +00:00
Rizwan Qureshi b866610156 mb/google/hatch: Change the DEVSLP reset config to PLTRST
In S3 the PCH is driving the DEVSLP signal low, assuming that the SATA device
is already powered off. However on hatch the SATA power is still enabled. And,
since DEVSLP is low, this causes the SATA device to not enter low power state.
The fix here is to set the pad config to be reset on PLTRST assertion which
will cause the pin to be high impedance state and will be pulled up by the
SATA device.

BUG=b:126611255
BRANCH=None
TEST=Make sure that S3 and S0ix is working fine on hatch.
And also make sure that DEVSLP is pulled high in S3.

Change-Id: Ifb6a71a72244522c8dd8d48e9b9f8dc6feef8981
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-04 10:38:38 +00:00
Uwe Poeche b4a4036306 siemens/mc_apl4: Provide CLK on APL Pin PMU_SUSCLK
This patch provides a clock on Pin PMU_SUSCLK. This is necessary for correct
function of the SMARC module.

Test=mc_apl4 flashed, booted into Linux, ckecked CLK with scope

Change-Id: Ieb1d66b5a09363c9bed2b19e7a204f206ee04158
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32168
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-04 10:37:44 +00:00
David Wu 2e2fe3cc91 mb/google/fizz/variants/karma: Clear GPP_B4 when entering S5
Set GPP_B4 to low in S5 to meet touch panel power sequence

BUG=b:124197348
BRANCH=master
TEST=Verify GPP_B4 is low.

Change-Id: I65deb33a45fdc0c0ce64deaa29c2790029dc1d12
Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-04 10:37:16 +00:00
Frans Hendriks 2c63017ca3 soc/intel/braswell: Correct serial IRQ support
Serial IRQ was configured in quiet mode, but not enabled.
Enable serial IRQ and use 'enum seriirq_mode' as a devicetree
option.

Function sc_enable_serial_irqs() is added to enabled serial IRQs.
enable_serirq_quiet_mode() is renamed to
sc_set_serial_irqs_mode(). This function use the 'serirq_mode' to
set the mode. The call to this function is moved from finalize to init
having serial IRQs enable in early stage.

Serial IRQs must be enabled in continuous mode for at least one frame
before switching into quiet mode.

BUG=N/A
TEST=Portwell PQ7-M107

Change-Id: I7844cad69dc0563fa6109d779d0afb7c2edd7245
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-04-04 10:36:56 +00:00
Martin Roth 0828d03de2 soc/nvidia/tegra210: Increase bootblock size
There's an issue with the newest toolchain that is blowing the bootblock
size on Smaug when compiling for chromeos.  Increasing the bootblock
size by 2KB will take care of the issue for a while.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I58f7f1cedc8fc5b4c4287f5a120ed76140e1f7a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-04-04 10:34:51 +00:00
V Sowmya e8c655dd1b mb/intel/coffeelake_rvp: Configure FSP UPDs of DDI ports for cmlrvp
This patch configures FSP UPD values for HPD and DDC of DDI ports for
CMLRVP.

BUG=none
TEST= Tested that eDP works on CMLRVP.

Change-Id: If8c8480eaf2d63cec0b5598b5af3088c630dd78a
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32140
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-04 10:34:28 +00:00
Shelley Chen c10fed0743 mb/google/hatch: Add Kohaku board
Adding Kohaku as a variant of hatch.

BUG=b:129706980
BRANCH=NONE
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
     make sure HATCH_KOHAKU is built as well.

Change-Id: I5b451f421f6d353005e6b73eac180dcec2e8b0c0
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-04 10:34:14 +00:00
Shelley Chen c76409ca35 mb/google/hatch: Create kohaku variant
Creating Kohaku hatch variant.  Currently taking a copy of the hatch
variant.  Kohaku-specific changes to come in future CLs.

BUG=b:129706980
BRANCH=NONE
TEST=NONE

Change-Id: Ib4b8c2c8332910d992549e3aae8e6aff5234698b
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32160
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-04 10:34:09 +00:00
Joel Kitching e556f716e4 vboot: remove Kconfig option VBOOT_PHYSICAL_REC_SWITCH
This option is duplicated in depthcharge:
https://crrev.com/c/1545144

BUG=b:124141368, b:124192753, chromium:943150
TEST=make clean && make test-abuild
CQ-DEPEND=CL:1545144
BRANCH=none

Change-Id: I48e20ad21cdcb948a23387d3e5fcf142723b0c82
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-04-04 10:33:38 +00:00
Eric Lai b80ae90b6e mb/google/hatch: Enable Goodix Touch Screen
Enable Goodix touch screen.
Follow GT7375P_Datasheet_Rev.0.1

BUG=b:124460799
BRANCH=None
TEST=local build and tested with Goodix touch screen

Change-Id: Ib204e6b77b87ba6c775cf38e572476dd9eb37d1d
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32134
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-03 21:52:35 +00:00
John Su 0a4dcee75f mb/google/sarien/variants/sarien: Update thermal configuration for DPTF
Follow thermal table for second tunning.

BUG=b:129509918
TEST=Built and tested on sarien system

Change-Id: I64844b84891dc3ab7abe9378cdca5dcf57b3e433
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2019-04-03 08:46:25 +00:00
Julius Werner 6d9c131061 vboot: Change oprom checks to CONFIG_VBOOT, assert OPROM_MATTERS
Skipping display init on normal-mode boot is a vboot feature, not
specific to Chrome OS. Fix the code in display_init_required() and
pci_dev_init() to check CONFIG_VBOOT rather than CONFIG_CHROMEOS now
that the two aren't always the same anymore.

Also add a check to guarantee at compile time that
CONFIG_VBOOT_OPROM_MATTERS is enabled on all platforms that make a check
to this function (when CONFIG_VBOOT is also enabled). The whole display
skipping mechanism is based on the oprom_needed NVRAM flag, and skipping
display init without enabling the option to tell vboot that it needs to
pay attention to that flag would make the whole thing not work right.

Change-Id: I5d6421509bdcdaa61b78015af3fa6241fe75bb7f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-02 13:08:43 +00:00
Ran Bi b197808852 mediatek/mt8183: Fix RTC initialization flow
1. Fix RTC lpd settings. Rewrite powerkeys after lpd init
   to enable low power detect function.
2. Rearrange RTC initialization flow.
3. Add return status for rtc_init.
4. Add log if calling pwrap_write or pwrap_read fail.
5. Increase timeout time to resolve unexpected timeout.

BUG=b:127405695
BRANCH=none
TEST=Boots correctly on Kukui

Change-Id: I6f26edd6699c2f6d9af80c285b70742b44407136
Signed-off-by: Ran Bi <ran.bi@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
2019-04-02 10:25:42 +00:00
Frank Wu 274613303e mb/google/poppy/variants/nami: update sku_ids for Pantheon
The sku ids are updated for Pantheon.
Sync'ing the sku_ids list in the master sku sheet for Pantheon.

BUG=b:121207221
BRANCH=firmware-nami-10775.B
TEST=emerge-nami coreboot chromeos-bootimage

Change-Id: Ibf683ca8219b2980ea9d9c40b06db264d58440b0
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
2019-04-02 10:25:12 +00:00
John Su eb7720e00a mb/google/hatch: Change GPIO_E1 setting
For HW require to change GPIO_E1.
Change GOIO_E1 setting from NF2(SATAGP1) to NF1(SATAPCIE1).

BUG=b:123730924
TEST=flash BIOS and make sure hatch boots up properly

Change-Id: I0f5569e13b17a2dc713be5031a63436e8f31f911
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32099
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-02 10:22:29 +00:00
Krishna Prasad Bhat c41b0e8ea3 mb/google/hatch: Re-configure GPP_A12 as GPO before entering sleep
GPP_A12 has a Native3 (SX_EXIT_HOLDOFF#) mode, which allows to delay
resuming to S0. If this pad is not locked and platform was not initially
designed for this functionality, malware could reconfigure this pads
setting under OS (switch to Native3), which would make platform not able
to resume until G3 is applied. To prevent misuse of this pad,
re-configure this pad before entering S3 and S5 to guarantee that the
pad configuration is correct.

BUG=b:128686027

Change-Id: I1e7979baa491acf2c56d223afb4618f0f6429e37
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-02 10:21:59 +00:00
Subrata Banik 51c8532c6b drivers/intel/fsp2_0: Use same stack with coreboot
This patch ensures to have same stack base for FSP and coreboot.

Feature added in FSP2.1
- Remove stack swapping from FSP.
- Stack will be shared between coreboot and FSP.

TEST=Build and boot FSP2.1 enable platform like dragonegg, iclrvp.
No car global variable corruption seen after enabling
this feature.

Change-Id: I673b4216d991d8ccad725c3931006a694184106c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32079
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-02 02:18:24 +00:00
Elyes HAOUAS 17fa9deef1 mb/aopen/dxplplusu: Remove redundant use of ACPI offset operator
Change-Id: I790303a1fab64dbbe749563325394b9be2c109ad
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-04-01 18:37:34 +00:00