Like the QPI Link device, there can be more of these devices on
multi-socket platforms. So, name it Physical Layer 0.
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.
Change-Id: Ia5f6e42a742bc69237de38f1833e56c8da7c4f7e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
On multi-socket platforms, there can be two QPI buses, each with its own
PCI device. We only have one QPI link on Arrandale, though. In case
support for multi-socket processors ever gets added, name it Link 0.
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.
Change-Id: I6481154a2d1cc1c84c1f167a374a62af3b2cf3d8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This register resides within the SAD's config space, and is 64-bit.
Change-Id: I19458f7c6be6b1a5fcd47ac93ee0597f1251a770
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Let's hope this cheers up the poor System Address Decoder device.
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.
Change-Id: Ia62c05abb07216dc1ba449c3a17f8d53050b5af1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Only some registers have such a prefix. Drop it for consistency.
Change-Id: I1ef7307d10a06db8f3c1a05bd9184f21fceb9d90
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Uppercase variable names can be confused with register definitions. Use
lowercase names instead, conforming to the coding style guidelines.
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.
Change-Id: I61a28bf964ea8c2c662539825ae9f2c88348bdba
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This is the only instance of `BETTER_MEMORY_MAP` in the tree.
Change-Id: I118e5b5a0f10da56e2335828477caed81c5bf855
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This register does not seem to exist on Ironlake.
Change-Id: I3fba6a3fd443f2c9eab874e1d1b8f081f58b1536
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Looks like some registers are defined twice. Also, group some QPI
registers together. They were scattered around and mixed with the host
bridge registers, probably because other northbridges have such
registers in the host bridge's PCI config space. But not Ironlake.
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.
Change-Id: I6e60f7fcb1467f302618eeab1b0d995920a98569
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Sort them by ascending offsets.
Tested with BUILD_TIMELESS=1, Foxconn D41S does not change.
Change-Id: I521aa3e49b17a9fb6b279ae758801356e510d054
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
From a log of a machine using Crystal Well CPU [1], Crystal Well CPUs
use some new PCI IDs. Without this patch, the Crystal Well northbridge
cannot be initialized in ramstage, thus the machine cannot boot. Some
PCI IDs of Crystal Well related devices can be found in the PCI ID
database [2].
Tested with i5-4570R (with LGA1150 mod) on ASRock H81M-HDS. The board
boots to SeaBIOS with boot screen displayed on HDMI output, and then
boots Arch Linux on a USB disk.
[1] https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/DNHLQTNTRQT43T67DG7L2HVI5CV74ZCM/
[2] https://pci-ids.ucw.cz/read/PC/8086
Change-Id: Icfe55323fd06187148c788ebfa7b679b6944e4f3
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41658
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the name of the assembly instruction it uses, mfence.
Change-Id: I98d7926434694a41fb6415bed4276741fa7996af
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Fill in the maximum DRAM capacity and slot count read from CAPID0_A
registers on Sandy Bridge and Haswell.
While the register isn't part of the Core Series datasheet, it can be
found in the corresponding "Intel Open Source Graphics Programmer's
Reference" datasheets.
Note that the values for DDRSZ (maximum allowed memory size per channel)
need to be halved when only one DIMM per channel is supported. On mobile
platforms, all but quad-core processors are subject to this restriction.
Tested on Lenovo X230:
On Linux, verify that `dmidecode -t 16` reports the actual maximum
capacity (16 GiB) instead of the currently-installed capacity (4 GiB) or
the max capacity assuming two DIMMs per channel is possible (32 GiB).
Change-Id: I6e2346de1ffe52e8685276acbdbf25755f4cc162
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
On Haswell platforms, the processor and the PCH are two separate dies,
and communicate through a high-speed bus. This is DMI (Direct Media
Interface) on traditional two-package platforms, but single-package
Haswell LP variants use OPI (On-Package Interconnect) instead.
Since OPI is not routed through the mainboard, most link parameters are
static and cannot be changed. OPI self-initializes on boot, anyway.
However, DMI needs to be initialized in firmware. On Haswell, the MRC
initializes the physical DMI link, but things like topology and power
management need to be configured as well. And we don't do that properly.
We enable ASPM on the PCH side of the DMI link, but not on the SA side.
Both sides need to use the same settings, so enable DMI ASPM on the SA.
Clearing the error status bits needs to be done on all Haswell variants.
Tested on Asrock B85M Pro4, still boots.
Change-Id: Ie97ff56eec9f928cfd2d5d43a287f3e0d2fbf3cf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The Kconfig lint tool checks for cases of the code using BOOL type
Kconfig options directly instead of with CONFIG() and will print out
warnings about it. It gets confused by these references in comments
and strings. To fix it so that it can find the real issues, just
update these as we would with real issues.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I5c37f0ee103721c97483d07a368c0b813e3f25c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This to silent a bug found using gcc-10.
src/northbridge/intel/ironlake/raminit.c: In function 'setup_heci_uma':
src/northbridge/intel/ironlake/raminit.c:1805:11: error: 'reply.command' may be used uninitialized in this function [-Werror=maybe-uninitialized]
1805 | if (reply.command != (MKHI_SET_UMA | (1 << 7)))
| ~~~~~^~~~~~~~
cc1: all warnings being treated as errors
Change-Id: I0d13de549b6d428ac3675ee3f91eb5e42aeb25e8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42461
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add missing registers and sort them by ascending offsets.
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change.
Change-Id: I98f836668144032d920b56afff878acc0a58ed82
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
It was only used in one function, but its value was never read. Drop it.
Change-Id: Ib511352d51d4452d666640d0f52810b06c8d61ce
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
There's no need to set up the southbridge in the northbridge code.
Change-Id: I0f80c92aca885812c27a8803c2745844d8dfb939
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Make it default to 0x400, which is what the touched southbridges use.
Change-Id: I95cb1730d5bf6f596ed1ca8e7dba40b6a9e882fe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
There's no generic way to tell whether a mainboard has an EC or not.
Making Kconfig symbols for these options seems overkill, too. So, just
put them on the devicetree. Also, drop unnecessary assignments when the
board's current value is zero, as the struct defaults to zero already.
Change-Id: If2ebac5fcab278c97dfaf8adc9d1e125888acafe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43129
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If the Intel in-PCH GbE MAC is enabled in the devicetree, then tell MRC
to enable it as well. No one can ever forget to set this option anymore!
Change-Id: I946af36d16c94bb1a0f146604d0329fe6d6ce7e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43128
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
And use it instead of directly writing to the MRC struct.
Change-Id: I7f04db29a08512c1a8b2b2300dba71cb3b84a5c5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Check the PCH's LPC device ID to know the system type instead of relying
on hardcoded numbers. The `get_pch_platform_type` function is MRC-safe.
Change-Id: Icfe7c2dccb7c7a178892ad3a2e34ca93b33b2bb9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43124
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This Kconfig symbol allows doubling the memory's refresh rate, assuming
that the MRC actually cares about it. It is disabled by default except
on the mainboards which explicitly enabled this setting in `pei_data`.
Change-Id: I6318dad0350d1c506c67f9d117d0ae8dad871281
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
All mainboards have a non-zero SPD address to implemented DIMM slots.
Knowing this, it is possible to compute the MRC slot population masks
automatically instead of hardcoding the values on each mainboard.
Change-Id: Ia8f369dd1228d53d64471e48700e870e01e77837
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43119
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These settings are the same on all boards. Since the other boards
currently overwrite the struct contents, it doesn't make a difference.
To ease review, the same settings will be dropped from other boards in
separate commits, one board at a time.
Change-Id: I500b7a1d7d97c6976e0c7c10ca491d3875cae22b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
This is what sandybridge does, and if done properly allows factoring out
common settings. Said refactoring will be handled in subsequent commits.
Change-Id: I075eba1324a9e7cbd47e776b097eb940102ef4fe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
It only contains a pointer to another struct. Flatten it.
Change-Id: Iab427592c332646e032a768719fc380c5794086b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Instead of using function pointers, we can use weak functions. So, drop
the pointer from `romstage_params`, leaving `pei_data` as the only
remaining member. This will be cleaned up in a follow-up commit.
Change-Id: I3b17d21ea7a650734119a5cab4892fcb158b589d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This function is called at the end of `romstage_common`. Only one board
makes use of it, the Lenovo ThinkPad T440p. To preserve behavior, call
it after `romstage_common` has done nearly everything.
Change-Id: I35742879e737be4f383a0e36aecc6682fc9df058
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43094
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Code has evolved such that there seems to be little
use for global definition of cbmem_top_chipset().
Even for AMD we had three different implementations.
Change-Id: I44805aa49eab526b940e57bd51cd1d9ae0377b4b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43326
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I5e33526a02872c14e9fa37a485d2f93dea8b088f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: Icb98f3535f6c5f51081fc82262f6413f4b1a5733
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43261
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I41a4f73df7fdd372ec7a80a41c8216c502054c39
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43262
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I36500c1f0eb3c37d08c691d22382ceca732d1355
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
This simplifies things and makes type checking possible.
Change-Id: Iefc9baabae286aac2f2c46853adf1f6edf01586f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Instead of passing around a pointer to an array, just write the relevant
registers directly. Note that intel/baskingridge used spaces to indent
line continuations and had to be replaced with tabs to quell Jenkins.
Change-Id: Ifa06a2ab24da9b8c6aac6480542fa32d04f6d6fe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Other platforms do this as well. It will ease refactoring on follow-ups.
Change-Id: I643982a58c6f5370c78acef93740f27df001a06d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
This was silently commenting out the line after it.
Change-Id: I2714090b8f99193ace420ad02e2d42b324349c9e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Remove some unneeded newlines, add some commas for consistency and
relocate comments to match the code.
Tested with BUILD_TIMELESS=1, Foxconn D41S does not change.
Change-Id: I0ac18a692bf613c75083c4aa1860e0a9f07e68d8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Use C-style comments, drop unneeded newlines, add missing commas for
consistency and relocate a comment to match the code.
Tested with BUILD_TIMELESS=1, Getac P470 remains identical.
Change-Id: I37fffb60944c35dfb5e0491bb023babfcf2c6a73
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43177
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use C-style comments, drop an unneeded newline, add missing commas for
consistency and relocate a comment to match the code.
Tested with BUILD_TIMELESS=1, Roda RK9 does not change.
Change-Id: I3f91d1b57eb5530c8adcf5f682e73747435f0d47
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43172
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use C-style comments. Also drop some unnecessary newlines.
Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change.
Change-Id: Icd33a326cc7d9ead765e2b32e7dea237bd76fd4f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The host bridge register definitions haven't changed from Sandy Bridge
to Haswell, according to the datasheets. However, coreboot's ACPI code
is not the same. Looks like Haswell values are wrong, so correct them.
Change-Id: Ib099575b5cc5e7d468db51f382a15b8aac3eedea
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
p3b-f suspend code is going to use it.
Change-Id: Iebc17257e9f690115ec35d94c7c36df39341f0df
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41092
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Bring DRB7 OpRegion and top-of-memory indicator inside NB device.
Use more concise ASL 2.0 syntax for TOM calculations.
Change-Id: I2c74ef30a9bb48e02154f963b1ca3a4f5f3004df
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reflow lines, correct coding style and align struct members, among
other things. As raminit is very large, handle it on a follow-up.
Tested with BUILD_TIMELESS=1, packardbell/ms2290 does not change.
Change-Id: I343edf1bc2a5ac20ff0aa6de4486e685ce430737
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42701
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Just call the called function directly.
Change-Id: I0c997a63cbbd2b1029f94c23685847df910f8a0e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Currently, northbridge BARs are 32-bit values. We don't have any use
case for BARs above 4 GiB in early stages, so handling possibly 64-bit
values seems unnecessary, which currently is a noisy way to write zero.
Tested with BUILD_TIMELESS=1, packardbell/ms2290 remains identical.
Change-Id: I93d1740b961f6a5962757d9a1e960b3f1014a0c6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This function was copy-pasted, comments included, from Sandy Bridge.
However, it is only called with 0x0044 as the northbridge's PCI ID.
Therefore, `bridge_silicon_revision() & BASE_REV_MASK` will always
evaluate to 0x40, which never equals `BASE_REV_SNB`, that is, 0x00.
As the condition is always false, treat this code as dead and drop it.
Following a similar reasoning, all direct comparisons against SNB
steppings will always be true, because `bridge_silicon_revision()`
returns at least 0x40 which is always larger than either `SNB_STEP_D0`
or `SNB_STEP_D1`. So, drop all but the code path that is actually used.
Change-Id: I5219a6af3df98ed77c9c4abfb9a63c2ebf8171bb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
These were copied from gm45, but are not used. Drop them.
Change-Id: I85ca37516272a2c1af88a65df2682e92d7579050
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This function isn't defined anywhere for Pineview. Drop its declaration.
Change-Id: I38a01d6ba5aaa91de08702c1eb8a2e8c70688192
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Also drop now-redundant definitions and include headers where needed.
Tested with BUILD_TIMELESS=1, Roda RK9 remains identical.
Change-Id: I3ddd133a4e81a7f6ce9c33ce227b40006a0d1850
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42658
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There's a useless check with both branches doing the same: enabling RC6
and disabling RC6p. In past, this condition would enable RC6p in IVB but
not on SNB. Then, at some point, RC6p was considered unstable and was
disabled, but the condition remained.
It's not needed so let's remove it.
Change-Id: I926bb682d1b9d21185048224490b966c33204b6a
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The PCI COMMAND register is 16 bits wide. So, do not use 32-bit PCI ops
to update it.
Change-Id: I8f8d9e978f3b241cb544dd1d26e0f5fa8997d11e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
At least one mobile 945 series northbridge supports 4 threads, because
the dual-core Atom 330 CPU supports Hyper-threading. Therefore, we use
that as the default for this chipset.
Change-Id: I899ed1644d9b2da4fc72f09233a421200770110d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41845
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
LGA775 CPUs can have at most 4 threads, and Eaglelake supports them.
As this socket is also used by other chipsets, temporarily place this
symbol into the northbridge scope until all chipsets are factored out.
Change-Id: I6e01363d995e135815cc70779e0cd5baf806cf60
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The offset between registers has to be between different channels.
Change-Id: Ic6d959c31c78073a3ecbf7a17dfb73ac36340599
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change.
Change-Id: If16d8c4aef3dfd1dbeaf48d6855dd4c0ef328168
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change.
Change-Id: If7f3f06cd3524790b0ec96121ed0353c89eac595
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Commit 5ac723e (nb/intel: Fix 16-bit read/write PCI_COMMAND register)
uses `pci_read_config8` to read the PCI command register, which does not
correspond with what has been stated in the commit message. Moreover, it
potentially breaks things, as the upper byte of the PCI command register
is now being cleared.
So, restore the original behaviour of the code, using 16-bit accesses.
Fixes: 5ac723e (nb/intel: Fix 16-bit read/write PCI_COMMAND register)
Change-Id: Id2c42ea8551a2fa2fa5c64e8fff8940d8304fbe0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Lower 20bits of TOLUD and TOLM registers include 19 reserved bits and
1 lock bit. If lock bit is set, then systemagent.asl would end up
reporting the base address of low MMIO incorrectly i.e. off by 1.
This change masks the lower 20 bits of TOLUD and TOM registers when
exposing it in the ACPI tables to ensure that the base address of low
MMIO region is reported correctly.
Change-Id: Ib0ffd9a332fa9590de63f8828d30daa710fe50db
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This change updates hostbridge.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.
TEST=Verified using --timeless option to abuild that the resulting
coreboot.rom is same as without the ASL2.0 syntax changes for google/link.
Change-Id: I5345ee22df7da92ee48c718f5bd748d7ea6155f2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Lower 20bits of TOLUD and TOLM registers include 19 reserved bits and
1 lock bit. If lock bit is set, then systemagent.asl would end up
reporting the base address of low MMIO incorrectly i.e. off by 1.
This change masks the lower 20 bits of TOLUD and TOM registers when
exposing it in the ACPI tables to ensure that the base address of low
MMIO region is reported correctly.
Change-Id: I1fb52a42e84130d973e0970024e263f443aa0b89
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This change updates hostbridge.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.
TEST=Verified using --timeless option to abuild that the resulting
coreboot.rom is same as without the ASL2.0 syntax changes for
google/beltino.
Change-Id: I0ba2da441c7b398cc7f84a7ef7a5d233b0365cbe
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
<types.h> is supposed to provide <commonlib/bsd/cb_err.h>,
<stdbool.h>,<stdint.h> and <stddef.h>. So remove those includes
each time when <types.h> is included.
Change-Id: I886f02255099f3005852a2e6095b21ca86a940ed
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The allocator should take care of this.
Change-Id: I4ec88ebe23b4dcab069f764decc8b9b0c6e6a142
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40726
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It never was in GNVS, it never belonged among the ACPI tables. Having
it in CBMEM, makes it easy to look the location up on resume, and saves
us additional boilerplate.
TEST=Booted Linux on Lenovo/X201s, confirmed ASLS is set and
intel_backlight + acpi_video synchronize, both before and
after suspend.
Change-Id: I5fdd6634e4a671a85b1df8bc9815296ff42edf29
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40724
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds legacy VGA memory (0xa0000 - 0xbffff) as
mmio_resource in northbridge.c read_resources() to match what is
exposed to the OS in hostbridge.asl. It ensures that the resource
allocator does not use this range for dynamic resource allocation.
Change-Id: I24e3aaf97202575fa9df8408366c8db5bea07145
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
This change selects the old resource allocator RESOURCE_ALLOCATOR_V3
for northbridge/amd chipsets. This is required until the chipsets can
be fixed to report the resource requirements correctly before resource
allocator runs. Issues identified in the chipset code are captured in
the mailing list thread here:
https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/QWLUXO3V5IR5AS6ARRI722BFVAPOD5TS
Change-Id: Iaf873ee76a67482483e410aede653dd8f662e468
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
This change updates find_pci_tolm() to not consider any unassigned
resources. This is achieved by adding the following checks:
1. Call search_bus_resources() with mask set to IORESOURCE_MEM |
IORESOURCE_ASSIGNED.
2. In the callback tolm_test, check that the new resource selected has
a non-zero size.
This change is being made so that the resource allocator does not have
to set the IORESOURCE_ASSIGNED flag for marking a resource as
invalid.
Change-Id: I796784dd93aa165e20a672c985b4875991901c87
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Now that we have created the IOSAV API, we can put it to good use.
Drop all the helper macros and replace them with struct constructs.
Tested with BUILD_TIMELESS=1, ASUS P8Z77-V LX2 remains unchanged.
Change-Id: Ib366e364df11c9bb240cdfbce418540ec715c634
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41003
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We now use a static variable to handle the sequence length.
Tested on Asus P8Z77-V LX2, still boots.
Change-Id: Id3115c14336ea128264bd3945a99c52b9796d115
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Instead of directly writing values to the IOSAV registers, use a struct
and some helper functions to provide a cleaner interface for the IOSAV.
Having IOSAV_SUBSEQUENCE refer to a static function is weird, but we
will remove this macro in a follow-up that does not change the binary.
Tested on Asus P8Z77-V LX2, still boots.
Change-Id: I73f13c18a739c5586a7415966f9017c2335fdfd1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
We set bit 15 of IOSAV_n_SUBSEQ_CTRL three times, but it is reserved.
Since this bitfield is five bits wide, manually truncate the values so
that bit 15 does not get set.
Tested on Asus P8Z77-V LX2, still boots.
Change-Id: Ib61b026b016b0d22e164f8817158ec5093f6bb9e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Turn `iosav_run_queue` and `iosav_run_once` into functions. Inlining
them does not have any effect, as the resulting binary is identical.
Tested on Asus P8Z77-V LX2, still boots.
Change-Id: I7844814eeedad9b1d24f833a77c90902fa926bfe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Turn it into a macro that looks like a function, and add another, more
generic `iosav_run_queue` that covers all current use-cases. They will
be replaced with functions in a follow-up to preserve reproducibility.
Tested with BUILD_TIMELESS=1, ASUS P8Z77-V LX2 remains unchanged.
Change-Id: I07b260b5fb111c1408ff75316dc0735a9e642ac9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
To replace the register writes with assignments to struct fields, we
would need to have the values as parameters of a single macro. So,
split the raw value of `IOSAV_n_SP_CMD_CTRL_ch` in two parts. Note that
the single command that sets bit 17 is likely wrong, but it will be
fixed after refactoring. For now, we'll treat it as part of `ranksel`.
Move the parameters of `ADDR_UPDATE` into the top-level IOSAV macro.
Hopefully, this will be enough to replace the underlying implementation.
Line length limits are not for review. Breaking the lines unnecessarily
complicates search and replace operations, and wil be taken care of in
subsequent commits.
Tested with BUILD_TIMELESS=1, ASUS P8Z77-V LX2 remains unchanged.
Change-Id: I404edbd5d90ddc2a6993f39f552480d1ef24e153
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Other northbridges use an index variable to assign monotonically
incrementing values to each resource. Do it here as well.
Change-Id: I8719a1a5973a10531cf11b3307652212cb3d4895
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The IOSAV register descriptions are plagued with errors and nonsense.
Using `git blame` to find the culprit... Zoinks! Turns out it was me!
Rewrite the comment so that the difference between a sub-sequence and a
command is clear. Also, expand the descriptions that could be ambiguous
and fix some insane blunders. CKE and ODT fields are per DIMM and rank!
As per review comments, also invert the order of bitfield value ranges.
Change-Id: Ie384304c565f962fe58baa231c15109eb3d284aa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
NO_RANKSEL was introduced because it appeared less often and it did not
cause any lines to become too long. To simplify macro transmutation, add
the RANKSEL opposite and keep NO_RANKSEL as a no-op to ease replacement.
Line length limits are not for review. Breaking the lines unnecessarily
complicates search and replace operations, and wil be taken care of in
subsequent commits.
Tested with BUILD_TIMELESS=1, ASUS P8Z77-V LX2 remains unchanged.
Change-Id: I5d7aad59fc79840da7de2e9421b84834a6024eb9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40977
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a temporary solution to simplify refactoring verification.
Programming a subsequence involves writing a group of four registers.
Abstract this into a "program subsequence" operation. This eliminates
register write noise, which should improve the readability of the code.
To replace the register writes with assignments to struct fields, we
would need to have the values as parameters of a single macro. So,
unroll SUBSEQ_CTRL and SP_CMD_ADDR into parameters of IOSAV_SUBSEQUENCE.
Line length limits are not for review. Breaking the lines unnecessarily
complicates search and replace operations, and wil be taken care of in
subsequent commits.
Tested with BUILD_TIMELESS=1, ASUS P8Z77-V LX2 remains unchanged.
Change-Id: I23f7706ba8a87c1c26f9d40a50b6d47dcf95106a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
We have a single IOSAV sequence that is broadcast across all channels.
Introduce the BROADCAST_CH macro, so that we can use the per-channel
register definitions. Treating all IOSAV sequence writes the same eases
the refactoring done in subsequent commits. Also, drop the broadcast
register definitions for the IOSAV commands, as they are now obsolete.
Line length limits are not for review. Breaking the lines unnecessarily
complicates search and replace operations, and wil be taken care of in
subsequent commits.
Tested with BUILD_TIMELESS=1, ASUS P8Z77-V LX2 remains unchanged.
Change-Id: I2dbb100fcad68d128e92b1bc9321fc1e53b748c9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40976
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The chipset code was incorrectly adding memory resources
to the domain device after resource allocation occurred.
It's not possible to get the correct view of the address space,
and it's generally incorrect to not add resources during
read_resources(). This change fixes the order by adding resources in
read_resources().
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I84c1ba8645b548248a8bb8bf5bc4953d3be12475
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Keith Hui <buurin@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The chipset code was incorrectly adding memory resources
to the domain device after resource allocation occurred.
It's not possible to get the correct view of the address space,
and it's generally incorrect to not add resources during
read_resources(). Fix the order by hanging the resources off
of the host bridge device.
Change-Id: I8a7081020be43da055b7de5a56dd97a7b5a9f09c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
pci_domain_set_resources is duplicated in all the SOCs. This change
promotes the duplicated function.
Picasso was adding it again in the northbridge patch. I decided to
promote the function instead of duplicating it.
BUG=b:147042464
TEST=Build and boot trembyle.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iba9661ac2c3a1803783d5aa32404143c9144aea5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
All boards using this northbridge now enable serial in bootblock,
so this is no longer needed.
Change-Id: I6baf2de81870dbba2a7f1abb3f1fdd6716d64511
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41048
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We only write to the IOSAV LFSR registers twice, but we do so between
the writes to the other four IOSAV per-subsequence registers. Since we
know that the IOSAV is sleeping when we program the subsequences, we
might as well do the two oddball LFSR register writes after we have
programmed the always-written-to group of four registers. That way,
subsequent changes can reproducibly replace the four writes with a
single macro.
Tested on Asus P8Z77-V LX2, still boots.
Change-Id: If7bb14a9862a53a3eba565d17401347dcc9ffbe9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40973
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reorder the order of the operands in three register writes, so that
replacing them with macros in a follow-up does not change the binary.
Tested on Asus P8Z77-V LX2, still boots.
Change-Id: I44aee9c0f49770586de322ee7f44c3609dbadd0b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40972
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Copyright notices are best stored in AUTHORS
Change-Id: Ib9025c58987ee2f7db600e038f5d3e4edc69aacc
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41203
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Stefan thinks they don't add value.
Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)
The exceptions are for:
- crossgcc (patch file)
- gcov (imported from gcc)
- elf.h (imported from GNU's libc)
- nvramtool (more complicated header)
The removed lines are:
- fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-# This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */
Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
vboot_recovery_mode_enabled() was recently changed to assert() when it
is called before vboot logic has run, because we cannot determine
whether we're going to be in recovery mode at that point and we wanted
to flush out existing uses that pretended that we could. Turns out there
are a bunch of uses like that, and there is some code that is shared
across configurations that can and those that can't.
This patch cleans them up to either remove checks that cannot return
true, or add explicit Kconfig guards to clarify that the code is shared.
This means that using a separate recovery MRC cache is no longer
supported on boards that use VBOOT_STARTS_IN_ROMSTAGE (this has already
been broken with CB:38780, but with this patch those boards will boot
again using their normal MRC caches rather than just die). Skipping the
MRC cache and always regenerating from scratch in recovery mode is
likewise no longer supported for VBOOT_STARTS_IN_ROMSTAGE.
For FSP1.1 boards, none of them support VBOOT_STARTS_IN_BOOTBLOCK and
that is unlikely to change in the future so we will just hardcode that
fact in Kconfig (otherwise, fsp1.1 raminit would also have to be fixed
to work around this issue).
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I31bfc7663724fdacab9955224dcaf650d1ec1c3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This replaces GPLv2-or-later and GPLv2-only long form text with the
short SPDX identifiers.
Commands used:
perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.*of.*the.*License.*or.*(at.*your.*option).*any.*later.*version.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-or-later */|s' $(cat filelist)
perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist)
perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation[.;,].+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist)
perl -i -p0e 's|/\*[*\n\t ]*This software is licensed under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation,.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist)
Change-Id: I7a746088a35633c11fc7ebe86006e96458a1abf8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
That makes it easier to identify "license only" headers (because they
are now license only)
Script line used for that:
perl -i -p0e 's|/\*.*\n.*This file is part of the coreboot project.*\n.*\*|/* This file is part of the coreboot project. */\n/*|' # ...filelist...
Change-Id: I2280b19972e37c36d8c67a67e0320296567fa4f6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Also remove an extra star in comment.
Change-Id: I2ef938573e75022dcb31c935dde7d3055e7a53f0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40802
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It declares a function that was either never or no longer implemented.
Change-Id: I714d39374519bff1afb94870d0e84f57db619a1f
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This change moves all ACPI table support in coreboot currently living
under arch/x86 into common code to make it architecture
independent. ACPI table generation is not really tied to any
architecture and hence it makes sense to move this to its own
directory.
In order to make it easier to review, this change is being split into
multiple CLs. This is change 3/5 which basically is generated by
running the following command:
$ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g'
BUG=b:155428745
Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
The table of initial i440BX register values has a bitmask that allows
preserving certain bits as they are programmed. This feature has been
unused since day one and probably will never be used. So drop it.
Drop DRB, RPS, PGPOL registers from the table as they will be
programmed during RAM init. These two reductions combined saved ~104
bytes.
Drop unneeded SDRAMC "+0".
Slightly compact a comment block.
TEST=Boot tested on asus/p2b-ls, i440bx config did not change
Change-Id: I020f616455bb671fe284993a488beb6386a03d0d
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Looks like 5 is a valid system type, as Google Beltino and Slippy are
using it. According to comments on these mainboards' code, this value
corresponds to ULT systems. So, add it to the comment on the pei_data
struct, which was likely copied from Sandy Bridge and was not updated.
Change-Id: I3654bb6022839dba3e1499cf43e8beaa97d1def1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
.acpi_fill_ssdt() does not need to modify the device structure. This
change makes the struct device * parameter to acpi_fill_ssdt() as
const.
Change-Id: I110f4c67c3b6671c9ac0a82e02609902a8ee5d5c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40710
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
.write_acpi_tables() should not be updating the device structure. This
change makes the struct device * argument to it as const.
Change-Id: I50d013e83a404e0a0e3837ca16fa75c7eaa0e14a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Some PCI peripherals, such as discrete VGA adapters, require a great
amount of memory mapped IO. This patch allows the user to select at
build time the bottom IO to leave enough space for such devices.
We cannot calculate this value at runtime because it has to be set
before the PCI devices are enumerated. 0x80000000 has been successfully
boot-tested on A88XM-E (fam15tn), G505S (fam15tn) and AM1I-A (fam16kb).
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: Ie235631231bcb4aeebaff2e0026da2ea9d82f9d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
The WDB (Write Data Buffer) is a data region in CAR, used as a
scratchpad in the read and write training algorithms of memory
initialization. Both SNB and IVB use this buffer, but HSW does not.
Unlike earlier chipsets, Haswell contains much more in-hardware memory
training machinery, known as REUT (Robust Electrical Unified Testing).
Among other changes, the REUT hardware has a pattern storage buffer,
which renders the need for a pattern storage buffer in CAR obsolete.
Deprecate the WDB-related parameters in the pei_data structure for
Haswell, as they are leftovers from the previous generation's MRC.
Remove them from the mainboards, and explain why they are not required.
Because the MRC ABI has to remain the same, the layout of pei_data must
not be changed, so rename the WDB parameters instead of deleting them.
Tested on Asrock B85M Pro4, still boots with the MRC from Google Wolf.
Change-Id: I7acc9353a22f8c6f9fe6407617162f35849a79dd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
It is not necessary to pass its value around various function calls.
Move it closer to where it is actually used, so as to make it static.
Also, use config_of_soc and flip the branches of the first conditional.
Tested on Asus P8Z77-V LX2, still boots.
Change-Id: I5c49c943c87218d4d40d3168bd8b7b900b0ec2e9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39851
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With this bootblock messages are transmitted over serial too.
TEST=Serial messages transmitted normally on asus/p2b-ls.
Change-Id: I6f3ee68e7c76a8c6db6d75956e6a7fb75ef83850
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add support for detection ECC capability and forced ECC mode.
Print the ECC mode in verbose debugging mode.
Change-Id: I5b7599746195cfa996a48320404a8dbe6820483a
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/22214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
`.read_resources` and `.set_resources` are the only two device
operations that are considered mandatory. Other function pointers
can be left NULL. Having dedicated no-op implementations for the
two mandatory fields should stop the leaking of no-op pointers to
other fields.
Change-Id: I6469a7568dc24317c95e238749d878e798b0a362
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40207
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Providing an explicit no-op function pointer is only necessary for
`.read_resources` and `.set_resources`. All other device-operation
pointers are optional and can be NULL.
Change-Id: I3d139f7be86180558cabec04b8566873062e33be
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40206
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use defined structures to assemble IVRS and IVHD entries. Additionally
assemble IVHD type 11h which supersedes IVHD type 10h. In order to
utilize all IOMMU features firmware should also expose IVHD type 11h.
The new type is already supported and parsed since Xen 1.13. IVHD
type 10h should still be present for backwards compatibility.
TEST=boot PC Engines apu2 and disassemble IVRS using newest IASL,
boot Xen 1.13 or newer with debug enabled and see IVRS IVHD 11h parsed
in xl dmesg
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I9a2c24b67adfa8ebd718caeb5eec88687dcbcc9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: Id2cb642baa764fd69543460ba869cd822ab5acad
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Unmentioned fields are initialized with 0 (or NULL) implicitly. Beside
that, the struct has grown over the years. There are too many optional
fields to list them all.
Change-Id: Icb9e14c58153d7c14817bcde148e86e977666e4b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40126
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
No longer used by southbridge, no longer needed since pineview
doesn't utilize drivers_intel_gma_displays_ssdt_generate()
Change-Id: Ia386f8fcd208e201fb8bc2a37cdbecd6f45a044b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39960
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Simplify generation of GMA SSDT, using updated naming convention.
If acpi_fill_ssdt is being invoked, then we know the IGD device is
present and enabled, so we can skip those checks. And the SSDT
generator now checks that the gfx struct is populated, so we can
skip that too.
Change-Id: Ideddfc3d327c4421faffb6583e347cd2b094e155
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Simplify generation of GMA SSDT, using updated naming convention.
If acpi_fill_ssdt is being invoked, then we know the IGD device is
present and enabled, so we can skip those checks. And the SSDT
generator now checks that the gfx struct is populated, so we can
skip that too.
Change-Id: I68848516fab2058d4aa96ac0342c883fd1df2d6d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Simplify generation of GMA SSDT, using updated naming convention.
If acpi_fill_ssdt is being invoked, then we know the IGD device is
present and enabled, so we can skip those checks. And the SSDT
generator now checks that the gfx struct is populated, so we can
skip that too.
Change-Id: Iacce01ab7d6c220779e84c2b695fbb597b493586
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Simplify generation of GMA SSDT, using updated naming convention.
If acpi_fill_ssdt is being invoked, then we know the IGD device is
present and enabled, so we can skip those checks. And the SSDT
generator now checks that the gfx struct is populated, so we can
skip that too.
Change-Id: I1b6d57c091441aa7431061b1f16135d54cc97b47
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Simplify generation of GMA SSDT, using updated naming convention.
If acpi_fill_ssdt is being invoked, then we know the IGD device is
present and enabled, so we can skip those checks. And the SSDT
generator now checks that the gfx struct is populated, so we can
skip that too.
Change-Id: If34ebe0edc46674244c9d5afc7ed165c2ad685ba
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Simplify generation of GMA SSDT, using updated naming convention.
If acpi_fill_ssdt is being invoked, then we know the IGD device is
present and enabled, so we can skip those checks. And the SSDT
generator now checks that the gfx struct is populated, so we can
skip that too.
Change-Id: Icd9caf622dd4c46b13589ebb772138b25888752f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
These two identifiers were always very confusing. We're not filling and
injecting generators. We are filling SSDTs and injecting into the DSDT.
So drop the `_generator` suffix. Hopefully, this also makes ACPI look a
little less scary.
Change-Id: I6f0e79632c9c855f38fe24c0186388a25990c44d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39977
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: David Guckian
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Including gma.asl at the platform level (vs the board level)
means that even desktop boards need to include the default
brightness levels, which makes no sense. To begin to clean this up,
include gma.asl in default_brightness_levels.asl (as well as
the handful of board-specific brightness files) and remove it
from the various platforms.
A follow-on commit will remove default_brightness_levels.asl
from all boards which lack an internal display.
Change-Id: I8063deeef4ab6d6ab34ed9b0be5b1d541d6e9b6b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39878
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Further backport the backlight-PWM handling from Skylake. Beside
configuring the PWM frequency in Hz, we also use the PCH's logic
for the brightness setting via BLM_PCH_OVERRIDE_ENABLE. Linux
would toggle it anyway and that might confuse our ASL code.
We assume that the 183Hz value that was set before for Slippy
variants was overridden by Linux with the 200Hz VBT value, like
it was for the Broadwell Chromebooks. So we set 200Hz for them
in the devicetrees. The calculated value for the T440p of 220Hz
seems sane and also matches the VBT.
Change-Id: I17dfe1a3610d5e2918c617cf5d10896692fdccb3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Some commands, like ZQCS and ZQCL, use the same macro. This is because
they differ in things outside of the IOSAV_SP_CMD_CTRL registers. Also,
correct a comment that does not concur with the actual command in use.
With BUILD_TIMELESS=1, the binary of ASUS P8Z77-V LX2 remains identical.
Change-Id: Id2ff4c85f9d9db7c892b764472423cbf2e6db422
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The four CS control signals are grouped into the same nibble.
Change-Id: Iaf8d5216fdca6014be61ae2583fc963d69111571
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
It is only for Ivy Bridge, and needs to be set on certain circumstances.
Change-Id: I4093adef44fae787c96fec4b4b8c7c867786d219
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This register is specific to Ivy Bridge. This changes the binary because
the operations get reordered, but it is equivalent.
Change-Id: Ibc9127e0fc268466c13f7c5ac8d942543713ca32
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This changes the binary because the operations get reordered, but it is
otherwise equivalent.
Change-Id: I362187b2889e6f7a68bf752a23c1279cebf961f2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Expand a comment with additional information, and split it in two lines.
Change-Id: I10389a1a575833c8ecc9a79a374c1816000f5667
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
It is no longer specific to Ivy Bridge.
Change-Id: I3684e654a1b1aee308e30db739d41cf18e7ea6bd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39790
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Sandy Bridge now uses the same code as Ivy Bridge. Drop the old code.
Change-Id: I4f6a71a4223194d83c0ee790d317ecdcafd664fd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The code for Sandy Bridge is a subset of the code for Ivy Bridge. Adapt
the Ivy Bridge code so that it also supports Sandy Bridge, and use it.
Tested on Asus P8Z77-V LX2, still boots with i7-2600 and i5-3330.
Change-Id: I7b78ec605aff976b9a5cdbb364a69df4b4947c6e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39737
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This field can take eight different values, depending on the maximum
supported speed for the memory when using the 100 MHz reference clock.
Change-Id: I8f2f04f9444831319d4f7bf0d246d01030b6f864
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The code is just clamping the frequency index to a valid range. Do it
with a helper function. Also, add a CPUID check, as Sandy Bridge will
eventually use this code.
Change-Id: I4c7aa5f7615c6edb1ab62fb004abb126df9d284b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
It does not change once a frequency has been set, so store it somewhere.
Since this changes the saved data definition, update MRC_CACHE_VERSION.
As SNB will eventually use the same code, only IVB is being refactored.
Change-Id: I25b7c394abab173241fffdf57ac5c929daad8257
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
There is no need to call get_FRQ a dozen times with the same parameters.
As SNB will eventually use the same code, only IVB is being refactored.
Tested on Asus P8Z77-V LX2, still boots with i7-2600 and i5-3330.
Change-Id: Idd7c119b2aa291e6396e12fb29effaf3ec73108a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Instead of adding more versions of the `*pch.asl`, unify the existing
ones and allow to override the register locations via Kconfig. The
current defaults should work for Skylake and some newer platforms.
TEST=Booted ThinkPad X201s, backlight control still works.
Change-Id: I0b21d9a0288f0f8d6cb0a4776909bffdae7576f5
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
The ACPI Spec 2.0 states, that Processor declarations should be made
within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated
and is removed here.
Additionally add processor scope patching for P-State SSDT created by
AGESA, becasue AGESA creates the tables with processors in \_PR scope.
TEST=boot Debian Linux on PC Engines apu2, check dmesg that there are
no errors, decompile ACPI tables with acpica to check whether the
processor scope is correct and if IASL does not complain on wrong
checksum, run FWTS
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I35f112e9f9f15f06ddb83b4192f082f9e51a969c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39698
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The timing tables for Sandy Bridge are a subset of Ivy Bridge's tables.
Move the latter to a common place, and use it for both generations.
Tested on Asus P8Z77-V LX2 with an i7-2600 and an i5-3330, both work.
Change-Id: Id14227febf4eebb8a2b4d2d4f37759d0f42648c6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39735
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Northbridge IOAPIC was not being initialized which caused its APIC ID to
be set to 0 (the same APIC ID as BSP).
TEST=boot Debian Linux on PC Engines apu2
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Id06ad4c22a56eb3559e1d584fd0fcac1f95f13e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Now that we have it, we might as well pass it around.
Tested on Asus P8Z77-V LX2, still boots fine.
Change-Id: Ia5aa2f932321983f11d2f8869aa624832afe9347
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39721
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Native raminit asserts that the DIMMs haven't been replaced before
reusing the saved training data. However, it does not check if the CPU
is still the same, so it can end up happily reusing data from an Ivy
Bridge CPU onto a Sandy Bridge CPU, which runs the raminit_ivy.c code
path. This can make the CPU run in unsupported configurations, which may
result in an unstable system, or a failure to boot.
To prevent that, ensure that the stored CPUID matches the CPUID of the
installed CPU. If they differ, print a message and do not use the saved
data. As it does not pose a problem for a regular boot, but precludes
resuming from S3, use different loglevels depending on the bootpath.
Tested on Asus P8Z77-V LX2 with an i7-2600 and an i5-3330, works well.
Change-Id: Ib0691f1f849b567579f6afa845c9460e14f8fa27
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Instead of storing an int with a single bit of information taken from
the CPUID, we might as well store the actual CPUID. And since we are
changing the definition of the saved data, bump the version number.
Tested on Asus P8Z77-V LX2, still boots fine.
Change-Id: I6ac435fb83900a52890f823e7614055061299e23
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39720
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When changing any of the structures that are cached in non-volatile
storage, it is necessary to bump MRC_CACHE_VERSION so that the old
information is not misinterpreted.
Change-Id: Idefbc38b3a8198b1b5909e775b3c289db689fc0c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39756
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Header files are supposed to not make allocations from .bss. Builds
fail if said file is included multiple times. To prevent this from
happening, move the definitions to a C file.
Also, rename raminit_patterns to raminit_tables. This is because more
tables that are not patterns will be added here in subsequent changes.
Tested on Asus P8Z77-V LX2, still boots fine.
Change-Id: If8e3a285ecdc4df9e978ae156be915ced6e1750b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39754
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make them fit in 96 characters, so that Jenkins does not complain.
With BUILD_TIMELESS=1, the binary of ASUS P8Z77-V LX2 remains identical.
Change-Id: I4a763f6050593e9d4db9211bfeedb442724e1ace
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39719
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The ACPI Spec 2.0 states, that Processor declarations should be made
within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated
and is removed here for Intel CPUs only.
Tested on:
* X11SSH (Kabylake)
* CFL Platform
* Asus P8Z77-V LX2 and Windows 10
FWTS does not return FAIL anymore on ACPI tests
Tested-by: Angel Pons <th3fanbus@gmail.com>
Change-Id: Ib101ed718f90f9056d2ecbc31b13b749ed1fc438
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
According to BKDGs these northbridges should support the K10
compatible temperature sensors.
TEST=boot FreeBSD on PC Engines apu2 and check the thermal zone
temperature using sysctl
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Icbdf44508085964452d74e084b133f1baa39e1a8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
According to BKDGs HTC temperature limit field indicates the threshold
where HTC becomes active. HTC active state means that processor is
limiting its power consumption and maximum P-State. Using this threshold
as _CRT is incorrect, since HTC active is designed to prevent
overheating, not causing immediate shutdown.
Change the behavior of temperature limit to act as a passive cooling
threshold. Make the passive cooling threshold a reference value for
critical and hot temperature with 5 degrees step.
TEST=boot FreeBSD on PC Engines apu2 and check the thermal zone
temperature using sysctl
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ife64c3aab76f8e125493ecc8183a6e87fb012e3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Fixes a blunder in commit 50db9c99be
(nb/intel/sandybridge: Use DIV_ROUND_UP macro to select timings).
Tested on Asus P8Z77-V LX2, still boots fine with an i7-2600.
Change-Id: I73436b9f7df9f3a065469fb89bcd0cc6183bb774
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
It does not make sense to disable an optimization that was not enabled
before, especially if that optimization only applies to Ivy Bridge.
Tested, still boots and can suspend correctly with:
- Asus P8Z77-V LX2 with i5-3330 and Windows 10
- Gigabyte GA-H61MA-D3V with i5-2400 and Arch Linux
Change-Id: I9f3eb545585824bbdf51e33f0592e7daa1c425af
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Use the version from native raminit, as it takes the reference clock
into account.
Change-Id: I00e979bec236167d22561e3eb44b30b4a34ad663
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39622
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This register needs to be written to once to lock it down. Do so.
Change-Id: I04bd496d064940b51cb9aa1ded6f5b8853ea7334
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39624
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The DMI link consists of four lanes, grouped in two bundles. Therefore,
some DMI registers may be organized as "per-lane" or "per-bundle". This
can be seen in the DMI initialization sequence as series of equidistant
offsets being programmed with the same value. Make this more obvious by
factoring out the register groups using loops.
With BUILD_TIMELESS=1, the binary of ASUS P8Z77-V LX2 remains identical.
Change-Id: Iebf40b2a5b37ed9060a6660840ea6cdff7eb3fc3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
- Reformat some lines of code
- Move MCHBAR registers and documentation into a separate file
- Add a few missing macros
- Rename some registers
- Rewrite several comments
- Use C-style comments for consistency
- Rewrite some hex constants
- Use HOST_BRIDGE instead of PCI_DEV(0, 0, 0)
With BUILD_TIMELESS=1, this commit does not change the result of:
- Asus P8Z77-V LX2 with native raminit.
- Asus P8Z77-M PRO with MRC raminit.
Change-Id: I6e113e48afd685ca63cfcb11ff9fcf9df6e41e46
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39599
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
They're listed in AUTHORS and often incorrect anyway, for example:
- What's a "Copyright $year-present"?
- Which incarnation of Google (Inc, LLC, ...) is the current
copyright holder?
- People sometimes have their editor auto-add themselves to files even
though they only deleted stuff
- Or they let the editor automatically update the copyright year,
because why not?
- Who is the copyright holder "The coreboot project Authors"?
- Or "Generated Code"?
Sidestep all these issues by simply not putting these notices in
individual files, let's list all copyright holders in AUTHORS instead
and use the git history to deal with the rest.
Change-Id: I89b10076e0f4a4b3acd59160fb7abe349b228321
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39611
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use De Morgan’s law to simplify the condition by getting rid of the
negations.
TEST=With `make BUILD_TIMELESS=1` getac/p470 remains unchanged.
Change-Id: I041f2740d6991f9b4e6b8f77988b970c028ca512
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
- Reformat some lines of code
- Put names to all MCHBAR registers in a separate file
- Rewrite several comments
- Use C-style comments for consistency
- Rewrite some hex constants
- Use HOST_BRIDGE instead of PCI_DEV(0, 0, 0)
- Align a bunch of things
Tested with BUILD_TIMELESS=1, foxconn/d41s remains unaffected.
Change-Id: I29104b0c24d66c6f49844f99d62ec433bb31bdaf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The code in coreboot is actually for the Arrandale processors, which
are a MCM (Multi-Chip Module) with two different dies:
- Hillel: 32nm Westmere dual-core CPU
- Ironlake: 45nm northbridge with integrated graphics
This has nothing to do with the older, single-die Nehalem processors.
Therefore, replace the references to Nehalem with the correct names.
Change-Id: I8c10a2618c519d2411211b9b8f66d24f0018f908
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38942
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The code is for Arrandale CPUs, whose System Agent is Ironlake.
This change simply replaces `nehalem` with `ironlake` and `NEHALEM`
with `IRONLAKE`. The remaining `Nehalem` cases are handled later, as
changing some of them would impact the resulting binary.
Tested with BUILD_TIMELESS=1 without adding the configuration options
into the binary, and packardbell/ms2290 does not change.
Change-Id: I8eb96eeb5e69f49150d47793b33e87b650c64acc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38941
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Reformat some lines of code
- Put names to all used MCHBAR registers
- Move MCHBAR registers into a separate file, for future expansion
- Rewrite several comments
- Use C-style comments for consistency
- Rewrite some hex constants
- Use HOST_BRIDGE instead of PCI_DEV(0, 0, 0)
Tested, it does not change the binary of Asrock B85M Pro4.
Change-Id: I926289304acb834f9b13cd7902801798f8ee478a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38434
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Per Mobile Intel ® 945 Express Chipset Family - Specification Update
Document Number: 309220-013 (page 15), the power saving optimization
Erratum is for Mobile Intel ® 945 Express Chipset family.
So rename 'fixup_i945_errata()' to 'fixup_i945gm_errata()' and apply
that function only for I945GM.
Change-Id: I2656021b791061b4c22c0b252656a340de76ae5e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This is a port of https://review.coreboot.org/c/coreboot/+/22337 to the
Haswell northbridge. This code is necessary to support the dGPU of the
t440p. Code was cut and pasted from Sandy Bridge with vendor IDs updated
to the correct Haswell values. Tested on t440p with dGPU on Ubuntu
18.04.4 with 5.3.0-28 kernel. Without patches dmesg reports Nouveau is
unable to read the VBIOS of the dGPU as it has an invalid checksum (I
checked that the ROM in CBFS is correct). With this patch DRM works
correctly with both the Nouveau driver and the Nvidia proprietary
driver. Windows 10 1909 also tested but generates bluescreen once GPU
driver is loaded.
Change-Id: Ie5f089fb6fd774e6c61f4f9281e2945bd44edf27
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Some local functions need renaming to avoid name collision.
Change-Id: I0ca311c12f013e54e23ff0427421bfad0b747ea6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37195
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
"amdfam10" is no more.
Change-Id: Ibf4892bb4076eb88b864fc0e894b986bf6f6e5bf
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38054
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The VBOOT code can be compiled but it asserts with:
ASSERTION ERROR: file 'src/security/vboot/common.c', line 40
Start VBOOT in bootblock to fix the assertion.
Tested on Lenovo X220:
The assertion is gone, the platform boots again.
Change-Id: I48365e911b4f43aecba3b1f950178b7ceed5b2e9
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Previously the PRTs were defined in southbridge code (8014714
southbridge/intel/bd82x6x/acpi: Fix IRQ warnings), but this was lost
when southbridge PRTs became autogenerated. Add the proper PRTs for the
PCI express for graphics root ports.
This (again) fixes warnings issued by Linux for interrupts on secondary
functions of devices on the PEG ports, such as the HDMI audio controller
on graphics cards.
pcieport 0000:00:01.0: can't derive routing for PCI INT B
snd_hda_intel 0000:01:00.1: PCI INT B: no GSI
Tested with GIGABYTE P67A-UD3R (CB:31363) with Radeon HD 5670.
Change-Id: Ic429ec2fdeadb9dab1c03916974e173004d6cd16
Signed-off-by: James Ye <jye836@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Change-Id: I70187d09ecdaa8149299cdd8f6f8fc9517b05e15
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Enable Access Control Services and Advanced Error Reporting for PCI Express
bridges in order to have PCIe devices in separate IOMMU groups for correct
passthrough.
TEST=run dmesg on Debian Buster on PC Engines apu2 and check whether PCIe
devices have separate groups
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I10a8eff0ba37196692f9db6519e498fe535ecd15
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Calculate the correct MMCONF size, which was only correct for
256MiB, but not for smaller values.
Tested on HP Z220:
Fixes "Not using MMCONF" warning in dmesg.
Change-Id: I986681126637c28f6442ab7c34acea5bb58ea3d2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Jonathan Kollasch <jakllsch@kollasch.net>
* Use new ACPI syntax
* Return either 0 or 0xf for PCI root port. That will make the
device show up in Windows. This might help users and possibly
Windows drivers working with PCIe ports.
Change-Id: I1e76b735ab1472f6a4ea493c733cd6b2e6fca29e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The type of dev in the PCI_FUNC(dev) is incorrect. Fix it using
PCI_DEV2DEVFN() macro. Tested on a T440P, and necessary on this board
to enable the dGPU.
Change-Id: I3fb0f677cc98800f355f6af7d3172be3e59ce5c2
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38722
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace the multiplications with corresponding shifts, so that it's
easier to see at which bit offsets the values get assigned.
Change-Id: I0b0d5172394ff65edfe57bdad474631938e58872
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Types from stdint.h are used in that header file without stdint.h being
included.
Change-Id: I71449dd26162dc8420c206285896ac9a8e4e04d4
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The two defines are identical, so deduplicate this.
Timeless build for lenovo/x230 results in identical binary.
Change-Id: I32e0eee88d72eb6f8dc71b0324d62f46079120a9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Drop DRAMT write as it's only rewriting the power on default.
PMCR write is required. Update comment on its purpose and move to
end of sdram_enable().
Change-Id: I62e8b2531f0f297ffb7db440db89ffa65771b7d5
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch doesn't change the resulting binary of a timeless build.
Change-Id: Ife0e70699df3efa162f8f6c0fd8c2928887fda2d
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This is to get a uniform format that matches the macros added in the
next patch, so that said follow-up patch won't change the output binary.
lenovo/x230 still boots with this patch.
Change-Id: Ibfbeb847cab09427a57bef3cbd2069036de5a21e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Rename array and use defines for the values.
The patch doesn't change the resulting binary when using BUILD_TIMELESS=1
Change-Id: I774373d231a0f4a2fe82ab7c6f1318fc56bcc678
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38405
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
LyCx(r, x, y) was a duplicate of the CxLy(r, x, y) with different order
of computation, so that the big refactoring doesn't change the output
binary of a timeless build. Now this workaround can be dropped.
Tested on lenovo/x230: still boots
Change-Id: I251b4dd383f954b27f392190092e06a9a06668e2
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
There are more instances of PCI_DEV(0, 0, 0), so use the macro for them.
Note that the resulting code with PCI_DEVFN(0, 0) is weird. It shall be
replaced with config_of_soc() in a follow-up.
Tested with BUILD_TIMELESS=1, resulting binary is identical.
Change-Id: Ia50965a108a734d192b584291a0796a2f2bc3a55
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38338
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some things fit in a single line now that we have a 96-char limit.
Tested, does not change the binary of Gigabyte GA-H61MA-D3V.
Change-Id: I3bef75291d1ecb2c9c3c74d9e78caf84a1f726aa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
While we are at it, also:
- Rename related variables to match the register names.
- Update some comments to better reflect what some registers are about.
- Add various FIXME comments on registers that seem to be used wrongly.
With BUILD_TIMELESS=1, this commit does not change the coreboot build of:
- Asus P8H61-M PRO with native raminit.
- Gigabyte GA-H61MA-D3V with native raminit.
- Lenovo Thinkpad X230 with native raminit.
- Lenovo Thinkpad X220 with MRC raminit.
Change-Id: I5e5fe56eaa90842dbbdd1bfbbcb7709237b4c486
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Also change some of the types to match the register widths
of the controller. It is expected that these prototypes
will be used with SMBus host controllers inside AMD chipsets
as well, thus the change of location.
Change-Id: I88fe834f3eee7b7bfeff02f91a1c25bb5aee9b65
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38226
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add back options that were lost on postcar migration. Some of them
seem to be required for IOMMU initialization.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ie9cc772d7fcbefded8bab88f9960fef663dc7217
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37999
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add missing BeforeInitLate hooks in order to bring back certain options
that were lost on postcar migration. This will also allow to disable
CDIT again that caused AmdInitLate error on 00730F01.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I1226e9c0c8a92920f2569ec0f85d0be0adcc9e30
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Long-term plan is to support loading runtime configuration
from SPI flash as an alternative, so move these prototypes
outside pc80/.
Change-Id: Iad7b03dc985550da903d56b3deb5bd736013f8f1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38192
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Ensure that the operation order is always the same. This results in
changes to the binary, but the effective result is the same.
Change-Id: I9772832c60089b35889df7298e20a2bd02b35b00
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
A device object must contain either a _HID object or an _ADR object,
but should not contain both.
Change-Id: I727116cbc38fcd264c684da6ce766ea5e854f58c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Make it consistent with the more used cmos_write().
Change-Id: I9cf643c770e9819de08dbede48b73f3d4fe15bd7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38178
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These devices were just added in 727ac0d263 (AMD {SoC, AGESA, binaryPI}:
Don't use both of _ADR and _HID), but they don't provide any information
and are not referenced anywhere.
Change-Id: I862a3c43eb610e488eb7d9246feb94a6d1333ca0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
I used register names guessed on what the registers do, since the SNB
documentation marked those registers as reserved; the IVB documentation
(326765-005) has names for the registers, so I'll use those.
Change-Id: I2f1194438a56546d9836dd12635d064a900a2fd8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38008
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that romcc is gone, move cmos_post_init() into post.c, and remove
some preprocessor workarounds.
Change-Id: I0ee4551e476cdd1102e86e7efc74d5909f64a37b
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
