Commit Graph

1685 Commits

Author SHA1 Message Date
Vladimir Serbinenko c7db28c580 intel/nehalem: Fix soft reset detection.
Change-Id: I4575cddc35dc8309372beafec441d194bc145242
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5267
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-03-03 21:09:14 +01:00
Vladimir Serbinenko e1eef694ea intel/nehalem: Use non-powercycle reset.
Change-Id: Ibc2421a50e272a580461e4eacec6cfcd38654fe8
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5266
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-03-03 21:04:12 +01:00
Vladimir Serbinenko 9817a37416 nehalem/raminit: Don't touch clock generator in raminit.
Clock generator is mobo-specific. Don't touch it in raminit.

Change-Id: Ie114696b7fb13b8daee8dd1393d43bc609e149b3
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5265
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-03-03 20:55:26 +01:00
Chris Douglass e92155fbe6 intel/sandybridge: add PCI IDs for 6-Series PCH
The PCI ids are taken from:
	Intel® 6 Series Chipset and
	Intel® C200 Series Chipset
	Specification Update – NDA
	October 2013
	CDI / IBP#: 440377

Change-Id: Ib8418173fd36fd4109b3c4ec0d5543ca8e39ffa6
Signed-off-by: Christopher Douglass <cdouglass.orion@gmail.com>
Reviewed-on: http://review.coreboot.org/5226
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-01 06:51:08 +01:00
Vladimir Serbinenko 4337020b95 Remove CACHE_ROM.
With the recent improvement 3d6ffe76f8,
speedup by CACHE_ROM is reduced a lot.
On the other hand this makes coreboot run out of MTRRs depending on
system configuration, hence screwing up I/O access and cache
coherency in worst cases.

CACHE_ROM requires the user to sanity check their boot output because
the feature is brittle. The working configuration is dependent on I/O
hole size, ram size, and chipset. Because of this the current
implementation can leave a system configured in an inconsistent state
leading to unexpected results such as poor performance and/or
inconsistent cache-coherency

Remove this as a buggy feature until we figure out how to do it properly
if necessary.

Change-Id: I858d78a907bf042fcc21fdf7a2bf899e9f6b591d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5146
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-25 00:57:35 +01:00
Paul Menzel 20f83d5656 intel/*/acpi: Increase range length of MCHBAR buffer to 32 kB
Linux kernel 2.6.31 reports the warning below on Intel Ivy Bridge (with
FSP).

	resource map sanity check conflict: 0xfed10000 0xfed17fff 0xfed10000 0xfed13fff pnp 00:01

Since Sandy Bridge the length of the MCHBAR is 32 kB and it is already
used that way in other places.

	$ more src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl
	[…]
	OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR, 0x8000)
	[…]

So instead of 16 kB specify that 32 kB are decoded in that memory
range for Intel Sandy Bridge, Ivy Bridge and Haswell.

(Linux kernel 3.10 does not warn about that.)

Change-Id: Ie7a9356d9051c807833df85e4a806e5a9498473f
Reported-by: Norwich in #coreboot on <irc.freenode.org>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5192
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Werner Zeh
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-02-24 21:58:08 +01:00
Vladimir Serbinenko 902626c23c nehalem: Make SPD address map into parameter.
It's mobo dependent.

Change-Id: I7a9ba0fb7374a61178e9282acd8f10098435f1fd
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5253
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-02-20 23:18:10 +01:00
Vladimir Serbinenko 2ab8ec7cfb nehalem/raminit: Fix typo of NUM_CHANNELS instead of NUM_SLOTS.
Change-Id: I0fbfa8cb39881782bec3af5e43ff3c63dd2e4919
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5276
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-20 20:54:50 +01:00
Kyösti Mälkki 591031f4de sandy/ivy: Fix mrc.cache file in CBFS
The file was not recreated when configuration changed. One would
hit this bug when turning CHROMEOS on/off.

Also do not create mrc.cache with CHROMEOS at all.

Change-Id: I5b0ecde66589396b24967ce289bf65e20bb08825
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5211
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-17 06:13:31 +01:00
Aaron Durbin 6a360048a1 haswell: backup the default SMM region on resume
Haswell CPUs need to use the default SMM region for
relocating to the desired SMM location. Back up that
memory on resume instead of reserving the default
region. This makes the haswell support more forgiving
to software which expects PC-compatible memory layouts.

Change-Id: I9ae74f1f14fe07ba9a0027260d6e65faa6ea2aed
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5217
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-16 20:42:41 +01:00
Oskar Enoksson 42283e7994 Eliminate some ASL warnings
The ASL compiler warned about "Control Method should be made Serialized
(due to creation of named objects within)". This commit eliminates the
warnings by changing those NonSerialized into Serialized.

Change-Id: I639e769cf7a9428c34268e0c555a30c7dee1e04c
Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
Reviewed-on: http://review.coreboot.org/5189
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-02-13 01:04:02 +01:00
Kyösti Mälkki 972d5cf040 Move hexdump32() to lib/hexdump.
Needs printk and is not a console core function.

Change-Id: Id90a363eca133af4469663c1e8b504baa70471e0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5155
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-11 21:54:34 +01:00
Vladimir Serbinenko 30fe6120ca MTRR: Mark all prefetchable resources as WRCOMB.
Change-Id: I2ecfd9733b65b6160bc2232d22db7b16692a847f
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5149
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-06 00:55:13 +01:00
Aaron Durbin 029aaf627c x86: add common definitions for control registers
The access to control registers were scattered about.
Provide a single header file to provide the correct
access function and definitions.

BUG=chrome-os-partner:22991
BRANCH=None
TEST=Built and booted using this infrastructure. Also objdump'd the
     assembly to ensure consistency (objdump -d -r -S | grep xmm).

Change-Id: Iff7a043e4e5ba930a6a77f968f1fcc14784214e9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172641
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4873
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-28 23:12:27 +01:00
Alexandru Gagniuc b92f5e884d nb/sandybridge: Move MRC cache above mrc.bin
This small change greatly reduces CBFS fragmentation. There is now a
small gap of only 728 bytes between mrc.bin and mrc.cache, with the
64 KiB alignment maintained for mrc.cache -- assuming systemagent-r6
is used. The gap was just under 64 KiB before.

With this change, it is easier to accommodate fallback and normal
boot stages without having to manually place the stages in the highly
fragmented CBFS.

Change-Id: Ia2340c1928ed6e232949e053d1943c2f5737f741
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4763
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-01-24 19:54:33 +01:00
Vladimir Serbinenko 786c0f5fca nehalem: Fix SMRAM register address
Change-Id: If6646853039d15d6ba0fcf2b9b9b0658004be6e6
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4787
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-23 20:29:52 +01:00
Vladimir Serbinenko bca985557e X201: Move early nehalem S3 magic to right place.
This MCH magic needs to be done before GPIO.

Now S3 (Suspend-to-RAM) works on X201.

Change-Id: I319e57af52ff01083bfbffbcd883ac5f453320a1
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4632
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-23 19:56:52 +01:00
Vladimir Serbinenko f7a42de725 nehalem: Restore frequency ratio registers on S3 resume
Previously registers 274/265 and 6dc/6e8 were recomputed
which lead to a slightly different values. On
S3 resume it needs to be a perfect match.

Change-Id: I14f42c7659dde5f327979831fcb1f84ea0c78dee
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4634
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-23 19:56:31 +01:00
Vladimir Serbinenko f62669c966 nehalem: Small cleanup to raminit RE bindings
Change-Id: Ifd3f172a1c8a108909d1a7dae94f926b2778c2b1
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4633
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-23 19:55:57 +01:00
Vladimir Serbinenko 82926e1d16 nehalem: Move mrc.cache to 0xfffe0000.
On nehalem there is no MRC.bin. To avoid excessively fragment the CBFS,
put MRC.bin as high as possible.

Change-Id: Ia3f7aef5a1e62a42c9fa9ea0f6eec2b29eb6722d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4708
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-23 19:41:53 +01:00
Vladimir Serbinenko bd89699516 nehalem: Simplify acpi.c by using __SIMPLE_DEVICE__
Change-Id: I93351a2716cd58c2006400cecca1390b1704e94b
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4603
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-23 19:39:45 +01:00
Kyösti Mälkki 2d8520b275 CBMEM: Replace cbmem_initialize() with cbmem_recovery()
The replacement function confirms CBMEM TOC is wiped clean on power
cycles and resets. It also introduces compatibility interface to ease
up transition to DYNAMIC_CBMEM.

Change-Id: Ic5445c5bff4aff22a43821f3064f2df458b9f250
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4668
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2014-01-22 20:54:57 +01:00
Vladimir Serbinenko 9609823ed8 sandybridge/igd: Add brightness register descriptions
Needed for brightness control for Lenovo X230

Change-Id: Ib6d127d2e050671dd402c31af06ff4726f65156c
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4618
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2014-01-21 16:33:46 +01:00
Kyösti Mälkki 78938481eb Intel (sandy/ivy): Avoid calling cbmem_initialize() twice
Delay the copying of MRC cache data from CAR to CBMEM until after
sdram_initialize() returns and cbmem_initialize() completes.
Calling cbmem_initialize() twice would complicate the decision logic
of when CBMEM area needs to be wiped clean.

Change-Id: Ic59e94cb2436293efc47b52f7418f5dbf76c714a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4666
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-15 15:33:54 +01:00
Kyösti Mälkki cb08e169cf CBMEM intel: Define get_top_of_ram() once per chipset
Only have one definition of get_top_of_ram() function and compile
it using __SIMPLE_DEVICE__ for both romstage and ramstage.

Implemented like this on intel/northbridge/gm45 already.
This also adds get_top_of_ram() to i945 ramstage.

Change-Id: Ia82cf6e47a4c929223ea3d8f233d606e6f5bf2f1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3993
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-15 15:29:52 +01:00
Vladimir Serbinenko 5e73be2a7a sandybridge: Allow skipping mrc.cache
On X230 MRC fails if cache is passed to it. Until better solution is found
do not create mrc.cache

Change-Id: I7e70ebe3c4879e7ab33a9c95a0c9e40408ff5ca4
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4680
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-15 14:56:01 +01:00
Alexandru Gagniuc af4bd599ca lib: Make log2() available in romstage on ARM, not just x86
On x86, log2() is defined as an inline function in arch/io.h. This is
a remnant of ROMCC, and forced us to not include clog2.c in romstage.
As a result, romstage on ARM has no log2().
Use the inline log2 only with ROMCC, but otherwise, use the one in
clog2.c.

Change-Id: Ifef2aa0a7b5a1db071a66f2eec0be421b8b2a56d
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4681
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-13 04:03:06 +01:00
Vladimir Serbinenko c2ee6801e8 sandybridge: Use calls rather than asm to call to MRC.
Using asm as it's done currently is unsafe because caller-saved registers
are not declared as clobbered.

Using real call is nicer.

regparm((1)) ensures that argument is passed in %eax as expected.

Change-Id: I7449182582eaa53d4e473bc834b472edd8ee0d30
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4675
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12 18:04:38 +01:00
Vladimir Serbinenko 1287416822 CBFS: use cbfs_get_file_content whenever possible rather than cbfs_get_file
Number one reason to use cbfs_get_file was to get file length.
With previous patch no more need for this.

Change-Id: I330dda914d800c991757c5967b11963276ba9e00
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4674
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2014-01-12 17:41:58 +01:00
Vladimir Serbinenko 0af61b6c82 lib/cbfs_core.c: Supply size of file as well in cbfs_get_file_content
Change-Id: I5b93e5321e470f19ad22ca2cfdb1ebf3b340b252
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4659
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2014-01-12 17:41:02 +01:00
Vladimir Serbinenko a37383db80 Replace all occurences of sprintf with snprintf
THis reduces risks of bufer overflows.

Change-Id: I77f80e76efec16ac0a0af83d76430a8126a7602d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4279
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-10 18:08:16 +01:00
Vladimir Serbinenko e51210dbae MRC cache: determine flash size on runtime
It should be possible to put coreboot compiled for smaller chip by
putting it at the end of bigger chip. We already have chip size in
flash->size. Use it.

Tested on Lenovo X230.

Change-Id: If8ff03ed72671a9f2745ed4e759a04e83aa7cc37
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4612
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-01-06 10:06:21 +01:00
Vladimir Serbinenko 503e4fef17 X201: Fix native video init
Due to recent restructuring X201 native video init has disappeared from
config options. Put it back and fix compilation with it.

Change-Id: I6d9ba5da196c093abd2df89a6fe5efefece1fb3c
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4606
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-01-04 12:20:47 +01:00
Kyösti Mälkki ea8d4607ce AMD K8 (rev F): Move rev F0/F1 workaround to header
Place this in header so it works also when raminit_f.c and
raminit_f_dqs.c are not #included in romstage.c build.

The workaround remains to be disabled for all boards.

Change-Id: Iff0271ceb21ee1e28a1a31d6bbdb97e29d76461e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4568
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-30 07:20:38 +01:00
Kyösti Mälkki 5c62375222 AMD K8 (rev F): Move MEM_TRAIN_SEQ check to northbridge
Do it just to remove MEM_TRAIN_SEQ test under mainboard/ to see all
K8 rev F boards do the same things here.

Change-Id: If75035a4ef8882c2618d434d83ba59c408593d86
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4567
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-30 07:19:10 +01:00
Kyösti Mälkki 7d3045b517 AMD K8: Define MEM_TRAIN_SEQ only with K8_REV_F_SUPPORT
Change-Id: I601efbff03d0f0f59557b33be8d6928ede310b62
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4558
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-30 07:17:16 +01:00
Kyösti Mälkki 0946190e15 AMD K8 (rev-F): Always have RAMINIT_SYSINFO
K8 Rev F raminit code cannot be built without RAMINIT_SYSINFO,
so have the option enabled together with K8_REV_F_SUPPORT.
Also move the option under AMD K8.

Change-Id: I91fa0b4ae7e3e54fbcb4a4f91eb043956cd0fb60
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4582
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-29 19:45:50 +01:00
Kyösti Mälkki 2e77461051 AMD K8: Socket implies K8_REV_F_SUPPORT
K8_REV_F_SUPPORT is already set by all affected sockets, (AM2, F, S1G1).

Change-Id: If42a4178263d90a4e195fae0c78943ac9eda1ad6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4557
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-29 00:04:02 +01:00
Paul Menzel 475e1b9095 via: Write »access« without »m« at end
The comment was copied around so fix all occurrences using the following
command.

	$ git grep -l accessm | xargs sed -i 's/accessm/access/g'

Change-Id: I46e117c126c0f851cd5e95cf9e42a77ca5f80996
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/4577
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-27 19:49:46 +01:00
Kyösti Mälkki 6c57f64e58 AMD fam10: Drop MEM_TRAIN_SEQ
This config was for AMD K8 only.

Change-Id: I76276405b676d1dd4d5dbf8c5b94194a670ccb25
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4555
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-26 23:23:30 +01:00
Kyösti Mälkki 88a67f0cc9 AMD boards (non-AGESA): Cleanup earlymtrr.c includes
Change-Id: I5f4bf9dbaf3470dc83d3e980bb6cab10801e15c1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4523
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-12-26 23:19:11 +01:00
Kyösti Mälkki 50ecb9c111 usbdebug: Add option to disable console for romstage
If there is trouble setting up usbdebug, it may be useful to delay
usbdebug init to run in ramstage.

Change-Id: I31de5a06d3f9ce19f71c422cce0c8cb0fd50f396
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4488
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-12-23 10:35:39 +01:00
Idwer Vollering d26da9c8f0 Coding style: punctuation cleanup [1/2].
Clean up superfluous line terminators.

Change-Id: If837b4f1b3e7702cbb09ba12f53ed788a8f31386
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/4562
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2013-12-23 02:12:51 +01:00
Stefan Reinauer 190688c65f haswell: add option to change DqPinsInterleaved
Some mainboards will need to have this set.

Signed-off-by: Stefan Reinauer <reinauer@google.com>

Change-Id: I4732a9af822a60b5050d03d2ac4bb7cbd6c723d0
Reviewed-on: https://gerrit.chromium.org/gerrit/65722
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4474
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 12:02:56 +01:00
Duncan Laurie 3106d0ffce haswell: Misc updates from 1.6.1 ref code
These programming sequences were changed in the latest code.

Change-Id: Ia4b763a49542635713d11a9ee81f7e7f200bf841
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65612
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4466
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 12:02:50 +01:00
Duncan Laurie 727b5455fb Add a specific post code for S3 resume failures
If the firwmare is flashed and the MRC cache is blown away
then it is not possible to resume.

Right now this can be inferred from the event log but it can
be made very clear by adding a unique post code for this event.

1) boot falco
2) flash firmware
3) suspend and then resume
4) check for post code 0xef in log

0 | 2013-08-08 16:27:47 | Log area cleared | 4096
1 | 2013-08-08 16:27:47 | ACPI Enter | S3
2 | 2013-08-08 16:27:55 | System boot | 48
3 | 2013-08-08 16:27:55 | Last post code in previous boot | 0xef | Resume Failure
4 | 2013-08-08 16:27:55 | System Reset
5 | 2013-08-08 16:27:55 | ACPI Wake | S5

Change-Id: I7602d9eef85d3b764781990249ae32b84fe84134
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65259
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4458
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 12:02:43 +01:00
Duncan Laurie 289bac6a04 haswell: Add pei_data field for USB routing
The linux kernel will unconditionally route all USB
ports to the XCHI controller at boot.  The EHCI controller
can then be disabled, and it should be left disabled
by the reference code when this is done.

However not all OS may do this unconditional route,
so provide an option to the reference code binary to
enable this behavior.

Change-Id: Iedf5af54182bf109cd1119c1999e46300665d41e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63797
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4403
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 07:39:33 +01:00
Duncan Laurie 0a7c49efa0 HDA: Enable Mini-HDA and fix up PCH-HDA init
The SystemAgent contains a mini-hd audio controller at PCI 0:3.0
which uses the same verb table init sequence as the southbridge.

In order to avoid two copies of the verb table loading code I
separated out the HDA verb table functions into a file that can
be re-used and then added a minihd driver to the haswell northbridge.

The minihd verb table is the same across devices so it can live
within the minihd driver rather than needing to be specified in
each separate mainboard.

I also fixed up the driver for lynxpoint HDA by following the
reference code.

Without HDMI cable plugged in driver does not find any codec,
and it does not seem to re-probe when HDMI is connected.  We may
be missing kernel patches for this.

hda-intel 0000:00:03.0: no codecs found!

With a basic kernel patch to add 0x0a0c device ID to HDA driver
and with HDMI cable connected it is much happier:

snd_hda_intel 0000:00:03.0: irq 60 for MSI/MSI-X
input: HDA Intel MID HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:03.0/sound/card0/input9
snd_hda_intel 0000:00:1b.0: irq 61 for MSI/MSI-X
input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:1b.0/sound/card1/input10
input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card1/input11

Change-Id: Ifa587984be4fc2801704a0368b9cdf8379c2450e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/59336
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4318
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12 22:11:46 +01:00
Duncan Laurie 356833d0b5 haswell: Fix up GPU power management setup
New/more magic values from latest ref code.

Change-Id: Ia2655333b4daca86c2f2a76f5edcd55cdaf3f851
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/61334
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4356
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12 22:06:03 +01:00
Duncan Laurie 118d105a37 haswell: Export functions for CPU family+model and stepping
These are needed to enable workarounds/features on specific
CPU types and stepping.  The older northbridge function and
defines from sandybridge/ivybridge are removed.

Change-Id: I80370f53590a5caa914ec8cf0095c3177a8b5c89
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/61333
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4355
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12 22:05:57 +01:00
Duncan Laurie b17117904d haswell: Add ACPI support for Controllable TDP
Add ACPI Methods to enable and disable power limiting with PL1.
This can be used in ACPI Thermal Zone or in EC ACPI _QXX events.

This commit adds new unused methods and is fully tested with the
subsequent commit that makes use of these methods.

Change-Id: I9d8d23bfe9cf7c756ff8ab0412e5a010826b12db
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/60546
Reviewed-on: http://review.coreboot.org/4334
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2013-12-07 03:33:10 +01:00
Duncan Laurie c70353f1eb haswell: Misc power management setup and fixes
1) fix enable of power aware interrupt routing
2) set BIOS_RESET_CPL to 3 instead of 1
3) mirror PKG power limit values from MSR to MMIO on all SKUs
4) mirror DDR power limit values from MMIO to MSR
5) remove DMI settings that were from snb/ivb as they do
not apply to haswell

1) verify power aware interrupt routing is working by looking
in /proc/interrupts to see interrupts routed to both cores
instead of always to core0

BEFORE: 58:       4943          0   PCI-MSI-edge      ahci
AFTER:  58:       4766        334   PCI-MSI-edge      ahci

2) read back BIOS_RESET_CPL to verify it is == 3

localhost ~ # iotools mmio_read32 0xfed15da8
0x00000003

3) read PKG power limit from MMIO and verify it is the same
as the MSR value

localhost ~ # rdmsr 0 0x610
0x0000809600dc8078
localhost ~ # iotools mmio_read32 0xfed159a0
0x00dc8078
localhost ~ # iotools mmio_read32 0xfed159a4
0x00008096

4) read DDR power limit from MSR and verify it is the same
as the MMIO value (note this is zero based on current MRC input)

localhost ~ # rdmsr 0 0x618
0x0000000000000000
localhost ~ # iotools mmio_read32 0xfed158e0
0x00000000
localhost ~ # iotools mmio_read32 0xfed158e4
0x00000000

Change-Id: I6cc4c5b2a81304e9deaad8cffcaf604ebad60b29
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/60544
Reviewed-on: http://review.coreboot.org/4333
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2013-12-07 03:31:06 +01:00
Idwer Vollering 8c0cb8ae3b Correct file permissions.
Some files have incorrect/odd permissions,
correct them: remove unnecessary +x flags.

Change-Id: I784e6e599dfee88239f85bb58323aae9e40fb21c
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/4490
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-12-07 00:39:09 +01:00
Ronald G. Minnich 5bcca7e982 haswell: pull in the init code for FUI
Removed two unnecessary register sets, and did the power well a bit
more correctly. Also, added a register definition include file so we can
used constants instead of magic numbers.

We also set registers to common initialized values that are
needed for FUI, VBIOS, and kernel. This set of registers
appears to be an absolute bare minimum. Since we're hoping to use
FUI for all chipsets from this one forward, we unconditionally do the
setting here.

Signed-off-by: Ronald G. Minnich <rminnich@google.com>

Change-Id: Ife3f661ba010214d92b646b336f2b06645119f17
Reviewed-on: https://gerrit.chromium.org/gerrit/59988
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-on: http://review.coreboot.org/4328
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-05 20:23:23 +01:00
Marc Jones 54b8e7a0bb Add Intel FSP northbridge support Sandybridge and Ivybridge
Add support for Sandybridge and Ivybridge using the Intel FSP.
The FSP is different enough to warrant its own source files.
This source handle the majority of FSP interaction.

"Intel® Firmware Support Package (Intel® FSP) provides key
programming information for initializing Intel® silicon and can be
easily integrated into a boot loader of the developer’s choice.
It is easy to adopt, scalable to design, reduces time-to-market, and
is economical to build."
http://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html

Change-Id: Ib879c6b0fbf2eb1cbf929a87f592df29ac48bcc5
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/4015
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-12-04 18:45:13 +01:00
Alexandru Gagniuc 72dccce0c9 global: Fix usage of get_option() to make use of CB_CMOS_ codes
Do not directly check the return value of get_option, but instead compare
the returned value against a CB_CMOS_ error code, or against CB_SUCCESS.

Change-Id: I2fa7761d13ebb5e9b4606076991a43f18ae370ad
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4266
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-12-02 22:11:20 +01:00
Duncan Laurie bcfcfa4473 haswell: Update pei_data to match ref code
- Add a new USB location field
- Add a new "ddr_refresh_2x" field, enabled on Falco only
- Fix copy+paste bug in baskingridge

Checked that tREFI is halved during memory setup in the memory
training log:
tREFImin = 6240       << DEFAULT
  C(0).tREFI = 0xc30  << MODIFIED (=3120)
  C(0).tREFI = 0xc30  << MODIFIED (=3120)

Also ensure that the SD card is detected properly again.

Change-Id: Ie3a82c08df06ada9af56282b5255caefa56487f2
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/57349
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4219
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-02 21:53:51 +01:00
Shawn Nematbakhsh 932fbd659a Add DDR refresh config to pei data structure.
Allow platform customized DDR config, including forcing refresh rate to
2x.

Change-Id: I311ae7ddf25142153c94a3fc3fb0a36e03f50ab2
Reviewed-on: https://gerrit.chromium.org/gerrit/50476
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4213
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-01 23:19:38 +01:00
Christian Gmeiner bd7e8d8d2b AMD Northbridge LX: simplify get_top_of_ram()
Get rid of not needed dependency to gliu0table. This change is
needed to move get_top_of_ram() to raminit.c - as needed for
EARLY_CBMEM_INIT.

Boot tested on a Bachmann OT200.

Change-Id: I0bfe40c366a3537775d5c1ff8e0b1f5ac94320b7
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3380
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-11-26 07:36:26 +01:00
Duncan Laurie c7f2ab742b haswell: Add magic to turn on grahpics in normal mode
The haswell i915 kernel driver apparently expects the VBIOS
to set a few specific registers.  This sequence is enough to
make the driver happy without executing the VBIOS.

This also makes graphics work after suspend/resume.

Change-Id: I34937d55ffff8a9445442e6e6ca1bfc49869da63
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56806
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4195
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25 23:47:54 +01:00
Aaron Durbin b1c25e74af haswell: update pei_data data structure
Update and use the new pei_data data structure. Now that the
reference code is fixed it's possible to properly disable/enable
the USB2 and USB3 ports correctly.

Change-Id: I075c646e7574be354420b6e59507e8917a97d0f0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56594
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4185
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25 23:37:57 +01:00
Vladimir Serbinenko c6f6be0929 Support for nehalem northbridge
Including raminit

Change-Id: If1dd3855181481b8b928adf0fdb40b29d15897db
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4044
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-25 20:23:38 +01:00
Duncan Laurie 990555b0ef haswell: Update GT PM register value
This was changed to 0x80000000 in SA BWG 1.5.0.

Change-Id: Ic6773f45057f3eb93b2d93ee543e3db77fccf805
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/50852
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4166
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24 16:11:30 +01:00
Peter Stuge c6f0997ffc Northbridge: i945: Native VGA init: print the GMA and GTT addresses
The patch was made by Peter Stuge, I just split it
  and added a commit message.

Change-Id: Ieaaaa2611f7bb8968f01b16daefe7e2afe870f72
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/4001
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24 05:38:51 +01:00
Peter Stuge 03e4ac6671 Northbridge: i945: Native VGA init: use UMA address
The patch was made by Peter Stuge, I just split it
  and added a commit message.

Change-Id: I4e88c26b70ea8cb249d7613c749b3edc5e3b5e7f
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/4000
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24 05:38:02 +01:00
Denis 'GNUtoo' Carikli 2186b6538e lenovo/x60: native vga init: fix code style issues.
Change-Id: I054edffbb38b13559da10180fc2c6cd9929ba162
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3999
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24 05:37:02 +01:00
Paul Menzel 0ce5ebf0a0 northbridge/intel/i945/raminit.c: Remove set but unused variable `reg16`
Change-Id: Id4a758644a7b799e7662113c07d395e053525934
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3984
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-05 21:35:13 +01:00
Kyösti Mälkki 697927cc35 CBMEM: Define cbmem_top() just once for x86
It is expected this will always be a casted get_top_of_ram() call
on x86, no reason to do that under chipset.

Change-Id: I3a49abe13ca44bf4ca1e26d1b3baf954bc5a29b7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3972
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-10-15 13:18:22 +02:00
Kyösti Mälkki f8bf5a10c5 Revert "CBMEM: Always have early initialisation"
This reverts commit de1fe7f655.

While things appeared to work, there were actually invalid references
to CAR storage after CAR was torn down on boards without
EARLY_CBMEM_INIT. It was discussed use of CAR_GLOBAL should be
restricted to boards that handle CAR migration properly.

Change-Id: I9969d2ea79c334a7f95a0dbb7c78065720e6ccae
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3968
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-10-14 17:16:22 +02:00
Paul Menzel 7a00ca75d7 northbridge/amd/amdk8/raminit_f_dqs.c: Remove unused variable `reg` in `setup_mtrr_dqs()`
Change-Id: I7fc7819c329c058472031e82237be5c170b277f4
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3965
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
2013-10-13 19:10:10 +02:00
Stefan Reinauer fd4f4136e8 Rename cpu/x86/car.h to arch/early_variables.h
and add an ARMv7 version.

Change-Id: I14fbff88d7c2b003dde57a19bf0ba9640d322156
Signed-off-by: Stefan Reinauer <reinauer@google.com>
[km: rebased fa004acf8 from chromium git]
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3939
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2013-10-13 12:47:05 +02:00
Corey Osgood 5a7e127cd4 southbridge/cimx/sb900: Rename headers to match sb700 & sb800
Northbridge code includes these headers, so they all need to
have the same name to allow different combinations of northbridge
and southbridge. This changes the sb900 names to match sb700 & 
sb800, and points agesa/family12 and amd/torpedo to the new file 
names.

Change-Id: I7a654ce9ae591a636a56177f64fb8cb953b4b04f
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Reviewed-on: http://review.coreboot.org/3825
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-09-24 01:20:02 +02:00
Kyösti Mälkki de1fe7f655 CBMEM: Always have early initialisation
Assume EARLY_CBMEM_INIT=y everywhere and remove option from Kconfig.

If romstage does not make the cbmem_initialize() call, features like
COLLECT_TIMESTAMPS and early CBMEM_CONSOLE will execute during
romstage, but that data will get lost as no CAR migration is
executed.

Change-Id: I5615645ed0f5fd78fbc372cf5c3da71a3134dd85
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3917
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-21 06:26:54 +02:00
Kyösti Mälkki c0beb6d418 timestamps epia-m850: Cleanup without enabling timestamps
Remove the existing hack, platform needs a fix for EARLY_CBMEM_INIT.

Change-Id: I7ce373c9698878d9fa056983e4fb571a68239c52
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3913
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-21 06:21:13 +02:00
Kyösti Mälkki f9f74afdd7 CBMEM x86: Unify get_cbmem_toc()
Remove any chipset-specific implementations and use arch-specific
implementation of get_cbmem_table() instead.

Change-Id: I338ee2c1bd51f5e517462115170dc926e040159e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3907
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11 07:18:53 +02:00
Kyösti Mälkki dcb688e5ec CBMEM: Unify get_top_of_ram()
Change-Id: Ic40a51638873642f33c74d80ac41cf082b2fb177
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3904
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11 07:16:00 +02:00
Kyösti Mälkki 42f4651434 CBMEM northbridges: Remove references to global high_tables_base
Use the new helper function set_top_of_ram() to remove remaining
uses of high_tables_base and _size under northbridge/.

Change-Id: I6b0d9615002ed2aff578c5811d7bd43dd2594453
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3561
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11 07:09:47 +02:00
Kyösti Mälkki 2b790f6512 CBMEM AMD: Fix calls to set_top_of_ram_once()
We can postpone the call to set_top_of_ram_once() outside the
loops and make just one call instead.

As set_top_of_ram() is now only called once, it is no longer
necessary to check if high_tables_base was already set.

Change-Id: I302d9af52ac40c7fa8c7c7e65f82e00b031cd397
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3895
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-09-11 07:09:21 +02:00
Kyösti Mälkki e7e847cd5c CBMEM AMD: Remove references to global high_tables_base
Prepare for removal of globals high_tables_base and _size
by replacing the references with a helper function.

Added set_top_of_ram_once() may be called several times,
but only the first call (with non-zero argument) takes effect.

Change-Id: I5b5f71630f03b6a01e9c8ff96cb78e9da03e5cc3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3894
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11 07:06:15 +02:00
Kyösti Mälkki 6f9fa8634a intel/i5000: remove explicit pcie config accesses
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove
the pcie explicit accesses. The default config accesses use
MMIO.

Change-Id: Ibe2fea68854af465900e443959a745a7167fb753
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3813
Tested-by: build bot (Jenkins)
2013-09-10 20:23:37 +02:00
Kyösti Mälkki 8aa7e83994 intel/i945 intel/i82801gx: remove explicit pcie config accesses
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove
the pcie explicit accesses. The default config accesses use
MMIO.

Change-Id: I46e69154cf576ddb642c34b6dd2bc0d27cc19b7e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3811
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-10 18:22:04 +02:00
Kyösti Mälkki 35a7249183 intel/gm45: Use MMCONF_SUPPORT_DEFAULT
Change all PCI configuration accesses to MMIO for all boards
with gm45 chipset. To enable MMIO style access, add explicit
PCI IO config write in the bootblock.

Change-Id: Id1c839b7d669946e0ca8b6837e5152ebcb9cd334
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3600
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-10 18:19:58 +02:00
Stefan Reinauer 3c46ca33a1 Sandybridge/Ivybridge: Unify and fix Kconfig defaults
Change-Id: Ia4a5530e6a1a1fd2dec6f348ff163b5c7a8cd4cd
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3830
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-08-29 00:52:41 +02:00
Kyösti Mälkki 3f9a62e5ad Add pci_devfn_t and use with __SIMPLE_DEVICE__
Declare the functions that may be used in both romstage and ramstage
with simple device model. This will later allow to define PCI access
functions for ramstage using the inlined functions from romstage.

Change-Id: I32ff622883ceee4628e6b1b01023b970e379113f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3508
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-24 07:37:12 +02:00
Paul Menzel 4159a8012e Correct spelling of shadow, setting and memory
Change-Id: Ic7d793754a8b59623b49b7a88c09b5c6b6ef2cf0
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3768
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-16 22:25:56 +02:00
Bruce Griffith 42e11f5a03 AMD Richland: Add new graphics device IDs to Family 15, Models 10-1F
Change-Id: Ic7fdedc0a22e7664f14b105f2f7cecd8f55980be
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3857
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-08-15 18:41:44 +02:00
Mike Loptien ac90d8013a AMD Kabini: Split DSDT into common sections
Split the Family16 (Kabini) DSDT file into logical regions.
Olive Hill is the only mainboard and Kabini is the only NB/CPU
currently using Family16 AGESA code.

Change-Id: I9ef9a7245d14c59f664fc768d0ffa92ef5db7484
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/3821
Tested-by: build bot (Jenkins)
2013-08-15 18:40:11 +02:00
Kyösti Mälkki fd98c65b9d intel/sandybridge intel/bd82x6x: remove explicit pcie config accesses
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove
the pcie explicit accesses. The default config accesses use
MMIO.

Change-Id: I58c4b021ac87a035ac2ec2b6b110b75e6d263ab4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3810
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-09 23:20:52 +02:00
Kimarie Hoot 0cc33da553 ASUS F2A85-M: Split DSDT into common sections (as per Parmer)
Rearranged the F2A85-M DSDT file to match the functionality found
on Parmer.  As with the Parmer implementation, the F2A85-M dsdt.asl
file in the mainboard directory contains only #include references to
the appropriate files.

As with Parmer, some include files have no content but are left as a
template for other platforms and as placeholders for completing the
ACPI implementation for F2A85-M.

Change-Id: Ic72cb6004538ca9d9f79826b9b3c8d6aeb25017c
Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com>
Reviewed-on: http://review.coreboot.org/3805
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin@se-eng.com>
2013-08-08 05:58:29 +02:00
Bruce Griffith 76db07e8c2 AMD Kabini: Add map_oprom() function for Vendor/Device IDs
Change-Id: I14285f0677003fbf8b9b112207af202658807894
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Bruce Griffith <bruce.griffith@se-eng.com>
Tested-by: Bruce Griffith <bruce.griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3806
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-08-05 22:13:20 +02:00
Siyuan Wang 3e32cc00d1 AMD Kabini: Add northbridge AGESA wrapper (new AMD processor)
src/arch/x86/boot/tables.c and src/include/device/pci_ids.h are also
changed because these two files depend on F16kb northbridge macros

Change-Id: Iedc842f0b230826675703fc78ed8001a978319c5
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Bruce Griffith <bruce.griffith@se-eng.com>
Tested-by: Bruce Griffith <bruce.griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3782
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-08-05 18:23:34 +02:00
Kyösti Mälkki ef84401149 Add directive __SIMPLE_DEVICE__
The tests for __PRE_RAM__ or __SMM__ were repeatedly used
for detection if dev->ops in the devicetree are not available
and simple device model functions need be used.

If a source file build for ramstage had __PRE_RAM__ inserted
at the beginning, the struct device would no longer match the
allocation the object had taken. This problem is fixed by
replacing such cases with explicit __SIMPLE_DEVICE__.

Change-Id: Ib74c9b2d8753e6e37e1a23fcfaa2f3657790d4c0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3555
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-01 15:57:11 +02:00
Stefan Reinauer 0aede1185b Drop unused EXTERNAL_MRC_BLOB
The Kconfig variable EXTERNAL_MRC_BLOB is not used.
Drop it.

Change-Id: I3caa5c2b6bcf5d2c13b6987da8ab3987bad0e506
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3829
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2013-07-31 22:02:41 +02:00
Steve Goodrich bf0988b0a2 AMD Fam15tn: Split DSDT into common sections
Split the Parmer, Family 15tn, and Hudson DSDT into groups.  This splits
the DSDT table into includable ASL files which carry details specific
to the Family 15tn APU, the Parmer platform, and the Hudson FCH.  The
dsdt.asl file in the mainboard directory contains only #include
references to the appropriate files.

Initially, this split was done by moving each piece of functionality
into its own file (e.g. IRQ routing and mapping, processor tree, sleep
states and sleep methods, etc.) and those pieces were #included in
dsdt.asl to ensure an exact match (via acpidump/acpixtract/iasl -d)
with the extant version of the table.  Once the new tables were found
to exactly match the existing tables, the pieces were rearranged into
reasonable groups (e.g. fch.asl, northbridge.asl, pci_int.asl, etc.).

Some include files have no content but are left as a template for
other platforms and as placeholders for completing the ACPI
implementation for Parmer (e.g. thermal.asl, superio.asl, ide.asl,
sata.asl, etc.).

Change-Id: I098b0c5ca27629da9bc1cff1e6ba9fa6703e2710
Signed-off-by: Steve Goodrich <steve.goodrich@se-eng.com>
Reviewed-on: http://review.coreboot.org/3629
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-07-16 16:14:56 +02:00
Kyösti Mälkki 33e5df3f25 Set PCI bus operations at buildtime for ramstage
PCI bus operations are static through the ramstage, and should be
initialized from the very beginning. For all the replaced instances,
there is no MMCONF_SUPPORT nor MMCONF_SUPPORT_DEFAULT selected for
the northbridge, so these continue to use PCI IO config access.

Change-Id: I658abd4a02aa70ad4c9273568eb5560c6e572fb1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3607
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-11 01:29:35 +02:00
Kyösti Mälkki 9e7806a788 usbdebug: Move ehci_debug_info allocation
Move ehci_debug_info allocation from console to lib, as console code
was only built for ramstage.

Implement dbgp_ehci_info() to return the EHCI context. Alread alias this
as dbgp_console_input() and _output() to return the console stream context
later on.

Change-Id: Id6cc07d62953f0466df61eeb159e22b0e3287d4e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3625
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 23:23:55 +02:00
Stefan Reinauer 6adef0847e Rename hardwaremain() to main()
... and drop the wrapper on ARMv7

Change-Id: If3ffe953cee9e61d4dcbb38f4e5e2ca74b628ccc
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3639
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 02:40:30 +02:00
Ronald G. Minnich 78c3e33550 FUI: reorganize include files
We've got enough of a handle on this to realize some things:
drm_dp_helper.h is by design device and architecture independent
i915.h is common to most intel graphics chipsets going back several years
i915_reg.h is as well

Move these files to src/include/device, and adjust the .c files accordingly.

Change-Id: I07512b3695fea0b22949074b467986420783d62a
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3637
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 02:39:42 +02:00
Kyösti Mälkki 54d6abd276 Drop some duplicates of PCI-e config functions
These are not specific to Intel. Further work needs to be done to
combine these with MMCONF_SUPPORT in arch/io.h.

Change-Id: Id429db2df8d47433117c21133d80fc985b3e11e4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3502
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 01:24:42 +02:00
Kyösti Mälkki 872c922296 Fix MMCONF_SUPPORT_DEFAULT for ramstage
Define at one place whether to use IO 0xcf8/0xcfc or MMIO via
MMCONF_BASE_ADDRESS for PCI configuration access funtions in ramstage.

The implementation of pci_default_config() always returned with
pci_cf8_conf1. This means any PCI configuration access that did
not target bus 0 used PCI IO config operations, if PCI MMIO config
was not explicitly requested.

Change-Id: I3b04f570fe88d022cd60dde8bb98e76bd00fe612
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3606
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-07-10 00:57:09 +02:00
Ronald G. Minnich 4f78b18749 fox_wtm2: First step support for coreboot-based graphics startup
This code is the initial version of FUI for haswell and wtm2.

The code is simplified from before in many ways. I've gotten rid of
the opcode table, because it obscured meaning and I don't think it is
needed any more. Register sets, mainly used for reset, are just lines
of code -- not many of them. There are a bunch of not-yet-documented
registers here; the VBIOS seemed to think they were necessary and
testing shows they seem to be right.

As a bit of added paranoia, we always include the VBIOS code as our
emergency recovery path. You have to run it now anyways, so this is no
regression from our current situation; and, if all goes well, in a
week (or so), you'll never have to run it again, but like the Force
and nose hair, it will be with you always.

The code can return in three ways. The first, best way is success:
panel is up and the VBIOS need not run. The second mode is that we
tried to light up the panel but could not, for some reason, but will
return with the panel partly up. In this case, it's ok not to power
cycle the panel. The third, worst case, which will NEVER happen, ha
ha, is that we have to turn the panel off and wait the required 600ms
for it to cycle. Life sucks sometimes. This failure mode is in the
'hang on we're going to fix it' category now that we have ramstage in
RW.

The Big Goal here is to create something other coreboot ports can use
as well. The guys doing the x60 report that the link FUI works,
without too many mods, on that chipset, so it seems Intel is keeping
things from changing too much over time.

Also, again, please note: this and the next 3 versions will ALWAYS fail.
The goal is to verify the correctness of the recovery path.

The bizarre tab-space formatting in drm_dp_helper.h is from the original,
as in i915_reg.h

Change-Id: I6ecf454633029d185c29d470980b5a0f3114a8ce
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3635
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-09 22:16:37 +02:00
Ronald G. Minnich 2a66d6b804 FOX_WTM2: First pass at FUI.
This lights up the display. We don't get graphics but we are missing the gttsetup
at this point, so that is no shock. The real shock is that anything works at all.

Change-Id: I03fc470334e96878aeb8465044b3cc9c90378735
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3634
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-09 22:16:09 +02:00
Kyösti Mälkki 9e974232e4 intel/i5000: Use MMCONF_SUPPORT_DEFAULT
Change all PCI configuration accesses to MMIO on two boards
with i5000 chipset. To enable MMIO style access, add explicit
PCI IO config write in the bootblock.

Change-Id: I26f1c2da5ae98aeeda78bdcae0fb1e8c711a3586
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3601
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-04 03:10:22 +02:00
Kyösti Mälkki 575e6817e6 Move select MMCONF_SUPPORT under northbridge (fix)
I missed the board with gm45 when I moved MMCONF_SUPPORT lines.

Also, the intel/i3100 does not have MMCONF_SUPPORT implemented
even though it was previously selected for intel/eagleheights board.

Change-Id: I9c7f6b0a150b4d54288a1e015277b9d98467fca4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3598
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-04 03:06:53 +02:00
Kyösti Mälkki 032c23db08 intel/i945: Use MMCONF_SUPPORT_DEFAULT
Change all PCI configuration accesses to MMIO on all boards
with i945 chipset. To enable MMIO style access, add explicit
PCI IO config write in the bootblock.

Change-Id: Ia1ab73f1a2dcda87db4eb9b2ffddc6f7b4382b01
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3584
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-07-04 00:53:39 +02:00
Kyösti Mälkki fbdb085549 intel/sandybridge intel/ivybridge: Use MMCONF_SUPPORT_DEFAULT
Change all PCI configuration accesses to MMIO on all boards
with SandyBridge and IvyBridge. To enable MMIO style access,
add explicit PCI IO config write in the bootblock.

Change-Id: I8f957a80bf57df000897c5a080dd5ff131b1ec0d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3576
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-07-04 00:53:06 +02:00
Kyösti Mälkki 15c4ab7adf Move select MMCONF_SUPPORT under northbridge
Move/remove MMCONF_SUPPORT reference under mainboard Kconfig, as
that feature originates from northbridge and cannot be disabled
for a single mainboard.

Change-Id: I6d6861079876ddddaff90b10f18edb6936e93bd0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3589
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-03 19:34:11 +02:00
Paul Menzel abe6847cd2 Intel GM45, 945, Sandy Bridge: Unify `delay.c` and `udelay.c`
Use the same indentation, comment placement and spelling of words.
Run `indent -linux …`.

Change-Id: Id5765c45b28058cdd50ee4c0a1fd9f645ad7f3f8
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3220
Reviewed-by: Nico Huber <nico.huber@secunet.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-02 21:07:44 +02:00
Dave Frodin 59158b2fb0 Make setting MAX_PIRQ_LINKs depend on NORTHBRIDGE_VIA_VX900
The MAX_PIRQ_LINKS is defined in src/Kconfig with a default value
of 4. The src/northbridge/via/vx900/Kconfig also defines
MAX_PIRQ_LINKS with a default of 8 and it ends up giving us
a value of 8 for non-VIA platforms.

Change-Id: Iee1938d38a93ab7c35c8cb6fe9656a92cf3fa21e
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/3586
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-07-02 16:24:04 +02:00
Bruce Griffith 53abac1767 amd/cimx/rd890/amd.h: Eliminate redefinition of NULL
This change replaces a redefinition of NULL with the standard
definition from <stddef.h> to eliminate a compiler redefinition
warning.

Change-Id: I441fa569f545c0efb00284b5ee58aa27cb6617ba
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3540
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-28 01:36:29 +02:00
Bruce Griffith 58fff9d44f amd/agesa/family15/northbridge.c: Delete unused variable
This change eliminates an unused variable that causes a build warning.

Change-Id: I02487c7dd80d458f562d7afe1827eefcc0fb678b
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3526
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-28 01:35:59 +02:00
Stefan Reinauer 1cc3416f5f Add support to enable/disable builtin GbE (again)
This requires a new system agent binary (v6 / v11 on haswell).
Note that the existing system agent binaries are long time obsolete
and won't work with current coreboot, so this update is overdue.

Change-Id: I48d8649576ca84d2b85ab082ce06f3462e189059
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3568
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-28 01:35:39 +02:00
Kyösti Mälkki 714212a421 Revert "Add support to enable/disable builtin GbE"
This reverts commit d358a506c4

http://review.coreboot.org/#/c/3514/ comments:
The pei_data version changed to 6, so new binaries are needed.

However, demand for new binary blob is not referenced with this commit nor is git submodules hash updated. Also the new binary blob almost doubles its size and no longer fits in the allocation sandybridge defines.

Change-Id: I84eb70517d5b9278c611fdfa587a71f6ca0f657f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3553
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-27 00:27:14 +02:00
Andrew Wu 8b9d4f3296 Vortex86EX northbridge.c : Remove Vortex86DX PCI N/B related code.
6021 is Vortex86DX northbridge PCI device ID, not for Vortex86EX.

Change-Id: I9bea799c9033adbcfacc8ad47052280a32f9ee59
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3529
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-25 16:16:42 +02:00
Kyösti Mälkki 59fb82aab1 intel/sch: Use MMCONF_BASE_ADDRESS
For iwave/iWRainbowG6 using intel/sch, MMCONF_BASE_ADDRESS was unused
and different from hardware setting. Change that to match hardware
programming.

Change-Id: I3324b7ea0e6f092206d4b6b791476d538e826657
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3507
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-25 08:03:52 +02:00
Kyösti Mälkki 6aeb4a269c AMD: Drop empty root_complex
There are no files to build left under AMD nortbridge/x/root_complex
directories. For some cases, even the Kconfig file was no longer sourced.
Remove all such references and empty files.

For devicetree.cb treat component paths with "/root_complex" in them valid
even when the directory does not exists. This is because AMD boards us this
dummy chip component as the root node in their devicetree.cb.

The generated devicetree file static.c remains unchanged.

Change-Id: I9278ebb50a83cebbf149b06afb5669899a8e4d0b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3434
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-24 17:22:44 +02:00
Rudolf Marek 5ce0506618 AMD Fam15tn: Add support for AGESA runtime allocation in CBMEM
The IOMMU AGESA needs a reserved scratch space and it wants
to allocate the stuff for runtime. So provide a simple
allocator for 4 KB CBMEM page.

Change-Id: I53bdfcd2cd69f84fbfbc6edea53a051f516c05cc
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/3315
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-24 00:53:52 +02:00
Rudolf Marek 88ebbeb7e2 AMD Fam15tn: Add IOMMU BAR allocation to northbridge
For IOMMU we need to allocate a 512 KB BAR in a non-standard
location. Use the standard allocator for that and limit the BAR
to 32-bits to be compatible with older systems.

Change-Id: I44414ce6b264b7f1c086a9b1c7ea275a0830205e
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3314
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-24 00:52:50 +02:00
Kyösti Mälkki eac00d2dbb intel/sandybridge: Locate CBMEM TOC early in ramstage
This patch allows the use of migrated CAR_GLOBAL variables from
the very beginning of ramstage. Without the patch, CAR_GLOBALS were
not available until northbridge set_resources().

Change-Id: Ifd4ab2ed52e07dcbe8c77e2e460dc483323e93c0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3513
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-06-22 20:48:08 +02:00
Andrew Wu 0651072597 Add support for DMP Vortex86EX PCI northbridge.
Change-Id: I60675a357f9db430ebb59b17be6d8c92a9cadf43
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3511
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-22 17:33:27 +02:00
Stefan Reinauer d358a506c4 Add support to enable/disable builtin GbE
In case we are going to use this in future designs.

BUG=none
TEST=none
BRANCH=none

Change-Id: I750addf10e4fe6f8240f8c8262253f8af7027e29
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/55844
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3515
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-21 19:36:55 +02:00
Patrick Georgi 483ff82539 sandybridge: Store MRC cache in CBFS
Location is hard-coded right now, which isn't optimal.
It must be chip erase block aligned, which might fail on some flash chips
(it's 64k aligned which should work for most cases).

Change-Id: I6fe0607948c5fab04b9ed565a93e00b96bf44986
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/3497
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-06-20 12:43:01 +02:00
Kyösti Mälkki 59d0d159f4 AMD: Kconfig cleanup
Change-Id: I21182eae1d389790c330f27e6a830d91c3ee4eb6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3433
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-13 01:08:12 +02:00
Alexandru Gagniuc 560433b493 VX900: Use MIN/MAX from stdlib.h instead of redefining them
Change-Id: I2dd693b300085493baa65bb652df8d6cce80b63b
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/3431
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-06-10 23:11:48 +02:00
Alexandru Gagniuc 23211b0200 VIA VX900: Add minimal ramstage needed to boot linux
This is the minimal code needed to get past ramstage, load SeaBIOS, jump
to GRUB2, and boot linux (or load memtest). See individual source files for
the status of each individual component.

Change-Id: Ib7d5d7593c945f18af2c2fc5e0ae689ba66131a2
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/3419
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-10 22:58:21 +02:00
Alexandru Gagniuc 7d31e7c138 VX900: Add DDR3 initialization
The VX900 can be connected to either DDR2 or DDR3. On my board, it is
DDR3, hence why there is no and will be no DDR2 code from my side.

This is the raminit for DDR3 dimms for the VX900. I like the term
"raminit" better than "memory training". This is a device, not a dog.

What works and what doesn't is documented in the code. It does not
make sense to hide that information in a commit message.

Change-Id: Ib2ebc10e6d4d22d0a937fe9e895c17ce79153c88
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/3417
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-10 22:56:06 +02:00
Alexandru Gagniuc 88a302346f VX900: Add support for early romstage
Add support for VX900 early initialization up until, but not including
raminit. Add the basic infrastructure, add a romstrap table, and
functionality to configure the CPU bus and SMBus.

This code is necessary and sufficient to prepare us for raminit.

Change-Id: Icc9c41e4927b589f17416836f87a6a5843b24aa7
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/3372
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-10 22:30:04 +02:00
Denis 'GNUtoo' Carikli 7ed739445b i945: Add Display defines for int15h handler.
Change-Id: I7bc99761c7047e64b4e29c307ad779cec49c17c8
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3306
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-06-07 02:49:06 +02:00
Denis 'GNUtoo' Carikli fd39ddd635 Intel 945: Select LAPIC_MONOTONIC_TIMER for X86EMU_DEBUG_TIMINGS
X86EMU_DEBUG_TIMING is needed for producing i915tool
  compatible output. So add its dependencies to the
  i945’s Kconfig in order to be able to use X86EMU_DEBUG_TIMINGS,
  which depends on HAVE_MONOTONIC_TIMER which
  LAPIC_MONOTONIC_TIMER provides/selects.

Note that UDELAY_LAPIC is already selected by the Intel CPU.

Change-Id: Ie834ebc92e527eb186a92b39341ebd0a08889fb0
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3356
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-05 01:07:14 +02:00
Ronald G. Minnich a296ce75e3 Move the MARK_GRAPHICS_MEM_WRCOMB to x86 architecture
The MARK_GRAPHICS_MEM_WRCOMB was spreading like a cancer
since it was defined in sandybridge. It is really
more of an x86 thing however, and we now have
three systems that can use it.

I considered making this more general, since it technically
can apply to PTE-based systems like ARM, and maybe we should.
But the 'WRCOMB' moniker is usually closely tied to the x86.

Change-Id: I3eb6eb2113843643348a5e18e78c53d113899ff8
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/3349
Tested-by: build bot (Jenkins)
2013-06-04 22:36:03 +02:00
Christian Gmeiner 7bc3575458 AMD Northbridge LX: get rid of #include "northbridge/amd/lx/raminit.c"
Change-Id: I249c63646267ebe8dd8e06980aa6367a16fe7297
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3370
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 17:56:48 +02:00
Christian Gmeiner c4e07bb503 AMD Northbridge LX: convert spd_read_byte() to non-static version
Change-Id: Ie329606852dfd7109acb694e9a9ff851b023cc63
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3369
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 17:56:35 +02:00
Christian Gmeiner e2dc80ceac AMD Northbridge LX: rename get_systop() to get_top_of_ram()
Change-Id: I6126d575b8289f76b38858304836e3037200bcdb
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3367
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 17:55:45 +02:00
Christian Gmeiner 84ae76caf8 AMD Northbridge LX: include northbridge.h in raminit.c
Change-Id: Ic2f50ae184678637c611757d3391826c1d2719a1
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3365
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 17:55:15 +02:00
Christian Gmeiner 194ec4d4d5 AMD Northbridge LX: make GeodeLinkSpeed() function prototype non-static
Change-Id: Id914be1ae4dac96c51f2640f056af4ce58a248eb
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3364
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 17:54:56 +02:00
Christian Gmeiner 6f9f785d9b AMD Northbridge LX: add some missing includes
This commit fixes problems if we build raminit.c
for romstage.

Change-Id: Ic1380f3635ac28b939fa2a8ce614814012455c44
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3363
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 17:54:27 +02:00
Christian Gmeiner eb6322f4b0 AMD Northbridge LX: make sdram_* function prototypes non-static
In order to get rid of the bad #include "northbridge/amd/lx/raminit.c"
line we need to do some prepartion steps. This commit is one of them.

Change-Id: I33173660bbda8894e7672e41e1b994d254d7ae8a
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3362
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 17:53:57 +02:00
Siyuan Wang 29840e234c AMD Fam 15tn: Use all memory on systems with more than 4 GB
Take a Parmer board with 4G memory as an example.

Use 'cat /proc/meminfo' to check memory, it reads 'MemTotal 3327540kB'.
Parmer uses 512M as video memory when it has 4G.
3327540+512*1024 = 3851828(kB), so some memory is lost.

When Parmer has 4G memory, TOM2 low is 0x1F000000, TOM2 high is
0x00000001. But in e820 table or coreboot table, the last item is

    6: 0000000100000000 - 0000000118000000 = 1 RAM

This is not correct, it should be

    6: 0000000100000000 - 000000011f000000 = 1 RAM

This patch changes the memory layout when TOM2 is set.

Change-Id: I4e2d163ae8fe1e65ddc384b520a5112ca067b1d1
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3366
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 17:48:47 +02:00
Aaron Durbin 27435d3bcd haswell: fix overflow handling TOUUD
It's possible that the TOUUD can be set to less than
4GiB. When that is the case the size_k variable is
an extremely large value. Instead ensure TOUUD is greater
than 4GiB before adding said resources.

Change-Id: I456633d6210824e60665281538300fd15656b86d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3352
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-03 17:30:09 +02:00
Paul Menzel 42409e8732 northbridge/amd/amdmct: Use `static const` instead of `const static`
From ISO C99 standard: »The placement of a storage-class specifier
other than at the beginning of the declaration specifiers in a
declaration is an obsolescent feature.«

Found at <http://www.approxion.com/?p=41>.

The following command was used to make the change.

    $ git grep -l 'const static' src/ | xargs sed -i 's/const static/static const/'

As asked by Bruce Griffith, the changes in `src/vendorcode` were
reverted as that is what AMD prefers.

The same change was done already for AMD Persimmon in the following
commit.

    commit 824e192809
    Author: Jens Rottmann <JRottmann@LiPPERTembedded.de>
    Date:   Wed Feb 20 21:24:20 2013 +0100

        Persimmon: platform_cfg.h: Declare codec arrays as `static const`

        Reviewed-on: http://review.coreboot.org/2474

Change-Id: I233c83fdc95ea4f83f7296c818547beb52366a3d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3197
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-06-03 08:20:54 +02:00
Ronald G. Minnich 5750fddcba Intel GM45, 945, SNB: Move `multiply_to_tsc()` to `tsc.h`
multiply_to_tsc was being copied everywhere, which is bad
practice. Put it in the tsc.h include file where it belongs.
Delete the copies of it.

Per secunet, no copyright notice is needed.

This might be a good time to get a copyright notice into tsc.h
anyway.

Change-Id: Ied0013ad4b1a9e5e2b330614bb867fd806f9a407
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/3242
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-05-25 14:22:06 +02:00
Paul Menzel 51837f9dac Intel Sandy Bridge: udelay.c: Change comparison from <= to <
Currently code in `udelay.c` differs between the Intel northbridges
GM45, 945 on the one hand and Sandy Bridge on the other hand.

The reason for this is that a wrong comparison > was used.

The following commit

    commit 784ffb3db6
    Author: Sven Schnelle <svens@stackframe.org>
    Date:   Tue Jan 10 12:16:38 2012 +0100

        i945: fix tsc udelay()

        Reviewed-on: http://review.coreboot.org/530

fixed the sign from > to <, whereas Stefan Reinauer changed it from
> to <= before adding the Sandy Bridge port in the following commit.

    commit 00636b0dae
    Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Date:   Wed Apr 4 00:08:51 2012 +0200

        Add support for Intel Sandybridge CPU (northbridge part)

        Reviewed-on: http://review.coreboot.org/854

As there are no technical reasons for this difference, unify this
between the chipsets. See the discussion of the other patch set in
Gerrit [1].

[1] http://review.coreboot.org/#/c/3220/1/src/northbridge/intel/i5000/udelay.c

Change-Id: I64f2aa1db114ad2e9f34181c5f3034f6a8414a11
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3259
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-05-23 10:44:36 +02:00
Nico Huber 393619b9a6 intel/gm45: Add more debug output to read/write training
Add debug output for the timing values of the edges found during
read and write training.

Now, output for one DIMM of DDR3-1066 in a roda/rk9 looks like:

[...]
Lower bound for byte lane 0 on channel 0: 0.0
Upper bound for byte lane 0 on channel 0: 8.4
Final timings for byte lane 0 on channel 0: 4.2
Lower bound for byte lane 1 on channel 0: 0.0
Upper bound for byte lane 1 on channel 0: 10.2
Final timings for byte lane 1 on channel 0: 5.1
Lower bound for byte lane 2 on channel 0: 0.0
Upper bound for byte lane 2 on channel 0: 7.5
Final timings for byte lane 2 on channel 0: 3.6
Lower bound for byte lane 3 on channel 0: 0.0
Upper bound for byte lane 3 on channel 0: 11.4
Final timings for byte lane 3 on channel 0: 5.6
Lower bound for byte lane 4 on channel 0: 0.0
Upper bound for byte lane 4 on channel 0: 9.4
Final timings for byte lane 4 on channel 0: 4.6
Lower bound for byte lane 5 on channel 0: 0.0
Upper bound for byte lane 5 on channel 0: 11.2
Final timings for byte lane 5 on channel 0: 5.5
Lower bound for byte lane 6 on channel 0: 0.0
Upper bound for byte lane 6 on channel 0: 8.4
Final timings for byte lane 6 on channel 0: 4.2
Lower bound for byte lane 7 on channel 0: 0.0
Upper bound for byte lane 7 on channel 0: 10.4
Final timings for byte lane 7 on channel 0: 5.2
Lower bound for group 0 on channel 0: 1.7.5
Upper bound for group 0 on channel 0: 2.2.2
Final timings for group 0 on channel 0: 1.10.7
Lower bound for group 1 on channel 0: 1.6.1
Upper bound for group 1 on channel 0: 2.0.2
Final timings for group 1 on channel 0: 1.9.1
Lower bound for group 2 on channel 0: 2.0.7
Upper bound for group 2 on channel 0: 2.8.1
Final timings for group 2 on channel 0: 2.4.4
Lower bound for group 3 on channel 0: 2.4.7
Upper bound for group 3 on channel 0: 3.0.0
Final timings for group 3 on channel 0: 2.8.3
[...]

Final timings are always the average of the two bounds. The last dots
separate eights (not decimals) and the middles are elenvenths or twelfths
depending on the clock speed (twelfths in this case).

Change-Id: Idb7c84b514716c7265b94890c39b7225de7800dc
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3257
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-22 18:07:22 +02:00
Nico Huber 12276acfd7 intel/gm45: Handle overflows during DDR3 write training
We halted the machine on any overflow during the write training.
However, overflows during the search for a good to bad edge are
non-fatal, and should be ignored.

Change-Id: I45ccbabc214e208974039246d806b0d2ca2fdc03
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3256
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-22 18:05:34 +02:00
Nico Huber 08bee23f7e intel/gm45: Refactor DDR3 write training
Split some code in individual functions. It's the refactoring part of
a bigger change, following...

Change-Id: Id19be4588ad8984935040d9bcba4d7c5f2e1114f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3255
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-22 18:04:11 +02:00
Nico Huber 35e45c0780 intel/gm45: Handle overflows during DDR3 read training
We halted the machine on any overflow during the read training. However,
overflows during the search for a good to bad edge are non-fatal, and
should be ignored.

Change-Id: I77085840ade25bce955480689c84603334113d1f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3254
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-22 18:02:24 +02:00
Nico Huber 26a6435123 intel/gm45: Refactor DDR3 read training
Split some code in individual functions. It's the refactoring part of
a bigger change, following...

Change-Id: Ied551a011eaf22f6f8f6db0044de3634134f0b37
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3253
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-22 18:00:56 +02:00
Nico Huber 0da92863a7 intel/gm45: Fix interpretation of VT-d disable bit
When configuring the GTT size for the integrated graphics, the state
of VT-d was read wrong. Bit 48 of CAPID0 (D0F0) is set when VT-d is
_disabled_.

In the log of a VT-d enabled roda/rk9 we have now:

[...]
VT-d enabled
[...]
IGD decoded, subtracting 32M UMA and 4M GTT
[...]

Without this patch, only 2M GTT were reported.

Change-Id: I87582c18f4769c2a05be86936d865c0d1fb35966
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3252
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-22 17:59:10 +02:00
Nico Huber 0f43af2ebb intel/i5000: Remove unused copy of udelay.c
It's a copy from i945 and looks like not beeing included in a
build at all.

If you should ever want to use that file for the Intel 5000,
please copy it from another chipset like the Intel 945 as it
is going to be improved.

Change-Id: I5c113bb0b2fed7b93feb3dcb1b5d962e1442963a
Reported-by: Ronald G. Minnich <rminnich@gmail.com>
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3219
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Sven Schnelle <svens@stackframe.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-21 17:46:02 +02:00
Stefan Reinauer c5e036a043 Get rid of a number of __GNUC__ checks
In the process of streamlining coreboot code and getting
rid of unneeded ifdefs, drop a number of unneeded checks
for the GNU C compiler. This also cleans up x86emu/types.h
significantly by dropping all the duplicate types in there.

Change-Id: I0bf289e149ed02e5170751c101adc335b849a410
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3226
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-05-10 17:31:31 +02:00
Paul Menzel bed88d65b2 northbridge/intel/i5000/udelay.c: Remove unused header `console.h`
Nothing from the header `console.h` is needed in `udelay.c`, so do
not include it.

This header was included since commit
»Add Intel i5000 Memory Controller Hub« (17670866) [1].

[1] http://review.coreboot.org/491

Change-Id: Ie136a1b862b55c9471f9293ed616ce27a1d01a50
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3218
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-10 00:36:22 +02:00
Stefan Reinauer 3f5f6d8368 Drop prototype guarding for romcc
Commit "romcc: Don't fail on function prototypes" (11a7db3b) [1]
made romcc not choke on function prototypes anymore. This
allows us to get rid of a lot of ifdefs guarding __ROMCC__ .

[1] http://review.coreboot.org/2424

Change-Id: Ib1be3b294e5b49f5101f2e02ee1473809109c8ac
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3216
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-10 00:06:46 +02:00
Stefan Reinauer 3949e37834 Drop CONFIG_AP_CODE_IN_CAR
This option has not been enabled on any board and was considered
obsolete last time it was touched. If we need the functionality,
let's fix this in a generic way instead of a K8 specific way.
This was mostly a speedup hack back in the day.

Change-Id: Ib1ca248c56a7f6e9d0c986c35d131d5f444de0d8
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3211
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-05-08 19:14:21 +02:00
Stefan Reinauer 2a3c10677f hardwaremain: drop boot_complete parameter
it has been unused since 9 years or so, hence drop it.

Change-Id: I0706feb7b3f2ada8ecb92176a94f6a8df53eaaa1
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3212
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-05-08 18:23:33 +02:00
Aaron Durbin 7cb1ba9a61 haswell: use tsc for udelay()
Instead of using the local apic timer for udelay() use the tsc.
That way SMM, romstage, and ramstage all use the same delay
functionality.

Change-Id: I024de5af01eb5de09318e13d0428ee98c132f594
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3169
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-07 18:32:41 +02:00
Aaron Durbin 243aa44b74 boot: remove cbmem_post_handling()
The cbmem_post_handling() function was implemented by 2
chipsets in order to save memory configuration in flash. Convert
both of these chipsets to use the boot state machine callbacks
to perform the saving of the memory configuration.

Change-Id: I697e5c946281b85a71d8533437802d7913135af3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3137
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-01 07:11:22 +02:00
Denis 'GNUtoo' Carikli 4b213a8d1f Intel i945: ACPI: Add _OSC method
Add the ACPI Operating System Capabilities Method and let the
operation system control everything.

Commit »AMD Fam14 DSDT: Add OSC method« (00a0e76b) [1] is used as
a template.

The Lenovo X60 [2] running the Parabola GNU/Linux distribution [3] is
used for testing.

Before that change:

    $ dmesg | egrep -e OSC -e ASPM
    [    0.108036] pci_root PNP0A08:00: ACPI _OSC support notification failed, disabling PCIe ASPM
    [    0.108040] pci_root PNP0A08:00: Unable to request _OSC control (_OSC support mask: 0x08)
    [    0.118089] ACPI _OSC control for PCIe not granted, disabling ASPM
    [   16.874569] e1000e 0000:01:00.0: Disabling ASPM L0s L1

With that change:

    $ dmesg | egrep -e OSC -e ASPM
    [    0.107962] pci_root PNP0A08:00: Requesting ACPI _OSC control (0x1d)
    [    0.108003] pci_root PNP0A08:00: ACPI _OSC control (0x1d) granted
    [    0.111052] pci 0000:01:00.0: disabling ASPM on pre-1.1 PCIe device.  You can enable it with 'pcie_aspm=force'
    [   17.537970] e1000e 0000:01:00.0: Disabling ASPM L0s L1

[1] http://review.coreboot.org/2738
[2] http://www.coreboot.org/Lenovo_x60x
[3] https://parabolagnulinux.org/

Change-Id: I1caffa44eea447d553c01caaf431f2db241ea5ea
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2938
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-18 02:48:02 +02:00
Denis 'GNUtoo' Carikli ed7e29e620 Lenovo ThinkPad X60: Add Native VGA init.
The code has been taken from the google link mainboard
  and modified to fit the ThinkPad X60.

Change-Id: Ie16e45163acdc651ea46699ecc33055bfd34099c
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/2998
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-16 05:20:12 +02:00
Nico Huber 8ecec215be Revert "siemens/sitemp_g1p1: Make ACPI report the right mmconf region"
This reverts commit 1fde22c54cacb15493bbde8835ec9e20f1d39bf5:

    commit 1fde22c54c
    Author: Patrick Georgi <patrick.georgi@secunet.com>
    Date:   Tue Apr 9 15:41:23 2013 +0200

        siemens/sitemp_g1p1: Make ACPI report the right mmconf region

        ACPI reported the entire space between top-of-memory and some
        (relatively) arbitrary limit as useful for MMIO. Unfortunately
        the HyperTransport configuration disagreed. Make them match up.

        Other boards are not affected since they don't report any region
        for that purpose at all (it seems).

        Change-Id: I432a679481fd1c271f14ecd6fe74f0b7a15a698e
        Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
        Reviewed-on: http://review.coreboot.org/3047
        Tested-by: build bot (Jenkins)
        Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

It sneaked in without it's dependencies and, therefore, broke the build for
all amdk8 targets. Paul Menzel already commented on the issue in [1]. It
also doesn't look like the dependencies would be pulled soon [2].

[1] http://review.coreboot.org/#/c/3047/
[2] http://review.coreboot.org/#/c/2662/

Change-Id: Ica89563aae4af3f0f35cacfe37fb608782329523
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3063
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-04-12 11:48:15 +02:00
Mike Loptien 573a1d6fa8 Persimmon/Fam14/SB800 DSDT: Split into common areas
Split the Persimmon DSDT into common code areas.
For example, split the Southbridge specific code into
the Southbridge directory and CPU specific code into
the CPU directory.  Also adding the superio.asl file
to the Persimmon DSDT tree. This file is empty for
the moment but will be necessary in the future.  I have
also emptied the thermal.asl file in the mainboard
directory because it does not seem to perform as
intended (fan control does not change when it is
brought back into the code base) and it has been
inside a '#if 0' statement for a long time.  Removing
it until it is decided that it is actually necessary.

This change was verified in three different ways:
	1. Visual comparison of the compiled DSDT pulled from the
	Persimmon after booting into Linux using the ACPI tools
	acpidump, acpixtract, and iasl.  The comparison was done
	between the DSDT before and after doing the split work.

	This test is somewhat difficult considering the expanse
	of the changes.  Blocks of code have been moved, and
	others changed.

	2. Linux logs were dumped before and after the DSDT split.
	Logs dumped and compared include dmesg and lspci -tv.
	Neither log changed significantly between the two compare
	points.

	3. The test suite FWTS was run on the Coreboot build both
	before and after doing the DSDT split with the command
	'sudo fwts -b -P -u'.  The flag -b specifies all batch jobs,
	-P specifies all power tests, and -u specifies utilities.
	Interactive jobs were not run as most of them consist of
	laptop checks.  Again, there were no significant changes
	between the two endpoints.

These tests lead me to believe that there was no change in
the functionality of the ACPI tables apart from what is
known and expected.

This patch is the first of a series of patches to split the DSDT.
The ASRock patch was merged before this one and breaks the ASROCK
E350M1 build (patch 8d80a3fb: http://review.coreboot.org/#/c/3050/).
Please be aware of this dependency when pulling these patches.
Other patches that depend on this patch are
'AMD Fam14: Split out the AMD Fam14 DSDT'
(http://review.coreboot.org/#/c/3051/)
and 'Fam14 DSDT: Also return for unrecognized UUID in _OSC'
(http://review.coreboot.org/#/c/3052/)

Change-Id: I53ff59909cceb30a08e8eab3d59b30b97c802726
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/3048
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-04-11 21:48:27 +02:00
Patrick Georgi 1fde22c54c siemens/sitemp_g1p1: Make ACPI report the right mmconf region
ACPI reported the entire space between top-of-memory and some
(relatively) arbitrary limit as useful for MMIO. Unfortunately
the HyperTransport configuration disagreed. Make them match up.

Other boards are not affected since they don't report any region
for that purpose at all (it seems).

Change-Id: I432a679481fd1c271f14ecd6fe74f0b7a15a698e
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/3047
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-10 17:40:49 +02:00
Paul Menzel 5b5cf3d610 AMD GX1: Remove useless copied header file `northbridge.h`
This was there since the beginning

    commit d24d6993b6
    Author: arch import user (historical) <svn@openbios.org>
    Date:   Wed Jul 6 17:06:46 2005 +0000

        Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-26
        Creator:  Hamish Guthrie <hamish@prodigi.ch>

        Added AMD GX1 northbridge and cs5530 Southbridge

but blindly copied from Intel 440 BX and is not used anywhere.

Thanks to Idwer Vollering for spotting this.

Change-Id: I38b3d3feb25966c3aa382994d323e59c3f3c9e6c
Reported-by: Idwer Vollering
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3020
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
2013-04-04 03:26:58 +02:00
Aaron Durbin c6f27226a8 sandybridge: enable ROM caching
If ROM caching is selected the sandybridge chipset code will
will enable ROM caching after all other CPU threads are brought
up.

Change-Id: I3a57ba8753678146527ebf9547f5fbbd4f441f43
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3017
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-03 19:26:25 +02:00
Aaron Durbin f567f16af4 sandybridge: add option to mark graphics memory write-combining.
The graphics memory can be accessed in a faster manner by
setting it to write-combing mode.  Add an option to enable
write-combining for the graphics memory.

Change-Id: I7d37fd78906262aabef92c2b4f4cab0e3f7e4f6d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2894
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-29 20:00:39 +01:00
Aaron Durbin fcfe67c3b2 haswell: add option to mark graphics memory write-combining.
The graphics memory can be accessed in a faster manner by
setting it to write-combing mode. Add an option to enable
write-combining for the graphics memory.

Change-Id: I797fcd9f0dfb074f9e45476773acbfe614eb4b0a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2893
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-29 20:00:25 +01:00
Aaron Durbin bb4e79a332 x86: add new mtrr implementation
The old MTRR code had issues using too many variable
MTRRs depending on the physical address space layout dictated
by the device resources. This new implementation calculates
the default MTRR type by comparing the number of variable MTRRs
used for each type. This avoids the need for IORESOURE_UMA_FB
because in many of those situations setting the default type to WB
frees up the variable MTTRs to set that space to UC.

Additionally, it removes the need for IORESOURCE_IGNORE_MTRR
becuase the new mtrr uses the memrange library which does merging
of resources.

Lastly, the sandybridge gma has its speedup optimization removed
for the graphics memory by writing a pre-determined MTRR index.
That will be fixed in an upcoming patch once write-combining support
is added to the resources.

Slight differences from previous MTRR code:
- The number of reserved OS MTRRs is not a hard limit. It's now advisory
  as PAT can be used by the OS to setup the regions to the caching
  policy desired.
- The memory types are calculated once by the first CPU to run the code.
  After that all other CPUs use that value.
- CONFIG_CACHE_ROM support was dropped. It will be added back in its own
  change.

A pathological case that was previously fixed by changing vendor code
to adjust the IO hole location looked like the following:

MTRR: Physical address space:
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
0x00000000000c0000 - 0x00000000ad800000 size 0xad740000 type 6
0x00000000ad800000 - 0x00000000d0000000 size 0x22800000 type 0
0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0
0x0000000100000000 - 0x000000014f600000 size 0x4f600000 type 6

As noted by the output below it's impossible to accomodate those
ranges even with 10 variable MTRRS. However, because the code
can select WB as the default MTRR type it can be done in 6 MTRRs:

MTRR: default type WB/UC MTRR counts: 6/14.
MTRR: WB selected as default type.
MTRR: 0 base 0x00000000ad800000 mask 0x0000007fff800000 type 0
MTRR: 1 base 0x00000000ae000000 mask 0x0000007ffe000000 type 0
MTRR: 2 base 0x00000000b0000000 mask 0x0000007ff0000000 type 0
MTRR: 3 base 0x00000000c0000000 mask 0x0000007ff0000000 type 0
MTRR: 4 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1
MTRR: 5 base 0x00000000e0000000 mask 0x0000007fe0000000 type 0

Change-Id: Idfcc78d9afef9d44c769a676716aae3ff2bd79de
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2889
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-29 19:53:43 +01:00
Aaron Durbin c965076c3e resources: introduce reserved_ram_resource()
mmio_resource() was previously being used for reserving
RAM from the OS by using IORESOURCE_IGNORE_MTRR atrribute.
Instead, be more explicit for those uses with
reserved_ram_resource(). bad_ram_resource() now calls
reserved_ram_resource(). Those resources are marked as cacheable
but reserved.

The sandybridge and haswell code were relying on the implementation
fo the MTRR algorithm's interaction for reserved regions. Instead
be explicit about what ranges are MMIO reserved and what are RAM
reserved.

Change-Id: I1e47026970fb37c0305e4d49a12c98b0cdd1abe5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2886
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-23 19:40:36 +01:00
Aaron Durbin c0cbd6e8c2 haswell: use dynamic cbmem
Convert the existing haswell code to support reloctable ramstage
to use dynamic cbmem. This patch always selects DYNAMIC_CBMEM as
this option is a hard requirement for relocatable ramstage.

Aside from converting a few new API calls, a cbmem_top()
implementation is added which is defined to be at the begining of the
TSEG region. Also, use the dynamic cbmem library for allocating a
stack in ram for romstage after CAR is torn down.

Utilizing dynamic cbmem does mean that the cmem field in the gnvs
chromeos acpi table is now 0. Also, the memconsole driver in the kernel
won't be able to find the memconsole because the cbmem structure
changed.

Change-Id: I7cf98d15b97ad82abacfb36ec37b004ce4605c38
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2850
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-22 00:13:56 +01:00
Aaron Durbin dd4a6d2357 coreboot: dynamic cbmem requirement
Dynamic cbmem is now a requirement for relocatable ramstage.
This patch replaces the reserve_* fields in the romstage_handoff
structure by using the dynamic cbmem library.

The haswell code is not moved over in this commit, but it should be
safe because there is a hard requirement for DYNAMIC_CBMEM when using
a reloctable ramstage.

Change-Id: I59ab4552c3ae8c2c3982df458cd81a4a9b712cc2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2849
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-22 00:13:42 +01:00
Stefan Reinauer 24d1d4b472 x86: Unify arch/io.h and arch/romcc_io.h
Here's the great news: From now on you don't have to worry about
hitting the right io.h include anymore. Just forget about romcc_io.h
and use io.h instead. This cleanup has a number of advantages, like
you don't have to guard device/ includes for SMM and pre RAM
anymore. This allows to get rid of a number of ifdefs and will
generally make the code more readable and understandable.

Potentially in the future some of the code in the io.h __PRE_RAM__
path should move to device.h or other device/ includes instead,
but that's another incremental change.

Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2872
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-22 00:00:09 +01:00
Duncan Laurie 467f31de92 haswell/lynxpoint: Use new PCH/PM helper functions
This makes use of the new functions from pmutil.c that take
care of the differences between -H and -LP chipsets.

It also adds support for the LynxPoint-LP GPE0 register block
and the SMI/SCI routing differences.

The FADT is updated to report the new 256 byte GPE0 block on
wtm2/wtm2 boards which is too big for the 64bit X_GPE0 address
block so that part is zeroed to prevent IASL and the kernel
from complaining about a mismatch.

This was tested on WTM2.  Unfortunately I am still unable to get an
SCI delivered from the EC but I suspect that is due to a magic
command needed to put the EC in ACPI mode.  Instead I verified that
all of the power management and GPIO registers were set to expected
values.

I also tested transitions into S3 and S5 from both the kernel and
by pressing the power button at the developer mode screen and they
all function as expected.

Change-Id: Ice9e798ea5144db228349ce90540745c0780b20a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2816
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21 23:11:25 +01:00
Duncan Laurie 969ac8db18 haswell: Drop the device ID check in graphics init path
Change-Id: I10c4264d317b5fac02a44f50ed10b457e1865e17
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2809
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21 23:04:07 +01:00
Aaron Durbin 8ce667e506 haswell: add multipurpose SMM memory region
The SMM region is available for multipurpose use before the SMM
handler is relocated. Provide a configurable sized region in the
TSEG for use before the SMM handler is relocated. This feature is
implemented by making the reserved size a Kconfig option. Also
make the IED region a Kconfig option as well. Lastly add some sanity
checking on the Kconfig options.

Change-Id: Idd7fccf925a8787146906ac766b7878845c75935
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2804
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21 22:59:03 +01:00
Aaron Durbin bf396ff21c haswell: use s3_resume field in romstage_handoff
Now that there is a way to disseminate the presence of s3 wake more
formally use that instead of hard coded pointers in memory and stashing
magic values in device registers. The northbridge code picks up the
field's presence in the romstage_handoff structure and sets up the
acpi_slp_type variable accordingly.

Change-Id: Ida786728ce2950bd64610a99b7ad4f1ca6917a99
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2799
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21 22:53:25 +01:00
Aaron Durbin 605ca1bb9c haswell: cbmem_get_table_location() implementation
Provide the implemenation of cbmem_get_table_location() so that
cbmem can be initialized early in ramstage when CONFIG_EARLY_CBMEM_INIT
is enabled. The cbmem tables are located just below the TSEG region.

Change-Id: Ia160ac6aff583fc52bf403d047529aaa07088085
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2798
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21 22:51:58 +01:00
Duncan Laurie 0013a69e70 haswell: drop memory reservation for sandybridge GPU bug
This is not needed in haswell.

Change-Id: I23817c2e01be33855f9d5a5e389e8ccb7954c0e2
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2847
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-20 04:17:35 +01:00
Kimarie Hoot fa91819e89 AMD Fam15: Add SPD read functions to wrapper code
Change:
This is the initial step for moving the AMD F15 & HUDSON1,2,3
SPD-read callout out of the mainboard directories and into
the wrapper.  The next step is to update the platforms to use
this routine in BiosCallouts.c and to delete the code from the
mainboard directories.  The DIMM addresses should be moved into
devicetree.cb.
If there are significant differences or reasons that the mainboard
needs to override this code, it's perfectly reasonable to keep using
the version in the mainboard, but this allows us to remove duplicated
code and simplify the mainboard directories.

Notes:
This started by duplicating what was in Dinar, and was changed to
use the devicetree.cb structures.  Significant cleanup and magic
number reduction was done as well.

It is intended that this file will not be included in ramstage as
the DIMM init is all done in romstage.

This is similar to what was done for Parmer/Thatcher in commit
7fb692bd - http://review.coreboot.org/#/c/2190/
Fam15tn: Move SPD read from mainboards into wrapper

Yes, it would make sense to split this into two separate files
and move the SMBus initialization and access into the southbridge
wrapper.  Maybe that can come next.

Change-Id: I4e00ada288e1486cf30684403505e475f9093ec2
Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com>
Reviewed-on: http://review.coreboot.org/2777
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-19 17:08:10 +01:00
Aaron Durbin 2ad1dbaf2a haswell: move call site of save_mrc_data()
The save_mrc_data() was previously called conditionally
in the raminit code. The save_mrc_data() function was called
in the non-S3 wake paths. However, the common romstage_common()
code was checking cbmem initialization things on s3 wake. Between
the two callers cbmem_initialize() was being called twice in the
non-s3 wake paths.  Moreover, saving of the mrc data was not allowed
when CONFIG_EARLY_CBMEM_INIT wasn't enabled.

Therefore, move the save_mrc_data() to romstage_common. It already has
the knowledge of the wake path. Also remove the CONFIG_EARLY_CBMEM_INIT
requirement from save_mrc_data() as well as the call to cbmem_initialize().

Change-Id: I7f0e4d752c92d9d5eedb8fa56133ec190caf77da
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2756
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-18 20:50:15 +01:00
Aaron Durbin 9b7f9b9768 haswell: remove unused sys_info structure
This structure is not used nor the variable being instantiated on the
stack. Remove them.

Change-Id: If3abe2dd77104eff49665dd33570b07179bf34f5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2753
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-18 20:48:17 +01:00
Aaron Durbin 3d0071bde3 haswell: adjust CAR usage
It was found that the Haswell reference code was smashing through the
stack into the reference code's heap implementation. The reason for this
is because our current CAR allocation is too small. Moreover there are
quite a few things to coordinate between 2 code bases to get correct.
This commit separates the CAR into 2 parts:
  1. MRC CAR usage.
  2. Coreboot CAR usage.
Pointers from one region can be passed between the 2 modules, but one
should not be able to affect the others as checking has been put into
place in both modules.

The CAR size has effectively been doubled from 0x20000 (128 KiB) to
0x40000 (256KiB). Not all of that increase was needed, but enforcing
a power of 2 size only utilizes 1 MTRR.

Old CAR layout with a single contiguous stack with the region starting
at CONFIG_DCACHE_RAM_BASE:

+---------------------------------------+ Offset CONFIG_DCACHE_RAM_SIZE
|  MRC global variables                 |
|  CONFIG_DCACHE_RAM_MRC_VAR_SIZE bytes |
+---------------------------------------+
|  ROM stage stack                      |
|                                       |
|                                       |
+---------------------------------------+
|  MRC Heap 30000 bytes                 |
+---------------------------------------+
|  ROM stage console                    |
|  CONFIG_CONSOLE_CAR_BUFFER_SIZE bytes |
+---------------------------------------+
|  ROM stage CAR_GLOBAL variables       |
+---------------------------------------+ Offset 0

There was some hard coded offsets in the reference code wrapper to start
the heap past the console buffer. Even with this commit the console
can smash into the following region depending on what size
CONFIG_CONSOLE_CAR_BUFFER_SIZE is.

As noted above This change splits the CAR region into 2 parts starting
at CONFIG_DCACHE_RAM_BASE:

+---------------------------------------+
|  MRC Region                           |
|  CONFIG_DCACHE_RAM_MRC_VAR_SIZE bytes |
+---------------------------------------+ Offset CONFIG_DCACHE_RAM_SIZE
|  ROM stage stack                      |
|                                       |
|                                       |
+---------------------------------------+
|  ROM stage console                    |
|  CONFIG_CONSOLE_CAR_BUFFER_SIZE bytes |
+---------------------------------------+
|  ROM stage CAR_GLOBAL variables       |
+---------------------------------------+ Offset 0

Another variable was add, CONFIG_DCACHE_RAM_ROMSTAGE_STACK_SIZE,
which represents the expected stack usage for the romstage. A marker
is checked at the base of the stack to determine if either the stack
was smashed or the console encroached on the stack.

Change-Id: Id76f2fe4a5cf1c776c8f0019f406593f68e443a7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2752
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-18 20:47:50 +01:00
Aaron Durbin 21efd8c037 haswell: fix ACPI MCFG table
The acpi_fill_mcfg() was still using ivy/sandy PCI device ids which Hawell
obviously doesn't have. This resulted in an empty MCFG table. Instead of
relying on PCI device ids use dev/fn 0/0 since that is where the host
bridge always resides. Additionally remove the defines for the IB and SB
pci device ids. Replace them with mobile and ult Haswel device ids and
use those in the pci driver tables for the northbridge code.

Booted to Linux and noted that MCFG was properly parsed.

Change-Id: Ieaab2dfef0e9daf3edbd8a27efe0825d2beb9443
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2748
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-18 17:11:24 +01:00
Aaron Durbin 7af20698f6 haswell: enable caching before SMM initialization
The SMM handler resides in the TSEG region which is far above
CONFIG_RAM_TOP (which is the highest cacheable address) before
MTRRs are setup. This means that calling initialize_cpus() before
performing MTRR setup on the BSP means the SMM handler is copied
using uncacheable accesses.

Improve the SMM handler setup path by enabling performing MTRR setup on
for the BSP before the call to initialize_cpus(). In order to do this
the haswell_init() function was split into 2 paths: BSP & AP paths.
There is a cpu_common_init() that both call to perform similar
functionality. The BSP path in haswell_init() then starts the APs using
intel_cores_init(). The AP path in haswell_init() loads microcode and
sets up MTRRs.

This split will be leveraged for future support of bringing up APs in
parallel as well as adhering to the Haswell MP initialization
requirements.

Change-Id: Id8e17af149e68d708f3d4765e38b1c61f7ebb470
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2746
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-18 17:10:18 +01:00
Aaron Durbin 239c2e843f haswell platforms: restructure romstage main
There was a mix of setup code sprinkled across the various components:
southbridge code in the northbridge, etc. This commit reorganizes the
code so that northbridge code doesn't initialize southbridge components.
Additionally, the calling dram initialization no longer calls out to ME
code. The main() function in the mainboard calls the necessary ME
functions before and after dram initialization.

The biggest change is the addition of an early_pch_init() function
which initializes the BARs, GPIOs, and RCBA configuration. It is also
responsible for reporting back to the caller if the board is being
woken up from S3. The one sequence difference is that the RCBA config
is performed before claling the reference code.

Lastly the rcba configuration was changed to be table driven so that
different board/configurations can use the same code. It should be
possible to have board/configuration specific gpio and rcba
configuration while reusing the romstage code.

Change-Id: I830e41b426261dd686a2701ce054fc39f296dffa
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2681
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-17 22:53:31 +01:00
Aaron Durbin e6c3b1d30d haswell: include TSEG region in cacheable memory
The SMRR takes precedence over the MTRR entries. Therefore, if the TSEG
region is setup as cacheable through the MTTRs, accesses to the TSEG
region before SMM relocation are cached. This allows for the setup of
SMM relocation to be faster by caching accesses to the future TSEG
(SMRAM) memory.

MC MAP: TOM: 0x140000000
MC MAP: TOUUD: 0x18f600000
MC MAP: MESEG_BASE: 0x13f000000
MC MAP: MESEG_LIMIT: 0x7fff0fffff
MC MAP: REMAP_BASE: 0x13f000000
MC MAP: REMAP_LIMIT: 0x18f5fffff
MC MAP: TOLUD: 0xafa00000
MC MAP: BGSM: 0xad800000
MC MAP: BDSM: 0xada00000
MC MAP: TESGMB: 0xad000000
MC MAP: GGC: 0x209

TSEG->BGSM:
   PCI: 00:00.0 resource base ad000000 size 800000 align 0 gran 0 limit 0 flags f0004200 index 4
BGSM->TOLUD:
   PCI: 00:00.0 resource base ad800000 size 2200000 align 0 gran 0 limit 0 flags f0000200 index 5

Setting variable MTRR 0, base:    0MB, range: 2048MB, type WB
Setting variable MTRR 1, base: 2048MB, range:  512MB, type WB
Setting variable MTRR 2, base: 2560MB, range:  256MB, type WB
Adding hole at 2776MB-2816MB
Setting variable MTRR 3, base: 2776MB, range:    8MB, type UC
Setting variable MTRR 4, base: 2784MB, range:   32MB, type UC
Zero-sized MTRR range @0KB
 Allocate an msr - basek = 00400000, sizek = 0023d800,
Setting variable MTRR 5, base: 4096MB, range: 2048MB, type WB
Setting variable MTRR 6, base: 6144MB, range:  256MB, type WB
Adding hole at 6390MB-6400MB
Setting variable MTRR 7, base: 6390MB, range:    2MB, type UC

MTRR translation from MB to addresses:

MTRR 0: 0x00000000 -> 0x80000000 WB
MTRR 1: 0x80000000 -> 0xa0000000 WB
MTRR 2: 0xa0000000 -> 0xb0000000 WB
MTRR 3: 0xad800000 -> 0xae000000 UC
MTRR 4: 0xae000000 -> 0xb0000000 UC

I'm not a fan of the marking physical address space with MTRRs as being
UC which is PCI space, but it is technically correct.

Lastly, drop a comment describing AP startup flow through coreboot.

Change-Id: Ic63c0377b9c20102fcd3f190052fb32bc5f89182
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2690
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-17 20:05:15 +01:00
Patrick Georgi 86a1110837 i945: Replace some two magic values by defined names
Devoutly to be wish'd. To die,—to sleep;—
To sleep! perchance to dream:—ay, there's the rub;
For in that sleep of death what dreams may come,

(Since who could argue with William Shakespeare?)

Change-Id: I4e4c617dcd3ede81a0abbe16f9916562d24fa8ce
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/2733
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2013-03-17 19:59:20 +01:00
Aaron Durbin 5c66f08a3a haswell: don't add a 0-sized memory range resource
It's possible that TOUUD can be 4GiB in a small physical memory
configuration. Therefore, don't add a 0-size memory range resouce
in that case.

Change-Id: I016616a9d9d615417038e9c847c354db7d872819
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2691
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-16 04:58:18 +01:00
Ronald G. Minnich 69efaa0388 Google Link: Add remaining code to support native graphics
The Link native graphics commit 49428d84 [1]

    Add support for Google's Chromebook Pixel

was missing some of the higher level bits, and hence could not be
used.  This is not new code -- it has been working since last
August -- so the effort now is to get it into the tree and structure
it in a way compatible with upstream coreboot.

1. Add options to src/device/Kconfig to enable native graphics.
2. Export the MTRR function for setting variable MTRRs.
3. Clean up some of the comments and white space.

While I realize that the product name is Pixel, the mainboard in the
coreboot tree is called Link, and that name is what we will use
in our commits.

[1] http://review.coreboot.org/2482

Change-Id: Ie4db21f245cf5062fe3a8ee913d05dd79030e3e8
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2531
Tested-by: build bot (Jenkins)
2013-03-15 20:21:51 +01:00
Aaron Durbin 1570260ba1 haswell: Fix BDSM and BGSM indicies in memory map
This wasn't previously spotted because the printk's were correct.
However if one needed to get the value of the BDSM or BGSM register
the value would reflect the other register's value.

Change-Id: Ieec7360a74a65292773b61e14da39fc7d8bfad46
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2689
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-15 16:58:54 +01:00
Aaron Durbin 1fef1f5177 haswell: reserve default SMRAM space
Currently the OS is free to use the memory located at the default
SMRAM space because it is not marked reserved in the e820. This can
lead to memory corruption on S3 resume because SMM setup doesn't save
this range before using it to relocate SMRAM.

Resulting tables:

	coreboot memory table:
	 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
	 1. 0000000000001000-000000000002ffff: RAM
	 2. 0000000000030000-000000000003ffff: RESERVED
	 3. 0000000000040000-000000000009ffff: RAM
	 4. 00000000000a0000-00000000000fffff: RESERVED
	 5. 0000000000100000-0000000000efffff: RAM
	 6. 0000000000f00000-0000000000ffffff: RESERVED
	 7. 0000000001000000-00000000acebffff: RAM
	 8. 00000000acec0000-00000000acffffff: CONFIGURATION TABLES
	 9. 00000000ad000000-00000000af9fffff: RESERVED
	10. 00000000f0000000-00000000f3ffffff: RESERVED
	11. 00000000fed10000-00000000fed19fff: RESERVED
	12. 00000000fed84000-00000000fed84fff: RESERVED
	13. 0000000100000000-000000018f5fffff: RAM

	e820 map has 13 items:
	  0: 0000000000000000 - 0000000000030000 = 1 RAM
	  1: 0000000000030000 - 0000000000040000 = 2 RESERVED
	  2: 0000000000040000 - 000000000009f400 = 1 RAM
	  3: 000000000009f400 - 00000000000a0000 = 2 RESERVED
	  4: 00000000000f0000 - 0000000000100000 = 2 RESERVED
	  5: 0000000000100000 - 0000000000f00000 = 1 RAM
	  6: 0000000000f00000 - 0000000001000000 = 2 RESERVED
	  7: 0000000001000000 - 00000000acec0000 = 1 RAM
	  8: 00000000acec0000 - 00000000afa00000 = 2 RESERVED
	  9: 00000000f0000000 - 00000000f4000000 = 2 RESERVED
	  10: 00000000fed10000 - 00000000fed1a000 = 2 RESERVED
	  11: 00000000fed84000 - 00000000fed85000 = 2 RESERVED
	  12: 0000000100000000 - 000000018f600000 = 1 RAM

Booted and checked e820 as well as coreboot table information.

Change-Id: Ie4985c748b591bf8c0d6a2b59549b698c9ad6cfe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2688
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-15 16:58:37 +01:00
Aaron Durbin c12ef9723e haswell: resource allocation
The previous code w.r.t. resource allocation was getting lucky
based on the way fixed mmio resources on the system were being
chosen. Namely, PCIEXBAR was the lowest mmio space and the other
fixed non-standar BARs were above it. The resource allocator would
then start allocating standard BARs below that.

On top of that other resources were being added when
dev_ops->set_resources() was being called on the PCI domain. At that
point the PCI range limit were already picked for where to start
allocating from.

To ensure we no longer get lucky during resource allocation add the
fixed resources in the host bridge and add the memory controller
cacheable memory areas. With those resources added the range limit
for standard PCI BARs is chosen properly.

Depending on haswell board configurations we may need to adjust and
pass in the size of physical address space needed for PCI resources
to the reference code. For the time being the CRBs appear to be OK.

Lastly, remove the SNB workaround for reserving 2MiB at 1GiB and 512MiB.

Output from 6GiB memory configuration:
	MC MAP: TOM: 0x140000000
	MC MAP: TOUUD: 0x18f600000
	MC MAP: MESEG_BASE: 0x13f000000
	MC MAP: MESEG_LIMIT: 0x7fff0fffff
	MC MAP: REMAP_BASE: 0x13f000000
	MC MAP: REMAP_LIMIT: 0x18f5fffff
	MC MAP: TOLUD: 0xafa00000
	MC MAP: BDSM: 0xada00000
	MC MAP: BGSM: 0xad800000
	MC MAP: TESGMB: 0xad000000
	MC MAP: GGC: 0x209

	coreboot memory table:
	 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
	 1. 0000000000001000-000000000009ffff: RAM
	 2. 00000000000a0000-00000000000fffff: RESERVED
	 3. 0000000000100000-0000000000efffff: RAM
	 4. 0000000000f00000-0000000000ffffff: RESERVED
	 5. 0000000001000000-00000000acebffff: RAM
	 6. 00000000acec0000-00000000acffffff: CONFIGURATION TABLES
	 7. 00000000ad000000-00000000af9fffff: RESERVED
	 8. 00000000f0000000-00000000f3ffffff: RESERVED
	 9. 00000000fed10000-00000000fed17fff: RESERVED
	10. 00000000fed18000-00000000fed18fff: RESERVED
	11. 00000000fed19000-00000000fed19fff: RESERVED
	12. 00000000fed84000-00000000fed84fff: RESERVED
	13. 0000000100000000-000000018f5fffff: RAM

	e820 map has 11 items:
	  0: 0000000000000000 - 000000000009fc00 = 1 RAM
	  1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
	  2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
	  3: 0000000000100000 - 0000000000f00000 = 1 RAM
	  4: 0000000000f00000 - 0000000001000000 = 2 RESERVED
	  5: 0000000001000000 - 00000000acec0000 = 1 RAM
	  6: 00000000acec0000 - 00000000afa00000 = 2 RESERVED
	  7: 00000000f0000000 - 00000000f4000000 = 2 RESERVED
	  8: 00000000fed10000 - 00000000fed1a000 = 2 RESERVED
	  9: 00000000fed84000 - 00000000fed85000 = 2 RESERVED
	  10: 0000000100000000 - 000000018f600000 = 1 RAM

Output from 4GiB memory configuration:
	MC MAP: TOM: 0x100000000
	MC MAP: TOUUD: 0x14f600000
	MC MAP: MESEG_BASE: 0xff000000
	MC MAP: MESEG_LIMIT: 0x7fff0fffff
	MC MAP: REMAP_BASE: 0x100000000
	MC MAP: REMAP_LIMIT: 0x14f5fffff
	MC MAP: TOLUD: 0xafa00000
	MC MAP: BDSM: 0xada00000
	MC MAP: BGSM: 0xad800000
	MC MAP: TESGMB: 0xad000000
	MC MAP: GGC: 0x209

	coreboot memory table:
	 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
	 1. 0000000000001000-000000000009ffff: RAM
	 2. 00000000000a0000-00000000000fffff: RESERVED
	 3. 0000000000100000-0000000000efffff: RAM
	 4. 0000000000f00000-0000000000ffffff: RESERVED
	 5. 0000000001000000-00000000acebffff: RAM
	 6. 00000000acec0000-00000000acffffff: CONFIGURATION TABLES
	 7. 00000000ad000000-00000000af9fffff: RESERVED
	 8. 00000000f0000000-00000000f3ffffff: RESERVED
	 9. 00000000fed10000-00000000fed17fff: RESERVED
	10. 00000000fed18000-00000000fed18fff: RESERVED
	11. 00000000fed19000-00000000fed19fff: RESERVED
	12. 00000000fed84000-00000000fed84fff: RESERVED
	13. 0000000100000000-000000014f5fffff: RAM

	e820 map has 11 items:
	  0: 0000000000000000 - 000000000009fc00 = 1 RAM
	  1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
	  2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
	  3: 0000000000100000 - 0000000000f00000 = 1 RAM
	  4: 0000000000f00000 - 0000000001000000 = 2 RESERVED
	  5: 0000000001000000 - 00000000acec0000 = 1 RAM
	  6: 00000000acec0000 - 00000000afa00000 = 2 RESERVED
	  7: 00000000f0000000 - 00000000f4000000 = 2 RESERVED
	  8: 00000000fed10000 - 00000000fed1a000 = 2 RESERVED
	  9: 00000000fed84000 - 00000000fed85000 = 2 RESERVED
	  10: 0000000100000000 - 000000014f600000 = 1 RAM

Output from 2GiB memory configuration:
	MC MAP: TOM: 0x40000000
	MC MAP: TOUUD: 0x100600000
	MC MAP: MESEG_BASE: 0x3f000000
	MC MAP: MESEG_LIMIT: 0x7fff0fffff
	MC MAP: REMAP_BASE: 0x100000000
	MC MAP: REMAP_LIMIT: 0x1005fffff
	MC MAP: TOLUD: 0x3ea00000
	MC MAP: BDSM: 0x3ca00000
	MC MAP: BGSM: 0x3c800000
	MC MAP: TESGMB: 0x3c000000
	MC MAP: GGC: 0x209

	coreboot memory table:
	 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
	 1. 0000000000001000-000000000009ffff: RAM
	 2. 00000000000a0000-00000000000fffff: RESERVED
	 3. 0000000000100000-0000000000efffff: RAM
	 4. 0000000000f00000-0000000000ffffff: RESERVED
	 5. 0000000001000000-000000003bebffff: RAM
	 6. 000000003bec0000-000000003bffffff: CONFIGURATION TABLES
	 7. 000000003c000000-000000003e9fffff: RESERVED
	 8. 00000000f0000000-00000000f3ffffff: RESERVED
	 9. 00000000fed10000-00000000fed17fff: RESERVED
	10. 00000000fed18000-00000000fed18fff: RESERVED
	11. 00000000fed19000-00000000fed19fff: RESERVED
	12. 00000000fed84000-00000000fed84fff: RESERVED
	13. 0000000100000000-00000001005fffff: RAM

	e820 map has 11 items:
	  0: 0000000000000000 - 000000000009fc00 = 1 RAM
	  1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
	  2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
	  3: 0000000000100000 - 0000000000f00000 = 1 RAM
	  4: 0000000000f00000 - 0000000001000000 = 2 RESERVED
	  5: 0000000001000000 - 000000003bec0000 = 1 RAM
	  6: 000000003bec0000 - 000000003ea00000 = 2 RESERVED
	  7: 00000000f0000000 - 00000000f4000000 = 2 RESERVED
	  8: 00000000fed10000 - 00000000fed1a000 = 2 RESERVED
	  9: 00000000fed84000 - 00000000fed85000 = 2 RESERVED
	  10: 0000000100000000 - 0000000100600000 = 1 RAM

Verified through debug messages that range limits as well as
resources were being properly honored.

Change-Id: I2faa7d8a2a34a6a411a2885afb3b5c3fa1ad9c23
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2687
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-03-15 15:24:31 +01:00
Duncan Laurie 26e7dd703d haswell: more ULT/LP support and minor tweaks
- Add ME device ID for Lynxpoint LP
- Add GPU device IDs for ULT
- SATA init tweaks from checking against DXE reference code
- Remove the ICH7 from the SPI driver so it works on all lynxpoint
without having to add more LPC device ID checks
- Add function disable for audio dsp and xhci, remove PCI bridge
- Add interrupt route registers for new devices (needs romstage setup)

Change-Id: Idb48f50d0bacb6bf90531c3834542b9abb54fb8a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2680
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14 20:16:26 +01:00
Aaron Durbin 7116129899 haswell: Add VGA PCI ID mappings
Needed to map VGA OPROM IDs to actual device IDs

Change-Id: I6743905c3db52519bf18f4bcc1a972aec43d3e9d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2674
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-14 18:28:08 +01:00
Duncan Laurie df7be71374 haswell: Add ULT device IDs
Device IDs for northbridge and GPU.

Also mask off the lock bit in the memory map registers.

Change-Id: I9a4955d4541b938285712e82dd0b1696fa272b63
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2646
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-14 18:24:20 +01:00
Aaron Durbin f72ad02158 graysreef: update platform information
Some of the Lynx Point ids were off. Correct those and make
the pei data BAR fields consistent with the others.

Change-Id: I4102439588362cdb94643bd1ce69c9fa4278329e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2622
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14 18:23:05 +01:00
Aaron Durbin 89f79a019f haswell: remove explicit pcie config accesses
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove
the pcie explicit accesses. The default config accesses use
MMIO.

Change-Id: I8406cec16c1ee1bc205b657a0c90beb2252df061
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2618
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14 06:35:48 +01:00
Aaron Durbin c1989c494e haswell: add PCI id support
In order for coreboot to assign resources properly the pci
drivers need to have th proper device ids. Add the host controller
and the LPC device ids for Lynx Point.

Resource assignment works correctly now w/o odd behavior because
of conflicts.

Change-Id: Id33b3676616fb0c428d84e5fe5c6b8a7cc5fbb62
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2638
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-03-14 05:10:13 +01:00
Aaron Durbin b6b5aa15ce haswell: Remove logic to send dram init done to ME
The reference code sends the dram init done command to the ME.
Therefore, there is no need for coreboot to do this.

Change-Id: I6837d6c50bbb7db991f9d21fc9cdba76252c1b7b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2633
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14 05:10:00 +01:00
Aaron Durbin 30c3900451 haswell: notes and updates.
Add a FIXME about checking a MCHBAR register that isn't setup yet.
Also, remove revision updating because I can't find anything in the
docs that suggest this is required for haswell.

Change-Id: Ia8a6e08f82e18789e31c6c2ec2c1d63740c18dc4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2631
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14 05:08:02 +01:00
Aaron Durbin 8256a9b715 haswell: align pei_data structure with intel-framework
The intel-framework code has an updated pei_data structure.
Use the new structure and revision. Also, remove the scrambler
seed saving in CMOS since that appears to be handled in the saved
data from the reference code.

Change-Id: Ie09a0a00646ab040e8ceff922048981d055d5cd2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2630
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14 05:07:43 +01:00
Aaron Durbin b9adf7ba4b haswell: use #defines for constants in udelay.c
Change the hard coded values in udelay.c to use the #defines
for MSRs and BCLK.

Change-Id: I2bbeb0b478d2e3ca155e8f82006df86c29a4f018
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2629
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14 05:07:21 +01:00
Duncan Laurie ce36b12c27 haswell: Add LPT LP device IDs to platform report
Boot haswell ULT and see LPT reported properly.

Change-Id: I48344a8dde6adbbf331c91231342de45b1b6c32a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2697
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14 05:03:51 +01:00
Duncan Laurie 67113e95cf haswell: Update GPU power management setup
This is the steps outlined in the BWG.

It seems this is a lot simpler now (so far) which is good.

To test, boot to chromeos with 3.7 kernel + i915.preliminary_hw_support=1 and
see that the i915 driver complains a lot less than before and that a
splashscreen is displayed.

Change-Id: I722c90ecd351860949cedab24533f6c10e5b90e5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2696
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14 05:03:29 +01:00
Aaron Durbin 6d04f0f89e haswell: always use MMIO PCI config accesses
Add a bootblock.c file for the northbridge and setup the
PCIEXBAR as the first thing using IO PCI config acceses.
After that all PCI config accesses can use MMIO.

Change-Id: I51d229c626c45705dda1757c2f14265cbc0e6183
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2617
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14 01:45:50 +01:00
Aaron Durbin 76c3700f02 haswell: Add initial support for Haswell platforms
The Haswell parts use a PCH code named Lynx Point (Series 8). Therefore,
the southbridge support is included as well. The basis for this code is
the Sandybridge code. Management Engine, IRQ routing, and ACPI still requires
more attention, but this is a good starting point.

This code partially gets up through the romstage just before training
memory on a Haswell reference board.

Change-Id: If572d6c21ca051b486b82a924ca0ffe05c4d0ad4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2616
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14 01:44:40 +01:00
Marc Jones e7ae96f488 Add Intel Panther Point USB3 initialization
Add PEI updates and ACPI updates for supporting EHCI to XHCI
USB port support.

Change-Id: I9ace68a1b3950771aefb96c1319b8899291edd9a
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/2519
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-03-09 00:09:37 +01:00
Martin Roth 3b2653b1fc AMD Fam14: Add SPD read functions to wrapper code
Change:
This is the initial step for moving the AMD F14 & HUDSON1,2,3
SPD-read callout out of the mainboard directories and into
the wrapper.  The next step is to update the platforms to use
this routine in BiosCallouts.c and to delete the code from the
mainboard directories.  The DIMM addresses should be moved into
devicetree.cb.
If there are significant differences or reasons that the mainboard
needs to override this code, it's perfectly reasonable to keep using
the version in the mainboard, but this allows us to remove duplicated
code and simplify the mainboard directories.

Notes:
This started by duplicating what was in Persimmon, and was changed to
use the devicetree.cb structures.  The ASF setup was also removed from
the persimmon copy (PMIO writes to 0x28 & 0x29) as that's not needed
for the SPD access and doesn't make sense to initialize here.
Significant cleanup and magic number reduction was done as well.

It is intended that this file will not be included in ramstage as
the DIMM init is all done in romstage.

This is similar to what was done for Parmer/Thatcher in commit
7fb692bd - http://review.coreboot.org/#/c/2190/
Fam15tn: Move SPD read from mainboards into wrapper

Yes, it would make sense to split this into two separate files
and move the SMBUS initialization and access into the southbridge
wrapper.  Maybe that can come next.

Change-Id: I1e106d3912c160b0015bf02158d9faba4f578ee3
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2497
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-07 18:29:23 +01:00
Kyösti Mälkki 41dd3dbd5e Intel e7505: provide get_top_of_ram
This is required to enable EARLY_CBMEM_INIT.

Change-Id: I6d8caf382aa48eded81c1e94bbbcd3975ea88a1a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/2550
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-03-07 00:48:02 +01:00
Paul Menzel a46a712610 GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«
In the file `COPYING` in the coreboot repository and upstream [1]
just one space is used.

The following command was used to convert all files.

    $ git grep -l 'MA  02' | xargs sed -i 's/MA  02/MA 02/'

[1] http://www.gnu.org/licenses/gpl-2.0.txt

Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2490
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-03-01 10:16:08 +01:00
Stefan Reinauer fd611f9c2c Drop CONFIG_WRITE_HIGH_TABLES
It's been on for all boards per default since several years now
and the old code path probably doesn't even work anymore. Let's
just have one consistent way of doing things.

Change-Id: I58da7fe9b89a648d9a7165d37e0e35c88c06ac7e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2547
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-28 00:00:30 +01:00
Paul Menzel a8ae1c66f9 Whitespace: Replace tab character in license text with two spaces
For whatever reason tabs got inserted in the license header text.
Remove one occurrence of that with the following command [1].

    $ git grep -l 'MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.'$'\t' | xargs sed -i 's,MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.[        ]*,MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\ \ ,'

[1] http://sed.sourceforge.net/grabbag/tutorials/sedfaq.txt

Change-Id: Iaf4ed32c32600c3b23c08f8754815b959b304882
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2460
Tested-by: build bot (Jenkins)
Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
2013-02-20 23:30:45 +01:00
Martin Roth 92f03c0a06 AMD Family12h: Fix warnings
Add needed prototypes to .h files.
Remove unused variables and fix types in printk statements.
Add #IFNDEFs around #DEFINEs to keep them from being defined twice.
Fix a whole bunch of casts.
Fix undefined pre-increment behaviour in a couple of macros.  These now
  match the macros in the F14 tree.
Change a value of 0xFF that was getting truncated when being assigned
  to a 4-bit bitfield to a value of 0x0f.

This was tested with the torpedo build.
This fixes roughly 132 of the 561 warnings in the coreboot build
  so I'm not going to list them all.
  Here is a sample of the warnings fixed:

In file included from src/cpu/amd/agesa/family12/model_12_init.c:35:0:
src/include/cpu/amd/amdfam12.h:52:5: warning: redundant redeclaration of 'get_initial_apicid' [-Wredundant-decls]
In file included from src/cpu/amd/agesa/family12/model_12_init.c:34:0:
src/include/cpu/amd/multicore.h:48:5: note: previous declaration of 'get_initial_apicid' was here

src/northbridge/amd/agesa/family12/northbridge.c:50:10: warning: no previous prototype for 'get_node_pci' [-Wmissing-prototypes]
src/northbridge/amd/agesa/family12/northbridge.c: In function 'get_hw_mem_hole_info':
src/northbridge/amd/agesa/family12/northbridge.c:302:13: warning: unused variable 'i' [-Wunused-variable]
src/northbridge/amd/agesa/family12/northbridge.c: In function 'domain_set_resources':
src/northbridge/amd/agesa/family12/northbridge.c:587:5: warning: format '%lx' expects argument of type 'long unsigned int', but argument 3 has type 'device_t' [-Wformat]
src/northbridge/amd/agesa/family12/northbridge.c:587:5: warning: format '%lx' expects argument of type 'long unsigned int', but argument 3 has type 'device_t' [-Wformat]
src/northbridge/amd/agesa/family12/northbridge.c:716:1: warning: format '%x' expects argument of type 'unsigned int', but argument 3 has type 'long unsigned int' [-Wformat]

In file included from src/mainboard/amd/torpedo/agesawrapper.h:31:0,
                 from src/northbridge/amd/agesa/family12/northbridge.c:38:
src/vendorcode/amd/agesa/f12/AGESA.h:1282:0: warning: "TOP_MEM" redefined [enabled by default]
In file included from src/northbridge/amd/agesa/family12/northbridge.c:34:0:
src/include/cpu/amd/mtrr.h:31:0: note: this is the location of the previous definition
In file included from src/mainboard/amd/torpedo/agesawrapper.h:31:0,
                 from src/northbridge/amd/agesa/family12/northbridge.c:38:
src/vendorcode/amd/agesa/f12/AGESA.h:1283:0: warning: "TOP_MEM2" redefined [enabled by default]

src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c: In function 'PcieInputParserGetNumberOfComplexes':
src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c:99:19: warning: operation on 'ComplexList' may be undefined [-Wsequence-point]
src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c: In function 'PcieInputParserGetLengthOfPcieEnginesList':
src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c:126:20: warning: operation on 'PciePortList' may be undefined [-Wsequence-point]
src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c: In function 'PcieInputParserGetLengthOfDdiEnginesList':
src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c:153:19: warning: operation on 'DdiLinkList' may be undefined [-Wsequence-point]
src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c: In function 'PcieInputParserGetComplexDescriptorOfSocket':
src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c:225:17: warning: operation on 'ComplexList' may be undefined [-Wsequence-point]

src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PciePhyServices.c:246:1: warning: no previous prototype for 'PcieFmForceDccRecalibrationCallback' [-Wmissing-prototypes]

In file included from src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexConfig.c:58:0:
src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/LlanoComplexData.h:120:5: warning: large integer implicitly truncated to unsigned type [-Woverflow]

And fixed a boatload of these types of warning:
src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c: In function 'HeapGetBaseAddress':
src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:687:17: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:694:19: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:701:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:702:23: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:705:23: warning: assignment makes integer from pointer without a cast [enabled by default]
src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:709:21: warning: assignment makes integer from pointer without a cast [enabled by default]

Change-Id: I97fa0b8edb453eb582e4402c66482ae9f0a8f764
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2348
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-18 05:01:53 +01:00
Stefan Reinauer 0aa37c488b sconfig: rename lapic_cluster -> cpu_cluster
The name lapic_cluster is a bit misleading, since the construct is not local
APIC specific by concept. As implementations and hardware change, be more
generic about our naming. This will allow us to support non-x86 systems without
adding new keywords.

Change-Id: Icd7f5fcf6f54d242eabb5e14ee151eec8d6cceb1
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2377
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14 07:07:20 +01:00
Stefan Reinauer 4aff4458f5 sconfig: rename pci_domain -> domain
The name pci_domain was a bit misleading, since the construct is only
PCI specific in a particular (northbridge/cpu) implementation, but not
by concept. As implementations and hardware change, be more generic
about our naming. This will allow us to support non-PCI systems without
adding new keywords.

Change-Id: Ide885a1d5e15d37560c79b936a39252150560e85
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2376
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14 02:00:10 +01:00
Zheng Bao 600784e8b9 spi.h: Rename the spi.h to spi-generic.h
Since there are and will be other files in nb/sb folders, we change
the general spi.h to a file name which is not easy to be duplicated.

Change-Id: I6548a81206caa608369be044747bde31e2b08d1a
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/2309
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-02-11 21:01:47 +01:00
Patrick Georgi 8cc8468971 Intel: Replace MSR 0xcd with MSR_FSB_FREQ
And move the corresponding #define to speedstep.h

Change-Id: I8c884b8ab9ba54e01cfed7647a59deafeac94f2d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2339
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-11 20:51:33 +01:00
Steven Sherk f04e68e9e2 Add MMCONF resource to AMD fam15 PCI_DOMAIN
This is a port of the following:
commit d5c998be99

	The coreboot resource allocator doesn't respect resources
	claimed in the APIC_CLUSTER. Move the MMCONF resource to the
	PCI_DOMAIN to prevent overlap with PCI devices.

original-Change-Id: I8541795f69bbdd9041b390103fb901d37e07eeb9
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    URL - http://review.coreboot.org/#/c/2167/

Change-Id: I6e585d5cf0d46bd58337a6801fb0690ab2dd000c
Signed-off-by: Steven Sherk <steven.sherk@se-eng.com>
Reviewed-on: http://review.coreboot.org/2248
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-04 23:59:42 +01:00
Mike Loptien 7407f43c2b Family 12: Update for string portability
Update function messages to be more portable by using
the __func__ compiler command instead of hard coded
function names.

Change-Id: I3368a831770df1b8449eb0c97ae4bb24f6678efd
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/2250
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-04 18:19:19 +01:00
Mike Loptien e133aab5b5 Family 15tn: Update for string portability
Update function messages to be more portable by using
the __func__ compiler command instead of hard coded
function names.

Change-Id: Ib8ab97666340a9481f3ab71f0f347382e964994f
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/2251
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-04 18:18:10 +01:00
Mike Loptien 6eced514bf Family 10: Update for string portability
Update function messages to be more portable by using
the __func__ compiler command instead of hard coded
function names.

Change-Id: Idf479980e427bbf0399bdbc15045d80f402f6dbe
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/2249
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-04 18:17:34 +01:00
Mike Loptien 8401453486 Family 15: Update for string portability
Update function messages to be more portable by using
the __func__ compiler command instead of hard coded
function names.

Change-Id: Ie71fec39df5e7703d35d6505dc7d5b55179e2c7e
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/2234
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-04 18:16:43 +01:00
Steven Sherk 1cbabb00d9 Add MMCONF resource to AMD fam15tn PCI_DOMAIN
In the process of verifying change it was discovered the MMCONF
default base address 0xA0000000 was set below mem_top 0xE0000000
and bus number 256 wasn't a relistic number. The Kconfig defaults were
changed to mirror fam15 defaults base address 0xF8000000 and bus
number 64. Verified changes with boot to OS.

This is a port of the following:
commit d5c998be99

	The coreboot resource allocator doesn't respect resources
	claimed in the APIC_CLUSTER. Move the MMCONF resource to the
	PCI_DOMAIN to prevent overlap with PCI devices.

original-Change-Id: I8541795f69bbdd9041b390103fb901d37e07eeb9
    Signed-off-by: Marc Jones <marc.jones@se-eng.com
    URL - http://review.coreboot.org/#/c/2167/

Change-Id: I47660061538f8889f528b9b880a82645074886a7
Signed-off-by: Steven Sherk <steven.sherk@se-eng.com>
Reviewed-on: http://review.coreboot.org/2260
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-04 18:14:35 +01:00
Martin Roth 7fb692bd86 Fam15tn: Move SPD read from mainboards into wrapper
Continuing with the mainboard cleanup for F15tn, move the functions
to read the SPD from the mainboards for Thatcher and Parmer into the
wrapper for the northbridge/amd/agesa/family15tn.

Move the SPD address customization for the mainboard into the
devicetree.cb file.

Unrelated side note - Porting.h has an un-closed #pragma pack(1)
that can cause confusing side-effects.  AGESA's structures all
use this, but coreboot's don't.  Be sure to include the coreboot
.h files BEFORE Porting.h is included, not after.

This fix has been tested.

Change-Id: I89cdd225be61f60c6b8e7020e6f8b879983bbd96
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2190
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
2013-02-01 04:00:02 +01:00
Hung-Te Lin 6fe0cab205 Extend CBFS to support arbitrary ROM source media.
Summary:
	Isolate CBFS underlying I/O to board/arch-specific implementations as
	"media stream", to allow loading and booting romstage on non-x86.

	CBFS functions now all take a new "media source" parameter; use
	CBFS_DEFAULT_MEDIA if you simply want to load from main firmware.
	API Changes:
		cbfs_find => cbfs_get_file.
		cbfs_find_file => cbfs_get_file_content.
		cbfs_get_file => cbfs_get_file_content with correct type.

CBFS used to work only on memory-mapped ROM (all x86). For platforms like ARM,
the ROM may come from USB, UART, or SPI -- any serial devices and not available
for memory mapping.

To support these devices (and allowing CBFS to read from multiple source
at the same time), CBFS operations are now virtual-ized into "cbfs_media".  To
simplify porting existing code, every media source must support both "reading
into pre-allocated memory (read)" and "read and return an allocated buffer
(map)". For devices without native memory-mapped ROM, "cbfs_simple_buffer*"
provides simple memory mapping simulation.

Every CBFS function now takes a cbfs_media* as parameter. CBFS_DEFAULT_MEDIA
is defined for CBFS functions to automatically initialize a per-board default
media (CBFS will internally calls init_default_cbfs_media).  Also revised CBFS
function names relying on memory mapped backend (ex, "cbfs_find" => actually
loads files). Now we only have two getters:
	struct cbfs_file *entry = cbfs_get_file(media, name);
	void *data = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, name, type);

Test results:
 - Verified to work on x86/qemu.
 - Compiles on ARM, and follow up commit will provide working SPI driver.

Change-Id: Iac911ded25a6f2feffbf3101a81364625bb07746
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2182
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-30 17:58:32 +01:00
Steven Sherk 5fc64dca45 Rename family15 pci northbridgeops functions.
This is a port of the following
commit 8a49ac7f80

    Rename fam14 pci northbridge ops functions.

    Clarify the northbridge ops function names.

original-Change-Id: If7d89de761c1e22f9ae39d36f5cf334cc2910e1d
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Id7889bf02e2696220081251acdf695327267c796
Signed-off-by: Steven Sherk <steven.sherk@se-eng.com>
Reviewed-on: http://review.coreboot.org/2225
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-01-30 17:39:50 +01:00
Steven Sherk f434058b04 Rename family15tn pci northbridgeops functions.
This is a port of the following
commit 8a49ac7f80

    Rename fam14 pci northbridge ops functions.

    Clarify the northbridge ops function names.

original-Change-Id: If7d89de761c1e22f9ae39d36f5cf334cc2910e1d
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Icda3ec58219baa177af3b1dce729c6ad1f744be8
Signed-off-by: Steven Sherk <steven.sherk@se-eng.com>
Reviewed-on: http://review.coreboot.org/2226
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-01-30 17:37:34 +01:00
Mike Loptien 58089e859d Family 14: Update for string portability.
Update function messages to be more portable by using
the __func__ compiler command instead of hard coded
function names.

Change-Id: I6327c9769c2544bbc56155a2f89afd767487faf6
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/2227
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-01-30 17:36:10 +01:00
Marc Jones d5c998be99 Add MMCONF resource to AMD fam14 PCI_DOMAIN.
The coreboot resource allocator doesn't respect resources
claimed in the APIC_CLUSTER. Move the MMCONF resource to the
PCI_DOMAIN to prevent overlap with PCI devices.

Change-Id: I8541795f69bbdd9041b390103fb901d37e07eeb9
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/2167
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Steve Goodrich <steve.goodrich@se-eng.com>
2013-01-22 19:17:35 +01:00
Marc Jones 8a49ac7f80 Rename fam14 pci northbridge ops functions.
Clarify the northbridge ops function names.

Change-Id: If7d89de761c1e22f9ae39d36f5cf334cc2910e1d
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/2166
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-01-22 12:18:10 +01:00
Martin Roth 73e86a88d2 F15tn: Fix all warnings, enable warnings as errors
Enable 'all warnings being treated as errors' in thatcher and parmer.

Fixed the following warnings on parmer / thatcher:
src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c:
 In function 'GetGlobalCpuFeatureListAddress':
src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c:291:14:
 warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]

src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:
 In function 'SaveDeviceContext':
src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:245:18:
 warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:309:16:
 warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]

src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c:
 In function 'GetPstateGatherDataAddressAtPost':
src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c:235:10:
 warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]

src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c:
 In function 'MemNInitNBDataTN':
src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c:353:32:
 warning: assignment from incompatible pointer type [enabled by default]
src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c:363:23:
 warning: assignment from incompatible pointer type [enabled by default]

src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c:
 In function 'GetGlobalCpuFeatureListAddress':
src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c:291:14:
 warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]

src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:
 In function 'SaveDeviceContext':
src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:245:18:
 warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:309:16:
 warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]

In file included from src/northbridge/amd/agesa/family15tn/northbridge.c:37:0:
src/vendorcode/amd/agesa/f15tn/AGESA.h:1547:0:
 warning: "TOP_MEM" redefined [enabled by default]
src/include/cpu/amd/mtrr.h:31:0:
 note: this is the location of the previous definition
src/vendorcode/amd/agesa/f15tn/AGESA.h:1548:0:
 warning: "TOP_MEM2" redefined [enabled by default]
src/include/cpu/amd/mtrr.h:34:0:
 note: this is the location of the previous definition
In file included from src/northbridge/amd/agesa/family15tn/northbridge.c:41:0:
src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h:378:0:
 warning: "LOCAL_APIC_ADDR" redefined [enabled by default]
src/include/cpu/x86/lapic_def.h:9:0: note:
 this is the location of the previous definition

In file included from src/mainboard/amd/parmer/BiosCallOuts.h:24:0,
                 from src/mainboard/amd/parmer/mainboard.c:28:
src/vendorcode/amd/agesa/f15tn/AGESA.h:1547:0:
 warning: "TOP_MEM" redefined [enabled by default]
src/include/cpu/amd/mtrr.h:31:0:
 note: this is the location of the previous definition
src/vendorcode/amd/agesa/f15tn/AGESA.h:1548:0:
 warning: "TOP_MEM2" redefined [enabled by default]
src/include/cpu/amd/mtrr.h:34:0: note:
 this is the location of the previous definition

Change-Id: Iecea28232f1761401cf09f7d2a77d3fbac2f5801
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2171
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-01-22 12:17:07 +01:00
Martin Roth 2892023fd4 AGESA F15tn: Move callouts into northbridge wrapper
There are currently too many things in the mainboard directories that
are really more suited to being in the northbridge / southbridge
wrappers.  This is a start at moving some of those functions down
into the wrappers.

Move the bios callback functions into the northbridge/amd/agesa/family15tn
directory from the mainboard directories.  These can still be overridden
by any mainboard just by updating the pointer in the callback table to
point to a customized version of the function.

Change-Id: Icefaa014f4a4abbe51870aee7aa2fa1164e324c1
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2169
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-01-21 18:54:51 +01:00
Martin Roth 2d8815197e F15tn: Modify devicetree to fix S3 resume
The way that devicetree.cb was configured for the family 15tn boards
was doing... interesting things to the video device initialization.
This was causing S3 resume to fail.

There is a disconnect between how the devicetree should be configured
if there are multiple HT links on the CPU and how it's configured if
there's only one HT link.  These platforms were set up as if they
had multiple HT links, which was causing duplicate instances of
devices in the device list.

The scan for the IO Hub was removed from the northbridge code which
isn't a problem for F15tn devices.

Change-Id: I3556b43027746e36b07de7cb1bece4d1b37a3c34
Signed-off-by: Martin Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/2160
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-01-21 18:52:30 +01:00
Stefan Reinauer 816e9d1f0e Support for Celeron 1007U
Change-Id: I6b96b0e387dc3e6985eb1476fea612772a2288bc
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2145
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin@se-eng.com>
2013-01-14 23:21:03 +01:00
Aladyshev Konstantin 9027845d65 rd890: clear IO-APIC before setup
Add function "clear_ioapic" before "setup_ioapic" for RD890 northbridge
like it is done for SB700 and SB800 chipsets ("amd/cimx/sb{7,8}00").

No functionality change is noticed.

Change-Id: I1fd87692d8bf35c166141c9b7a6a1e748c19a636
Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru>
Reviewed-on: http://review.coreboot.org/2045
Tested-by: build bot (Jenkins)
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-01-04 06:38:24 +01:00
Dave Frodin cbf3d407b8 Add function to map vendor/device to generic VBIOS IDs
Change-Id: I4d7c4ec2b91c97eacf96770c150c2b9a61309053
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1982
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-12-07 20:42:33 +01:00
Stefan Reinauer 8d7115560d Rename devices -> device
to match src/include/device

Change-Id: I5d0e5b4361c34881a3b81347aac48738cb5b9af0
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1960
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2012-11-30 23:59:58 +01:00
Ronald G. Minnich 5079a0d32f Remove assembly coded log2 function
As we move to supporting other systems we need to get rid of assembly
where we can. The log2 function in src/lib is identical to the assembly
one (tested for all 32-bit signed integers :-) and takes about 10 ns
to run as opposed to 5ns for the non-portable assembly version. While speed
is good, I think we can spare the 15 ns or so we add to boot time
by using the C version only.

Change-Id: Icafa565eae282c85fa5fc01b3bd1f110cd9aaa91
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/1928
Tested-by: build bot (Jenkins)
2012-11-28 07:57:17 +01:00
Patrick Georgi bbc880eee7 amdk8/amdfam10: Use CAR_GLOBAL for sysinfo
This gets rid of the somewhat unstructured placement of AMD's
sysinfo structure in CAR.
We used to carve out some CAR space using a Kconfig variable,
and then put sysinfo there manually (by "virtue" of pointer magic).

Now it's a variable with the CAR_GLOBAL qualifier, and build
system magic.

For this, the following steps were done (but must happen together
since the intermediates won't build):
- Add new CAR_GLOBAL sysinfo_car
- point all sysinfo pointers to sysinfo_car instead of GLOBAL_VAR
- remove DCACHE_RAM_GLOBAL_VAR_SIZE
  - from CAR setup (no need to reserve the space)
  - commented out code (that was commented out for years)
  - only copy sizeof(sysinfo) into RAM after ram init, where
    before it copied the whole GLOBAL_VAR area.
  - from Kconfig

Change-Id: I3cbcccd883ca6751326c8e32afde2eb0c91229ed
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1887
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-28 07:45:05 +01:00
Stefan Reinauer 721265b87a Drop driver-y from GM45/ICH9/RK9
This broke because those components were not yet
committed when the patch to drop the driver class
was made.

Change-Id: I29948223503a6c4b196eafa169c064cd26da1be1
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1934
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-27 23:52:02 +01:00
Patrick Georgi e135ac5a7e Remove AMD special case for LAPIC based udelay()
- Optionally override FSB clock detection in generic
  LAPIC code with constant value.
- Override on AMD Model fxx, 10xxx, agesa CPUs with 200MHz
- compile LAPIC code for romstage, too
- Remove #include ".../apic_timer.c" in AMD based mainboards
- Remove custom udelay implementation from intel northbridges' romstages

Future work:
- remove the compile time special case
  (requires some cpuid based switching)
- drop northbridge udelay implementations (i945, i5000) if
  not required anymore (eg. can SMM use the LAPIC timer?)

Change-Id: I25bacaa2163f5e96ab7f3eaf1994ab6899eff054
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1618
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-27 23:51:52 +01:00
Patrick Georgi 23f38cd05c Get rid of drivers class
The use of ramstage.a required the build system to handle some
object files in a special way, which were put in the drivers
class.

These object files didn't provide any symbols that were used
directly (but only via linker magic), and so the linker never
considered them for inclusion.

With ramstage.a gone, we can drop this special class, too.

Change-Id: I6f1369e08d7d12266b506a5597c3a139c5c41a55
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1872
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-27 22:00:49 +01:00
Patrick Georgi 2efc8808b8 intel/gm45: new northbridge
The code supports DDR3 boards only. RAM init for DDR2 is sufficiently
different that it requires separate code, and we have no boards to
test that.

Change-Id: I9076546faf8a2033c89eb95f5eec524439ab9fe1
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1689
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-27 09:16:18 +01:00
Patrick Georgi 3c84261e84 yabel: Use X86_* instead of the more verbose M.x86.REG_*
Makes it more similar to what realmode looks like.

Change-Id: I4407431f2d979c43dd186114d67ed11845907afe
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1892
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-24 20:12:16 +01:00
Patrick Georgi 199b09cb7a x86 realmode: Use x86emu register file + defines
By using the (global) register file as defined by x86emu,
we can use the same register access for YABEL and realmode
interrupt handlers.

- the x86 realmode interrupt handlers changed in signature
- to access registers, use X86_$REGNAME now (eg. X86_EAX)
- x86_exception_handler still uses struct eregs *regs to
  avoid spilling the x86emu register file stuff everywhere

Coccinelle script that handled most of this commit:
  @ inthandler @
  identifier FUNC, regs;
  @@
  int FUNC(
  -struct eregs *regs
  +void
   )
  { ... }

  @ depends on inthandler @
  identifier regs;
  @@
  -regs->eax
  +X86_EAX

  @ depends on inthandler @
  identifier regs;
  @@
  -regs->ebx
  +X86_EBX

  @ depends on inthandler @
  identifier regs;
  @@
  -regs->ecx
  +X86_ECX

  @ depends on inthandler @
  identifier regs;
  @@
  -regs->edx
  +X86_EDX

  @ depends on inthandler @
  identifier regs;
  @@
  -regs->esi
  +X86_ESI

  @ depends on inthandler @
  identifier regs;
  @@
  -regs->edi
  +X86_EDI

  @ depends on inthandler @
  identifier regs;
  @@
  -regs->eflags
  +X86_EFLAGS

  @ depends on inthandler @
  identifier regs;
  @@
  -regs->vector
  +M.x86.intno

Change-Id: I60cc2c36646fe4b7f97457b1e297e3df086daa36
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1891
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-24 20:11:46 +01:00
Patrick Georgi 503af721a1 x86 realmode: Adapt to x86emu/YABEL style return codes
realmode int handlers must return the same codes as the YABEL
int handlers now: 1 for "interrupt handled", 0 for "not handled"
(ie. error).

Change-Id: Idc01cf64e2c97150fc4643671a0bc4cca2ae6668
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1890
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-24 20:06:24 +01:00
Patrick Georgi 3e77eb6d1e x86emu: Move realmode handler into own directory
It's really a feature in parallel to YABEL/x86emu. Reflect this in
the directory structure.

Change-Id: Ie88e4fa6bfef13d23c55b2db3faacbd90f8cc30b
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1889
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-24 20:05:00 +01:00
Kyösti Mälkki e4d40b4d6e Drop no-op bootblock.c
Deletes unused file:
   src/northbridge/amd/agesa/family15tn/bootblock.c

Change-Id: Ic29553e008839407755d25bf125d599fa1f6131c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1843
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-17 02:12:02 +01:00
Stefan Reinauer 6446626c1e Use new system agent binaries
Change-Id: I716564c4ea3b8e298cdeb82dc68e68474ed595cc
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1879
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-17 00:29:18 +01:00
Stefan Reinauer c5334635ca VIA chipsets: fix compilation without real mode code
The VIA chipsets CX700, VT8623 and VX800 required to be
configured with real mode option rom code enabled. This
patch fixes the issue and drops some unneeded header files.

Change-Id: I0d8a3f8f99c2eacec7666f08f85b99f09c06af84
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1833
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14 05:56:05 +01:00
Marc Jones 313ec9d15b Sandybridge: Set PEG clock gating
If the PEI System Agent doesn't run PCIe initialization, the PEG
clock gating will not be setup. Add the PEG clock gating when
pei_data->pcie_init is 0.

Change-Id: I7e31bcebd11feb4807aa29b528adf09fb013c3ce
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1827
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14 05:39:19 +01:00
Stefan Reinauer 7e8c8e92bb Add PCIe init and NMode flag to PEI data structure
The IvyBridge reference code does some slow and
extensive PCIe init that we do not need on Link.
Hence, add a flag to disable/enable running that
init code from coreboot.

NMode was used during bringup. We'll switch
the setting back to auto, to let MRC decide the right thing.

Change-Id: Ia989bb9ea079aadfeb41dc3029b7c2c623e84760
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1826
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14 05:38:47 +01:00
Duncan Laurie e8179b5138 Add ddr3lv_support flag to pei_data structure
This will enable DDR3 1.35V support for memory training in
the reference code.  It requires the board to be setup for
1.35V with whatever board-specific GPIOs are available.

Change-Id: I14e4686c20f9610f90678e6e3bece8ba80d8621a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1825
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14 05:38:17 +01:00
Marc Jones 53508fedf8 pei_data.h: Fix comment
I added a comment to the pei_data.h to remind users about
how the OC pins are mapped.

Change-Id: I4d74eb69fc78816a69e61260c2c9b2b3e58cafec
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1824
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14 05:37:38 +01:00
Vadim Bendebury 48a4a7f244 Provide MRC with a console printing callback function
Let memory initialization code use the coreboot romstage console. This
simplifies the code and makes sure that all output is available in
/sys/firmware/log.

The pei_data structure is modified to allow passing the console output
function pointer. Romstage console_tx_byte() is used for this purpose.

Change-Id: I722cfcb9ff0cf527c12cb6cac09d77ef17b588e0
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/1823
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14 05:19:21 +01:00
Stefan Reinauer e5a0a5d6df Initial IGD OpRegion implementation
Change-Id: I9e57c5792409830895a1147799acab95d910a336
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1757
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12 18:36:30 +01:00
Vadim Bendebury ad67791382 Avoid using hardcoded values in MRC cache code
The MRC cache code, as implemented, in some cases uses configuration
settings for MRC cache region, and in some cases - the values read
from FMAP. These do not necessarily match, the code should use FMAP
across the board.

This change also refactors mrccache.c to limit number of iterations
through the cache area and number of fmap area searches.

Change-Id: Idb9cb70ead4baa3601aa244afc326d5be0d06446
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/1788
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12 17:11:53 +01:00
Stefan Reinauer a1ea82283d Make coreboot use the offset parameter in cbfstool create
On Sandybridge and Ivybridge systems the firmware image has to
store a lot more than just coreboot, including:
- a firmware descriptor
- Intel Management Engine firmware
- MRC cache information
This option allows to limit the size of the CBFS portion in
the firmware image.

Change-Id: Ib87fd16fff2a6811cf898d611c966b90c939c50f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1770
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-09 19:07:34 +01:00
Stefan Reinauer 4c8027abdd Make register/value lists const
These can be stored in the code segment, since it's never changed.

Change-Id: I8b3827838e08e6cc30678aad36c39249fbca0c38
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1749
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-09 19:03:51 +01:00
Stefan Reinauer 357bb2daf0 SandyBridge/IvyBridge: Use flash map to find MRC cache
Until now, the MRC cache position and size was hard coded in Kconfig.
However, on ChromeOS devices, it should be determined by reading the
FMAP.

This patch provides a minimalistic FMAP parser (libflashmap was too
complex and OS centered) to allow reading the in-ROM flash map and
look for sections.

This will also be needed on some partner devices where coreboot will
have to find the VPD in order to set up the device's mac address
correctly.

The MRC cache implementation demonstrates how to use the FMAP parser.

Change-Id: I34964b72587443a6ca4f27407d778af8728565f8
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1701
Reviewed-by: Marc Jones <marcj303@gmail.com>
Tested-by: build bot (Jenkins)
2012-11-07 08:28:28 +01:00
Stefan Reinauer c6b9f926cc Add missing newline in error message
This is purely cosmetic. All error messages in the Sandybridge raminit
code printed a newline at the end.

Change-Id: I880d291928291d487039850a2a3d53a1101124ba
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1699
Reviewed-by: Marc Jones <marcj303@gmail.com>
Tested-by: build bot (Jenkins)
2012-11-07 08:28:13 +01:00
Siyuan Wang becacec022 AMD G34 CPU: change lapic_id in northbridge.c to accommodate G34 CPU
Each G34 socket has two node. Previous lapic algorithm is written for
the CPU which has one node per socket. I test the code on h8qgi with
4 family 15 CPUs(8 cores per CPU). The topology is:
socket 0 --> Node 0, Node 1
socket 2 --> Node 2, Node 3
socket 1 --> Node 4, Node 5
socket 3 --> Node 6, Node 7
Each node has 4 cores.
I change the code according to this topology.

Change-Id: I45f242e0dfc61bd9b18afc952d7a0ad6a0fc3855
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/1659
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-07 04:02:54 +01:00
Duncan Laurie cf81b8294b CMOS: Move MRC seed offset into upper bank
This will allow the lower bank to be cleared without impacting the
ability to suspend/resume.

Change-Id: Iaec3c9e7e40c334053c814eaddd1f614df245a73
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1696
Reviewed-by: Marc Jones <marcj303@gmail.com>
Tested-by: build bot (Jenkins)
2012-11-07 04:01:37 +01:00
Siyuan Wang 6f05c2eb59 AMD rd890 late.c: Don't enable PCIe ports after PCIe init.
PCIE devices are detected and initialized by the AMD PCIe init functions,
which is in cimx rd890. The parameters are read from devicetree.cb before PCIe init.
Now, all bridges and devices are trained on the device 0.0 enable.
After PCIe init, the PCIe ports with devices are on and the PCIe ports
without devices are off. so resources may be allocated correctly
during the rest of the PCI scan.

But if the devicetree was being used to enable/disable devices after initialization,
the problems would arise. Take a look at the serial log:

do_pci_scan_bridge for PCI: 00:02.0
PCI: pci_scan_bus for bus 01
PCI: pci_scan_bus returning with max=001
do_pci_scan_bridge returns max 1
do_pci_scan_bridge for PCI: 00:03.0
PCI: pci_scan_bus for bus 02
PCI: pci_scan_bus returning with max=002
do_pci_scan_bridge returns max 2
do_pci_scan_bridge for PCI: 00:04.0
PCI: pci_scan_bus for bus 03
PCI: pci_scan_bus returning with max=003
do_pci_scan_bridge returns max 3

PCI bridge 02.0, 03.0 and 04.0 are not inserted devices, but these bridges
are still scanned. This is not correct.

Change-Id: I87dac5f062c6926081970ed0c5f26a7e3f447395
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/1640
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-07 02:03:36 +01:00
Siyuan Wang fa678bb87f AMD agesa family15: PCI domain should scan bus from 0x18.0
There are four mainboards using agesa family15 code:
Supermicro h8scm and h8qgi, Tyan s8226 and AMD dinar.
All of these boards' PCI domain starts from 0x18.0. Take h8scm as
an example, PCI devices from 0.0 to 0x14.5 is under 0x18.0.
Now, the PCI domain's scan bus function stats from 0.0. This would
result to the PCI devices be scanned twice. Because when the function
run to device 18.0, it would scan from 0.0 again.
This issue would result to 2 problems:
1) PCI device may be assigned two different PCI address.
   If this happenned on VGA device, coreboot maybe not load
   vga bios correctly.
2) coreboot initializes rd890's IO APIC twice.
So this patch scans from 0x18.0 and could resolve the problems above.

Change-Id: I90fbdf695413fd24c7a5e3e9b426dc7ca6e128b1
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/1639
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-07 02:03:05 +01:00
Stefan Reinauer 1e0ddf6f1f Fix some issues with new "reference" toolchain
Unfortunately the reference tool chain was updated
without ever even testing it on an abuild run. This
broke a number of ports.

This change gets coreboot at least compiling again
for all supported systems.

Change-Id: I92c7cbc834de6d792fdab86b75df339e2874c52e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1670
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2012-11-02 18:06:49 +01:00
Sebastian Andrzej Siewior 3e9155dddf northbridge/sch: move the \n so it reads a little better
Without this, the output of "Setting up ACPI…" continues right
after the output of stepping.

Change-Id: I2ad7cc3e55884ff509600b01274258b8e8250981
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Reviewed-on: http://review.coreboot.org/1632
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2012-10-26 21:55:28 +02:00
Sebastian Andrzej Siewior 59e3e02991 northbridge/sch: read the size of main memory from the proper register
I don't know if the size main memory supposed to be in PCI(0,0) reg 0x9c
but it is not written there. The size of memory is written in
src/northbridge/intel/sch/raminit.c to SCH port(2, 8, 4) (look for
"Setting up TOM").

Change-Id: Iea04a5185bda56f61d1c382533d5a0dac429ebbd
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Reviewed-on: http://review.coreboot.org/1629
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2012-10-26 21:55:17 +02:00
Sebastian Andrzej Siewior 50dd47bb58 northbridge/sch: Read the GPU memory from the correct PCI device
The GGC register which contains the size of memory that is used for GPU
is in PCI device 2,0 and not 0,0. It is set to to 4MiB in
src/mainboard/iwave/iWRainbowG6/romstage.c.

Change-Id: Ie9f1cc60544ecd9cad770f34c83c33564a6129d4
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Reviewed-on: http://review.coreboot.org/1628
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2012-10-26 21:54:50 +02:00
Sebastian Andrzej Siewior 66fa9e2865 northbridge/sch: don't overwrite hightables with GPU / TSEG memory
Without this, the hightables are placed just before the end of memory.
However we might have the GPU memory located at the exact same spot,
that is in the last 4 MiB. So without this patch, this area won't remain
marked as "CONFIGURATION TABLES" within coreboot's memory table but
becomes "RESERVED" because it is part of the PCI(2,0) device.

Change-Id: Ibd111c167c2f6ac03b0ba68581a74ecbd2c9c160
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Reviewed-on: http://review.coreboot.org/1627
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2012-10-26 21:54:42 +02:00
Patrick Georgi 9aeb69447d hpet: common ACPI generation
HPET's min ticks (minimum time between events to avoid
losing interrupts) is chipset specific, so move it to
Kconfig.

Via also has a special base address, so move it as well.

Apart from these (and the base address was already #defined),
the table is very uniform.

Change-Id: I848a2e2b0b16021c7ee5ba99097fa6a5886c3286
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1562
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2012-10-08 21:23:08 +02:00
Kyösti Mälkki 02790369ff Remove chip.h files without config structure
Also deletes files not included in build:
    src/southbridge/amd/cimx/sb700/chip_name.c
    src/southbridge/amd/cimx/sb800/chip_name.c
    src/southbridge/amd/cimx/sb900/chip_name.c

Change-Id: I2068e3859157b758ccea0ca91fa47d09a8639361
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1473
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-10-07 12:55:04 +02:00
Patrick Georgi 72cee54fd6 HAVE_HIGH_TABLES is gone
... but no-one told intel/sch.

Change-Id: I68eaae6910bd6fc579c35b5bc038b9597cd1b3e7
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1537
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-09-25 16:09:19 +02:00
Siyuan Wang 128c7d7315 agesa fam15 northbridge: change lapic_id to accommodate two CPUs
According to http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/vendorcode/amd/agesa/f15/Proc/CPU/cpuApicUtilities.c;hb=HEAD#l273 line 273,
adjust apic id to accommodate two CPUs.
The Tyan S8226 has two CPU sockets, and the current code just finds one CPU's cores.
we adjust apic_id in cpu_bus_scan so as to find all CPUs.

Change-Id: Ib3263fc6f5508f744b81e8e388fde9ccd9b51851
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/1498
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-09-19 23:16:10 +02:00
Kyösti Mälkki 87213b655e Fix AMD UMA for RS780
In commit 6b5eb1cc2d setup of
UMA memory region was moved to happen at a later state and
this broke UMA with RS780 southbridge.

Share the TOP_MEM and UMA settings before any of the PCI or CPU
scanning takes place.

Change-Id: I9cae1fc2948cbccede58d099faf1dfe49e9df303
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1488
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-28 23:27:10 +02:00
Kyösti Mälkki c33f1e9261 AMD northbridges: factor out CPU allocation
Factor CPU allocation out of AMD northbridge codes. As CPU topology
information is required for generation of certain ACPI tables, make
this code globally available.

For AMDK8 and AMDFAM10 northbridge, there is a possible case of
BSP CPU with lapicid!=0. We do not want to leave the lapic 0 from
devicetree unused, so always use that node for BSP CPU.

Change-Id: I8b1e73ed5b20b314f71dfd69a7b781ac05aea120
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1418
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-27 15:36:47 +02:00
Kyösti Mälkki cd9fc1aa5f AMD northbridges: rewrite CPU allocation
Use of alloc_find_dev() prevents creation of a device duplicates
for device_path and is SMP safe.

Reduce scope of variables to make the code more readable and in
preparation for refactoring the allocation out of northbridge.c.

Change-Id: I153dc1a5cab4f2eae4ab3a57af02841cb1a261c0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1186
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-27 15:35:34 +02:00
Kyösti Mälkki fee73df07a Auto-declare chip_operations
The name is derived directly from the device path.

Change-Id: If2053d14f0e38a5ee0159b47a66d45ff3dff649a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1471
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-22 05:06:41 +02:00
Kyösti Mälkki dbc4739a0d AMD northbridge: copy TOP_MEM and TOP_MEM2 for distribution
Take a copy of BSP CPU's TOP_MEM and TOP_MEM2 MSRs to be distributed
to AP CPUs and factor out the debugging info from setup_uma_memory().

Change-Id: I1acb4eaa3fe118aee223df1ebff997289f5d3a56
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1387
Tested-by: build bot (Jenkins)
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-09 19:15:32 +02:00
Stefan Reinauer 7874e9dcfc Sandybridge: Fix integer overrun in romstage udelay()
This was broken, fixing according to related patch for i945

Change-Id: I925cd205ee5beb918181740a7b981a4209688ac6
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1412
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-08-09 17:01:56 +02:00
Kyösti Mälkki cf8e466084 Cleanup coreboot memory table includes
The includes removed here were previously required for
struct lb_memory and lb_add_memory_range().

Change-Id: Ie6c0d4ef55c2225aa709cf3fbad30ff1080e3610
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1391
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2012-08-08 11:42:07 +02:00
Kyösti Mälkki 7bdf85bfdb Move cpus_ready_for_init() to AMD K8
The function is a noop for all but amd/serengeti_cheetah.

Change-Id: I09e2e710aa964c2f31e35fcea4f14856cc1e1dca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1184
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-07 06:40:41 +02:00
Stefan Reinauer 9ca1c0af64 Sandy/Ivy Bridge and Cougar/Panther Point: Fix names
The names were set at various times during development, but
the way the code works, you might end up with the wrong name
being displayed in the logs. Instead of doing magic, just
display both names for each component

Change-Id: I1f8ce44d156442f5f7d717e1a2b47ed1218d4527
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1413
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-08-07 01:05:47 +02:00
zbao ffb6bddea2 AMD f15: Change multiply ONE_MB to bit shifting (Propagation)
Apply the change
http://review.coreboot.org/1263
to family15 northbridge.

Change-Id: If1109f20ffd833a716e092c5e4f6f16ee6b968c7
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
[km: rebased]
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1405
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2012-08-05 16:18:47 +02:00
zbao 15dc3ccaab AMD f15 nb: Remove the misleading 0x100 from the limitk (Propagation)
Apply the change
http://review.coreboot.org/1265
to all the AMD northbridge.

Change-Id: Idf3994c1e9ec76cd19db9f740d825cf24059884f
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1404
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-08-04 05:42:03 +02:00
zbao 49bb26a469 AMD NB: Limit the device field to 5 bits. (Propagation)
Apply the change
http://review.coreboot.org/1264
to all the AMD northbridge.

Change-Id: Ied74d6f579d2c0350288e2619d7810f8d44fa574
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1403
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-08-04 05:41:27 +02:00
zbao d462736dfb Limit the device field to 5 bits.
The field device in PCI_ADDRESS only takes 5 bits. So if the device number is
more than 32, it will truncated to 5 bits. Before this patch, other pci devices
will be incorrectly probed as processor node.

Change-Id: I64dcd4f4fda7b7080a9905dce580feb829584b94
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1264
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-02 18:19:00 +02:00
Kyösti Mälkki 6b5eb1cc2d AMD and GFXUMA: move setup_uma_memory() to northbridge
UMA region can be determined at any time after the amount
of RAM is known and before the uma_resource() call.

Change-Id: I2a0bf2d3cad55ee70e889c88846f962b7faa0c7e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1379
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-02 12:56:09 +02:00
Kyösti Mälkki 30f04645c1 AMD Agesa and GFXUMA: drop use of uma_memory_base
Without GFXUMA, variables were not referenced anywhere.
Fail builds on Family10 if GFXUMA is selected, because the northbridge
code does not set UMA base or size.

Change-Id: I15b91cf6241e9a890398eed03824b753828a0a51
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1247
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-02 12:55:28 +02:00
Kyösti Mälkki f803ac4a45 AMD K8 and AMDFAM10, GFXUMA: drop use of uma_memory_base
The code in rs690 or rs780 is always used with K8 or AMDFAM10
northbridge. Without GFXUMA, both of these set the same static value
indirectly using the variable uma_memory_base.

Make the register setting with immediate value, to remove the obscure
use of variable uma_memory_base.

Change-Id: I5354684457a76e73013b4e34a4538a6d122eee8d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1246
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-02 12:54:55 +02:00
zbao 9fd183efde AMD F15tn northbridge: Remove the misleading 0x100 from the limitk.
I dont known if missed something, but why an extra 0x100 was added to limit?
My board would get the wrong memory table entry 7f000000-7fffffff as RAM, which
is higher than TOM.
coreboot memory table:
0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1. 0000000000001000-000000000009ffff: RAM
2. 00000000000c0000-000000005e13efff: RAM
3. 000000005e13f000-000000005effffff: CONFIGURATION TABLES
4. 000000005f000000-000000007effffff: RESERVED
5. 000000007f000000-000000007fffffff: RAM
6. 00000000a0000000-00000000afffffff: RESERVED

Ronald G. Minnich:
 I think someone who wrote the code was trying to round up the
next 0x100 boundary and did it incorrectly.
Here is code that would do it correctly:
limitk = ((resource_t)((d.mask + 0x00000ff) & 0x1fffff00)) << 9 ;

Zheng:
 Plus 0xFF is correct, but the d.mask take bit 0 as enable it.
This bit should be clear when we try to calculate the limitk.

Change-Id: I3848ed5f23001e5bd61a19833650fe13df26eef3
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1265
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-08-01 17:24:04 +02:00
Kyösti Mälkki 5e29f00c55 Intel and GFXUMA: drop redundant use of lb_add_memory_range()
Use of uma_resource() in northbridge code created a memory
resource marked as reserved. Such resources are removed
from system memory in write_coreboot_table().

Change-Id: I14bfd560140d8d30ec156562f23072bfae747bde
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1238
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-01 11:53:27 +02:00
Kyösti Mälkki 7f189cc74e Intel Sandybridge and UMA: use mmio_resource()
With SandyBridge northbridge code, uma_memory_size was reset to
zero before variable MTRRs were set. This means MTRR setup routine
did not previously create a un-cacheable hole for uma.

Keep the behaviour that way, mmio_resource() has a prerequisuite that
the new region does not overlap with any cacheable ram_resource().

The result is not optimal setup in the number of used MTRRs, but
continue with this approach until MTRR algorithm is improved.

Change-Id: I63c8df19ad6b6350d46a3eca3055abf684b8b114
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1373
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-01 10:58:44 +02:00
Kyösti Mälkki 1ec5e744c6 Intel Sandybridge: add reserved memory as resources
Reserved memory resources will get removed from memory table at
the end of write_coreboot_table(),

Change-Id: I02711b4be4f25054bd3361295d8d4dc996b2eb3e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1372
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-01 10:57:17 +02:00
Sven Schnelle d4ee8082f1 sandybridge: reinitialize usbdebug after MRC
MRC messes with USB devices, so we have to reinitialize
USB debug after MRC has finished.

Change-Id: I45c0a687cebd69d0a31235bb870f8c455f42d4f2
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1377
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2012-07-30 20:54:03 +02:00
Kyösti Mälkki 6ff1d36a47 Intel and GFXUMA: fix MTRR and use uma_resource()
Commit 2d42b34003 changed the
variable MTRR setup and removed compensation of uma_memory_size in
the cacheable memory resources.

Since the cacheable region size was no longer divisible by a large
power of 2, like 256 MB, this caused excessive use of MTRRs.
As first symptoms, slow boot with grub and poor user response.

As a solution, register the actual top of low ram with ram_resource(),
and do not subtract the UMA/TSEG regions from it.

TSEG may require further work as the original did not appear exactly
right to begin with. To have UMA as un-cacheable, use uma_resource().

Change-Id: I4ca99b5c2ca4e474296590b3d0c6ef5d09550d80
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1239
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Tested-by: build bot (Jenkins)
2012-07-27 15:54:08 +02:00
Kyösti Mälkki 08ef498d0b Intel 82810 and 82830: always room for PCI memory
No need for the test, tomk is at most 1GB on these chipsets.
Even if there was no room, adjusting the memory resource would not
not divert accesses in the hardware from DRAM to PCI.

Change-Id: I2213b8d9d2e6ab8da8fd3e8081cc62bb05b6b316
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1369
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-07-27 14:05:15 +02:00
Kyösti Mälkki b5f5652e0f Intel i945 and sch: no memory over 4GB
No need for the test, tomk is top of low memory and always below 4GB.

Change-Id: Ifc8f29268b761aa9b07b578673236a673f0c70b5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1368
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-07-27 11:18:07 +02:00
Patrick Georgi efff733ad8 Refactor driver structs
Our driver infrastructure became more flexible recently.
Make use of it.
These are the low hanging fruits (files with 5 device
variants or more), but there are still lots of files
with less potential for deduplication.

Change-Id: If6b7be5046581f81485a511b150f99b029b95c3b
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1358
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2012-07-26 22:25:10 +02:00
Patrick Georgi 7dc2864be7 amd/lx: Move configuration from source to Kconfig
LX has two values that are usually automatically derived but can
be overridden, that were so far defined in each board's romstage.

These values, along with the toggle to enable override are now
part of LX's Kconfig. For boards that gave values but requested
autogeneration, the values are removed.

Further improvements: Figure out the various fields in PLLMSRlo
and make them sensible Kconfig options (instead of the hex value
it is now)

Change-Id: I8a17c89e4a3cb1b52aaceef645955ab7817b482d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1227
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-07-26 21:33:31 +02:00
Duncan Laurie 1b3207ee61 CTDP: Only do TDP down/nominal change from TNP0
Otherwise there is a flurry of TDP changes with suspend/resume
as the kernel powers devices off on suspend and brings them
back online in resume.

This also adds a mutex around the TDP operations since it is
split across two methods and can't just rely on being Serialized.

Change-Id: I7757d3ddad34ac985a9c8ce2fc202e2b2dcb2527
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1348
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-07-26 21:12:31 +02:00
Duncan Laurie 55864eff92 ACPI: Add support for runtime config TDP down
The required power MSRs are mirrored in MCHBAR so
it is possible to configure TDP at runtime via ASL.

This adds the required fields and a set of methods to
configure "TDP down" and "TDP nominal".  It explicitly
does not support "TDP up" at the moment.

PSSS: method is added to assist in searching the _PSS
table for the appropriate entry that corresponds to the
desired max non-turbo ratio.

STND: Set TDP Down from Nominal.  This will limit CPU to
the TDP down configuration by sequencing the required
changes in the right order.

STDN: Set TDP Nominal from Down.  This will set the CPU
back to nominal configuration by sequencing the required
changes in the correct (reverse) order.

This does not introduce any functional changes and must
be paired with additional changes to be useful.

The current configured TDP can be checked to see that
the transition to/from a desired level is successful.

> mmio_read8 0xfed15f50
0x00  # TDP-Nominal

> mmio_read8 0xfed15f50
0x01  # TDP-Down

Change-Id: I31a2f30cc9d134cc5eee980ae9288ae45e71c6e6
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1344
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-26 20:33:06 +02:00
zbao 405cfe219a Change multiply ONE_MB to bit shifting.
2048 * ONE_MB will cause warning,
src/northbridge/amd/agesa/family15tn/northbridge.c:667:50: warning: integer overflow in expression [-Woverflow]
I guess it will change the data type to signed integer.
I think the bit shifting is better.

Change-Id: I823f7ead1f7d622bf653cb3bf2ae2343f5e76805
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1263
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-07-25 22:15:17 +02:00
zbao d59d62484d sync the northbridge.c with other family.
Change-Id: Ice4d0202590fca0169dcda2770ca6add166b5c13
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1262
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-25 01:18:03 +02:00
Duncan Laurie f4d362339f ELOG: Add support for a monotonic boot counter in CMOS
This maintains a 32bit monotonically increasing boot counter
that is stored in CMOS and logged on every non-S3 boot when
the event log is initialized.

In CMOS the count is prefixed with a 16bit signature and
appended with a 16bit checksum.

This counter is incremented in sandybridge early_init which is
called by romstage.  It is incremented early in order notice
when reboots happen after memory init.

The counter is then logged when ELOG is initialized and will
store the boot count as part of a 'System boot; event.

Reboot a few times and look for 'System boot' events in the
event log and check that they are increasing.  Also verify
that the counter does NOT increase when resuming from S3.

171 | 2012-06-23 16:02:55 | System boot | 285
176 | 2012-06-23 16:26:00 | System boot | 286
182 | 2012-06-23 16:27:04 | System boot | 287
189 | 2012-06-23 16:31:10 | System boot | 288

Change-Id: I23faeafcf155edfd10aa6882598b3883575f8a33
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1315
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-25 00:47:10 +02:00
Stefan Reinauer 696262bd99 More descriptive error messages in Sandybridge raminit code
MRC returns specific error codes; print the according error
message if we know what it means.

Change-Id: Iaaf1512b9d577d4291fccfb94d879043ab5b11b5
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1289
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-25 00:35:45 +02:00
Duncan Laurie 9c4c6ab0c8 ELOG: Fix boot count increment for non-wake case
The count was only incrementing for a wake from S5 and
it was not incrementing in the normal reboot case.

Change-Id: I73bc6db6bd02e6c4677f7e44a5c098c6dcb51747
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/1328
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-24 23:52:30 +02:00
Duncan Laurie fe7b5d2fa6 Ivybridge: fix workaround and enable PAIR
MCHBAR 0x5f10[7:0] should be set to 0x30 for ivybridge
and 0x20 for sandybridge.  Move this code to ramstage
and set it per-chipset.

Power Aware Interrupt Routing is supported in ivybridge,
enable it and set fixed priority.

Boot on ivybridge device and read MCHBAR 0x5f10:

mmio_read8 0xfed15f10
0x30

And verify PAIR is enabled (bit4=1):

mmio_read8 0xfed15418
0x24

Change-Id: If017d5ce2bd5ab5092c86f657434f2b645ee6613
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1303
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-24 23:50:59 +02:00
Duncan Laurie 77dbbac7e7 CPU: Add basic support for Nominal Configurable TDP
Ivybridge B0+ CPUs are capable of supporting multiple TDP levels.
This complicates the default case because now the registers that
were reporting max non-turbo ratio are reporting that value for
the highest possible TDP level.

For now this change just forces everything to use the Nominal TDP
values instead of the higher (or lower) levels.

- When building P-state tables, determine the P[1] (max non turbo)
ratio based on the Nominal ratio if available.
- Set the turbo activation ratio to the Nominal max ratio.
- Mirror the power level settings in new MCHBAR register after
they are written, which happens after BIOS_RESET_CPL is set.
- Set the current ratio to Nominal ratio at boot.

1) Verify that P-state table is generated properly with
P[0]=1801MHz (ratio 0x1C) and P[1]=1800MHz (ratio 0x12)

PSS: 1801MHz power 17000 control 0x1c00 status 0x1c00
PSS: 1800MHz power 17000 control 0x1200 status 0x1200

2) Verify power limits in MCHBAR match PKG_POWER_LIMIT:

> rdmsr 0 0x610
0x800080aa00dc8088
> mmio_read32 0xfed159a4
0x000080aa
> mmio_read32 0xfed159a0
0x00dc8088

3) Verify turbo activation ratio is set to nominal ratio:

> rdmsr 0 0x64c
0x0000000000000012

4) Check that proper ratio was set at boot on one core only:

> grep 'frequency set to' /sys/firmware/log
model_x06ax: frequency set to 1800
model_x06ax: frequency set to 1800
model_x06ax: frequency set to 1800
model_x06ax: frequency set to 1800

Change-Id: I592e60a7740f31b140986a8269dca91b4adbb270
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1304
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-24 23:39:44 +02:00
Stefan Reinauer b91a0f2b83 Rename cache_lbmem() to cache_ramstage()
... and don't require it to specify a cache type.
This function is only used on romcc boards, and should go away
(because all boards should be switched to CAR)

Change-Id: Ic32ca3be1afffc773c72c140e88b338d48a0c8ca
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1288
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-24 23:30:00 +02:00
Stefan Reinauer 6097e193fc Make ACPI code detect Sandy/Ivy Bridge dynamically
On systems with socketed CPUs we want to be able to
drop in a Sandy Bridge or Ivy Bridge CPU without recompiling the
firmware. Hence, detect the north bridge dynamically. In order
for this to work, we need Ivy Bridge MRC and coreboot configured
for Ivy Bridge.

Change-Id: I635bef2c61d47d36a3fdd87f8ecb6e69097ba969
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1281
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-24 19:53:13 +02:00
Stefan Reinauer afcaac2db5 Drop (empty) sandybridge_late_initialization()
The function is empty (a left-over from i945) and should be removed.

Change-Id: I91e573b5e37cb9133ea1037aef7e6daf3c292864
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1290
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-24 15:54:43 +02:00
Stefan Reinauer baae2d2761 Add support for HM70 and NM70 LPC bridge
This lets the SPI driver and the LPC driver know about HM70 and NM70.

Change-Id: Id2f1e0e5586a2f7200b2d24785df3f2be890da98
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1300
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-24 12:26:26 +02:00
Stefan Reinauer 542e9628ae Print PCI ID of PCH during boot up
Right now, if we have an unknown PCH, coreboot will print something like
this:

PCH type: Unknown rev id 4

Instead, it should also print the PCI ID of the device, so we can add it
to the list of known PCHes.

Change-Id: Ib0b96e287c36d2895d1287b1734ca13d75e7985a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1287
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-24 11:34:56 +02:00
Stefan Reinauer c664387082 Drop leading spaces from CPU name string
This is as per Intel's suggestion on how to display their name strings.

Change-Id: Ie82341305e58baa8041e50a61a11b395fa7d9582
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1298
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2012-07-24 10:13:24 +02:00
Stefan Reinauer 48214899c3 Fix MRC cache update delays
When no valid MRC cache area is found, the mrc_cache data structure
was used without prior initialization. This sometimes caused a long
delay when booting because compute_ip_checksum would checksum up to
4GB of memory.

Change-Id: I6a0ca1aa618838bbc3d042be425700fc34b427f2
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1277
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-24 06:55:35 +02:00
Walter Murphy 496f4a0c83 SandyBridge: Add another PCI device ID for northbridge
Change-Id: I153579561f7eed6d4befd74ff39e1a5e778d0e46
Signed-off-by: Walter Murphy <wmurphy@google.com>
Reviewed-on: http://review.coreboot.org/1269
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2012-07-24 00:14:23 +02:00
Duncan Laurie da83a5f18e Fixes to enable RC6 on IvyBridge
- The unneeded poll on non-MT force-wake bit was timing out
and causing the gma_pm_init_pre_vbios() function to exit
early so it was not preparing PM registers properly.
I changed the gtt_poll() calls to not return on timeout
unless it can't proceed so we don't see half-initialized
registers.

- RC6+ (Deep Render Standby) is not working reliably so we
can just enable RC6 in the BIOS and let the kernel decide
if it wants to enable RC6+ later.

This Kernel message is new in kernel 3.4:
[drm] Enabling RC6 states: RC6 on, RC6p off, RC6pp off

Change-Id: I69d005ba56be8c7684a4ea1133a1d761f7c07acc
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1268
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-24 00:02:55 +02:00
Patrick Georgi ce6e9fed2e i945: Disable IGD if plugin VGA is preferred
It's shut down, but UMA memory is not reclaimed. A later extension
could optionally do the magic register dance that allows initialization
of IGD as secondary graphics device.

Change-Id: I2a92bb71755005b886a8e1825325c678a9991bf2
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1252
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-07-22 17:01:29 +02:00
zbao 6db7f348ea Trinity wrapper code improvement.
Set the default location of hudson firmware to 3rdparty.
Move UMA code from mainboard to northbridge.

Change-Id: I11afea0c7fd04aa84a629dc762704c42baf002df
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1241
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-22 13:09:41 +02:00
Nico Huber 8bacc40fc7 Fix udelay() implementation for i945 romstage
Work around 32-bit overflow with 64-bit multiplication. Calculate
correct CPU frequency.

Change-Id: I86d78f2d70b9f9c62fd4e1e0d765e92e4de83f67
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1254
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-07-20 23:41:38 +02:00
Patrick Georgi bcdbe90296 Drop VGA_BRIDGE_SETUP config option
It defaults to true, and isn't disabled anywhere in the tree.
I also couldn't think of a case where it's actually useful.

Change-Id: I126a47625d5294f3cfff225629f2a948a83c9b7e
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1250
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-07-20 23:36:22 +02:00
Kyösti Mälkki cda9f93965 Intel SCH northbridge: fix resource index
Change-Id: If131ac9df89080faccd8ed952d6fc019483b5b2e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1237
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-07-20 01:53:06 +02:00
Kyösti Mälkki 1171986627 Drop invalid device ops on Agesa northbridge
One could not pass a device of type APIC to PCI resource functions.
The correct CPU model specific cpu->ops is set at later time in
cpu_initialize().

Change-Id: Ifa274185e4db3080433c1f07e3a48f2b55c0514f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1180
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16 20:33:59 +02:00
Kyösti Mälkki de3dde46fd AMD: Fix GFXUMA with 4GB or more RAM
Northbridge code incorrectly adjusted the last cacheable memory
resource to accomodate room for UMA framebuffer. If system had
4GB or more memory that last resource is not below 4GB and not
the one where UMA is located.

There are three consequences:

The last entry in coreboot memory table is reduced by uma_memory_size.

Due the incorrect code in northbridge code state.tomk,
end of last resource below 4GB, had not been adjusted.
Incrementing that by uma_memory_size diverts a region
possibly claimed for MMIO to RAM, as TOP_MEM is written.

Since the UMA framebuffer did not have IORESOURCE_CACHEABLE,
it was ignored from the MTRR setup and not set uncacheable.

The setting of TOP_MEM and TOP_MEM2, as well as all the MTRRs,
should be copied from BSP to all APs instead of deriving the data
separately for each Logical CPU.

Change-Id: I8e69fc8854b776fe9e4fe6ddfb101eba14888939
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1217
Tested-by: build bot (Jenkins)
Reviewed-by: Denis Carikli <GNUtoo@no-log.org>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16 18:57:43 +02:00
Kyösti Mälkki ba589e3630 Move setup_uma_memory() to K8 northbridge
These boards had identical UMA code:
  amd/dbm690t
  amd/pistachio
  technexion/tim5690
  technexion/tim8690

The ones below had whitespace or debug level change
compared to the one above:
  kontron/kt690
  siemens/sitemp_g1p1

These boards use AMDFAM10 guidelines in code:
  asrock/939a785gmh
  amd/mahogany

Change-Id: Id7c3f48035727f5847f2d7c3a6e87a3d15582003
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1210
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16 18:46:33 +02:00
Kyösti Mälkki 231f261402 Move setup_uma_memory() to AMDFAM10 northbridge
Following boards had identical code:
  advansus/a785e-i
  amd/bimini_fam10
  amd/mahogany_fam10
  asus/m5a88-v
  avalue/eax-785e
  gigabyte/ma78gm
  iei/kino-780am2-fam10
  jetway/pa78vm5

Following boards had identical code:
  amd/tilapia_fam10
  asus/m4a78-em
  asus/m4a785-m
  gigabyte/ma785gm
  gigabyte/ma785gmt

In between the two, only whitespace difference.

Change-Id: Iaa48cc7b0038ebcc81be49219b4fc87670aa9941
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1209
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16 18:45:37 +02:00
Kyösti Mälkki 55fff930ce Move setup_uma_memory() to Agesa Family14 northbridge
Following boards had identical code:
  amd/inagua
  amd/persimmon

The following had only whitespace or debug level changes
compared to ones above.
  amd/union_station
  amd/south_station
  asrock/e350m1

Change-Id: I11ee46e06e1dd510cba551166189ebcaa144464b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1208
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16 18:45:09 +02:00
Kyösti Mälkki d4821fc702 Move setup_uma_memory() to Agesa Family12 northbridge
Change-Id: Ieaf284c207f0cd4b2f6b804c52f949c16435d823
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1207
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16 18:44:29 +02:00
Kyösti Mälkki 03548aa6b8 Move setup_uma_memory() to Agesa Family15 northbridge
Change-Id: I5705623f5067823fae5986b3bcde58504a463508
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1206
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16 18:43:35 +02:00
Kyösti Mälkki cc55b9b919 Define global uma_memory variables
Use of the uma_memory_base and _size variables is very scattered.
Implementation of setup_uma_memory() will appear in each northbridge.

It should be possible to do this setup entirely in northbridge
code and get rid of the globals in a follow-up.

Change-Id: I07ccd98c55a6bcaa8294ad9704b88d7afb341456
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1204
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16 18:41:46 +02:00
Kyösti Mälkki 63f8c08830 Add global uma_resource()
Like ram_resource(), but reserved and not cacheable.

Switch all AMD northbridges to use this one.

Change-Id: I88515c6a0f59f80fd8607c390d0d4a2a35d805f2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1203
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16 18:38:46 +02:00
Sven Schnelle d4220691c5 i5000: Fix resource allocation
The current code didn't reserve static resource the right way.
Also reduce TOLM to 0xd0000000, because those boards have so many PCI
devices that 0xe0000000 isn't sufficient.

Change-Id: Ia75a81905eea1a096aed464b63ac154e044bc99c
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1220
Tested-by: build bot (Jenkins)
2012-07-16 08:40:48 +02:00
Sven Schnelle 34d86f0c61 i5000: reset system if raminit fails
Don't stop if RAM init fails at first try. It's better to restart
and try again instead of failing on the first try if the second
try would have worked.

Change-Id: Ib5660265d5b10a01588f2e4022dac2ee34f2c6d0
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1191
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
2012-07-09 11:34:37 +02:00
Sven Schnelle 7b48379575 i5000: Add PCI ids for all i5000 flavours
Change-Id: I48be647e3f38038830200bcc64429cbf86990ad7
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1174
Tested-by: build bot (Jenkins)
2012-07-06 16:40:30 +02:00
Patrick Georgi 6444bd4547 i945: Reset IGD on boot
This is mostly necessary for reboot, but it doesn't hurt the boot process.
On reboot explicitely reset the integrated graphics, otherwise the VGABIOS
might not be able to reinitialize it properly, and you either have a still
of the last pre-reboot image, garbage or an empty screen, but no text-mode.

Change-Id: Ic3d6932fbaf720d88daaac7e4b09c3c0b9f0b0e2
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1178
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2012-07-06 11:53:49 +02:00
zbao 2c08f6ade4 AGESA F15 wrapper for Trinity
The wrapper for Trinity. Support S3. Parme is a example board.

Change-Id: Ib4f653b7562694177683e1e1ffdb27ea176aeaab
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1156
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-03 09:38:55 +02:00
Nico Huber 904a0ec9d0 Don't use 64-bit constant 0x100000000 in linker scripts
The constant value 0x100000000 is used in linker scripts to calculate
offsets from the end of 32-bit-addressed memory. There is nothing
wrong with it, but 32-bit versions of ld do the calculation wrong.

Change-Id: I4e27c6fd0c864b4d98f686588bf78c7aa48bcba8
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1129
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2012-06-21 08:05:31 +02:00
Sven Schnelle 1454685327 i5000: fix another typo
As Mathias Krause pointed out, using movw/outw on %al is clearly invalid.
Let's do another typo fix...

Change-Id: Ib95832a11097f599a236ab30c64c26ef429a1699
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1119
Tested-by: build bot (Jenkins)
Reviewed-by: Mathias Krause <minipli@googlemail.com>
2012-06-20 20:24:29 +02:00
Sven Schnelle 39b47d2b03 i5000: fix typos
Peter and Ron pointed out two typos. They have no side effects, but
it's still worth to fix them.

Change-Id: I9aecccdbc72beb2623fbe558a06e4f1b050f6e74
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1117
Tested-by: build bot (Jenkins)
2012-06-20 16:37:18 +02:00
Sven Schnelle 1a7a7e610e i5000: enforce hard reset
Not doing a hard reset leaves the BOFL0 register cleared, which
prevents the BSP selection from working. To make sure we start
with known values, use the SPAD0 register for soft reset detection.
If there's a value other than 0, do a hard reset.

Change-Id: I390e3208084cfd32d73cce439ddf2bc9d4436a62
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1103
Tested-by: build bot (Jenkins)
2012-06-18 09:03:35 +02:00
Stefan Reinauer 88fc0b9e8d Sandybridge: Remove remnants of FDT support from MRC cache code
Originally, ChromeBooks would get the offset of the MRC cache
from an entry in the u-boot device tree. Not everyone wants to
use u-boot on Sandybridge systems, however.
Since the new code (based on Kconfig) is now fully working, we
can drop the u-boot device tree remnants.

Change-Id: I4e012ea981f16dce9a4d155254facd29874b28ef
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1051
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-29 11:27:42 +02:00
Stefan Reinauer 6e901fd3d2 Sandybridge: Fix MRC cache calculation
The MRC region is described by Kconfig variables, no further math
or parsing is required at this point.

Change-Id: I290d8788b69ef007e9ea2317ce55aefa2d791883
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1046
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-29 11:26:31 +02:00
Vikram Narayanan 2f00ce3d96 cbtypes.h: Unify cbtypes.h used in AMD board's code
Remove all the repeated sections of code in cbtypes.h and place it
in a common location. Add include dir in vendor code's Makefile.

Change-Id: Ida92c2a7a88e9520b84b0dcbbf37cd5c9f63f798
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Reviewed-on: http://review.coreboot.org/912
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-05-24 17:38:42 +02:00
Stefan Reinauer bb11e60cb2 Hook up MRC cache update
Requirements:
  - must be in ramstage (locking flash while executing code from there
    might not work)
  - must be after cbmem is reinitialized (so the mrc cache copy of the
    current run can be found)

Change-Id: I8028fb073349ce2b027ef5f8397dc1a1b8b31c02
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1002
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-11 00:30:03 +02:00
Stefan Reinauer 1244f4b52f Rework Sandybridge MRC cache handling
- Separate Sandybridge from ChromeOS a bit
  The Sandybridge code depends on chromeos features a whole lot.
  As a first step, provide a code path to look up the MRC cache
  without depending on u-boot.

- Move mrc cache handling to separate file
  This enables us to handle the MRC cache from ramstage,
  where we can write the flash safely (eg. to update the
  cache).
  Also teach it to lookup the current MRC cache from CBMEM,
  as the original data block isn't available anymore.

After all the preparations, finally write to the SPI
as necessary. It's a simple round robin wear levelling
that erases the entire MRC cache region when it's full
and starts from the beginning.

Change-Id: I4751385574cf709b03d5c9d153b7481ffc90ce12
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1001
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-11 00:29:44 +02:00
Patrick Georgi f8f00629e3 Some more #if cleanup
Replace #elif (CONFIG_FOO==1) with #elif CONFIG_FOO
find src -type f -exec sed -i "s,\(#.*\)(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]1),\1\2,g" {} +
(manual tweak since it hit a false positive)

Replace #elif (CONFIG_FOO==0) with #elif !CONFIG_FOO
find src -type f -exec sed -i "s,\(#.*\)(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]0),\1\!\2,g" {} +

Change-Id: I8f4ebf609740dfc53e79d5f1e60f9446364bb07d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1006
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Martin Roth <martin@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-05-08 00:38:11 +02:00
Patrick Georgi e166782f39 Clean up #ifs
Replace #if CONFIG_FOO==1 with #if CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1[[:space:]]*\$,#if \1," {} +

Replace #if (CONFIG_FOO==1) with #if CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1)[[:space:]]*\$,#if \1," {} +

Replace #if CONFIG_FOO==0 with #if !CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0[[:space:]]*\$,#if \!\1," {} +

Replace #if (CONFIG_FOO==0) with #if !CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0)[[:space:]]*\$,#if \!\1," {} +

(and some manual changes to fix false positives)

Change-Id: Iac6ca7605a5f99885258cf1a9a2473a92de27c42
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1004
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Martin Roth <martin@se-eng.com>
2012-05-08 00:34:34 +02:00
Stefan Reinauer f125d80135 Add missing newline to printk in Sandybridge init code
Change-Id: I9217a75ec1a0abb898c45752d990231ce98e5fb2
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/991
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-03 20:33:22 +02:00
Stefan Reinauer adc05c14c7 Make Intel i5000 specific options only appear on i5000 systems
Change-Id: If183611b0b62d9321a5a12311c4cb3b344b04b36
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/986
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-02 21:06:56 +02:00
Stefan Reinauer cafedcf5c8 Strip quotes from Sandybridge MRC blob
This fixes my build when specifying an absolute path to the binary.

Change-Id: I95fb3960be70f78146c6afeb9cc777dccdca6b5b
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/987
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-02 20:00:27 +02:00
Vadim Bendebury 7a3f36a228 Sandybridge: Display platform information early
It is important to have the system configuration reported as early as
possible to have a better idea what exact chipset the platform is
running with.

This change adds code to have an early coreboot module report the CPU
and PCH information. CPU info includes the 32 bit feature information
word, the symbolic processor brand string, and information about some
features support, as obtained through CPUID instructions.

The PCH information includes the symbolic device name and PCI device
version.

Change-Id: If6c21ad5ffb76d7d57d89f4f87d04bdd7192480a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/975
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-02 19:52:37 +02:00
Duncan Laurie 8508cff035 Update Ivybridge GT power meter tables
- New table for GT1
- Updates to GT2 17W table
- New table for GT2 35W SKU
- New table for GT2 Other

This also includes a workaround to poll on a different register
when deasserting force wake.  On some SKUs the kernel is hanging
when bringing up graphics unless this register is also polled.

Change-Id: I2badf62b464e901cfb0eaf4fc196f59111c71564
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/974
Tested-by: build bot (Jenkins)
2012-05-01 20:07:02 +02:00
Duncan Laurie dd585b8825 Update ivybridge graphics initialization
- Add config options to set backlight registers
- Update powermeter weight tables for IvyBridge GT1 and
add a new table for GT2 SKU
- Fix a few registers used during GPU PM init sequence

Change-Id: I1500bc07e3ba1bc10c77e7856089e716489dc07a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/973
Tested-by: build bot (Jenkins)
2012-05-01 20:06:47 +02:00
Duncan Laurie 7b508ddecb Only send ME Dram Init Done message on Sandybridge
This is done inside the SystemAgent binary on Ivybridge.

Change-Id: I8fb0f593a65a4803e160b284c21b9d5021e2e4a0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/970
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-01 20:04:41 +02:00
Vincent Palatin 0ff99b70f5 Modify DMI init for IvyBridge
The ASPM setting for the Direct Media Interface should no longer be done on
Ivybridge/PantherPoint based systems.

Change-Id: Id30de1beb1b162564048e76712736ccf7049dc7c
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: http://review.coreboot.org/969
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-01 20:04:24 +02:00
Stefan Reinauer e6063fee5c Fix Sandybridge/Ivybridge mainboards according to code review
This fixes a few cosmetics with the following three boards:

 - Intel Emerald Lake 2
 - Samsung ChromeBook
 - Samsung ChromeBox

The following issues were fixed:

 - rely on include path in ASL code instead of specifying relative
   paths
 - use updated ALIGN_CURRENT in acpi_tables.c
 - use preprocessor defines instead of hard coded values where possible

Change-Id: Ia5941be3873aa84c30c13ff2f0428d1c52daa563
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/963
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
2012-05-01 19:27:34 +02:00
Stefan Reinauer 6ea86b19f3 Sandybridge: Temporarily disable MRC cache finding code
This code is still using libfdt which was denied for inclusion
in coreboot, so it won't compile as is.
Without MRC cache, waking from suspend won't work, and cold boots are
significantly slower (adds around 300-400ms per channel IIRC).
A rework of this code is currently in the works, but will take a little bit
more time (and should not hold back the mainboards being merged)

Change-Id: Ifb9e7d7b86c1f52378803a748810da0d51b58384
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/948
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-30 23:07:31 +02:00
Martin Roth a403c687b1 Add default map_oprom_vendev() for AMD Family 14h processors.
AMD supplies their video bios for the Family 14h processor line
with Vendor ID: 1002, Device ID: 9802.  This rom should work for
Device IDs 9802-9809.  This patch maps all those device IDs to
0x9802 so coreboot will be able to load the vbios.  If a vbios
rom using the ACTUAL Device ID is loaded, this function will not
be called.
This file should contain of all Family 14h Graphics PCI IDs so
that they don't need to be overridden on a per mainboard basis.

Change-Id: If3d4a744b3c400dea9444a61f05382af2b2d0237
Signed-off-by: Martin L Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/955
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-04-30 17:20:32 +02:00
Martin Roth e9dfdd9dbd Reverse Vendor ID & Device ID for map_oprom_vendev()
- When calling map_oprom_vendev() the vendor ID and device ID
  are joined into a 32 bit value.  They were reversed from the
  order that I would have expected - Device ID as the high 16 bits
  and the Vendor ID as the low 16.  This patch reverses them so
  so that the the dword comparison in map_oprom_vendev() matches
  what's entered into Kconfig for vendor,device.
- Change files calling map_oprom_vendev()

Change-Id: I5b84db3cb1a359a7533409fde7d05fbc6ba3fcc4
Signed-off-by: Martin L Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/938
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-28 02:45:22 +02:00
Stefan Reinauer 16401b8f6d SMM: Add udelay on Sandybridge systems
Cougar Point southbridge does udelay in SMM, hence add it on Sandybridge
systems.

Change-Id: I6e5520ca27e7c6eaae632992fb68612067bc1e30
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/937
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-27 19:24:19 +02:00
Kyösti Mälkki 93b4ed91f6 Intel e7505: build as separate object file
No longer include northbridge files directly in the source for
mainboard romstage.c and fix includes.

Also make required adjustments to function declarations.

Change-Id: Iafdcc0766ed44c64cc628e5935eef2c6372f5f22
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/906
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-04-21 09:39:27 +02:00
Kyösti Mälkki 97c064f034 Intel e7505: enable ECC scrubbing
It takes about 3 seconds to scrub 8GiB DDR266 RAM.

After ECC scrub XIP cache is disabled for system stability. There is
very little to do in romstage after ECC scrub, especially when RAM
debug messages are turned off. So the delay caused by this is hardly
noticeable.

Cache for complete ROM is re-enabled before ramstage is decompressed,
and it has no unstability issues. So the code required to re-enable
cache for ROM currently already exists in cache-as-ram_ht.inc.

A Kconfig option HW_SCRUBBER enables the scrub to be run on hard
reboots and power-ons.

Change-Id: Icf27acf73240c06b58091f1229efc0f01cca3f85
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/905
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-04-21 09:37:04 +02:00
Patrick Georgi 26b00e6d39 Refactor some alignment handling
Made using coccinelle:
  @@
  expression E;
  @@
  -(E + 7) & -8
  +ALIGN(E, 8)

  @@
  expression E;
  @@
  -(E + 15) & -16
  +ALIGN(E, 16)

Change-Id: I071d2c98cd95580d7de21d256c31b6368a3dc70b
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/910
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-04-20 21:18:02 +02:00
Kyösti Mälkki 77e4f7ddda Intel e7505: refactor only
Drop comments (from e7501 era) which no longer seem to apply with
e7505. Write the semi-constant D0:F0 table as code. Some register
settings seem to be in different order compared with vendor BIOS,
and will be handled by follow-up patches.

Split RCOMP register copy function in two parts.
Drop some uses of inline and local_mdelay().

Change-Id: I8739d3b2bbad5861118e8b16ccea1dd86991204f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/896
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2012-04-19 20:40:53 +02:00
Kyösti Mälkki 26c7b86907 Intel e7505: handlers for undocumented registers
Makes the code a bit more readable, IMO. There is no clean way
to implement this as the affected registers are undocumented.

Seems ROMCC cannot handle the enum. Also any of my future changes
would not be even abuild tested as there is no longer a board with
ROMCC and this chipset. E7505 chipset is CAR only from now on.

Change-Id: I0e2d8ba0c7ed7cce46d9eafb8d8badf04cf75f7a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/895
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-17 10:57:04 +02:00
zbao f72237346d S3 code in coreboot public folder.
1. Move the Stack to high memory.
2. Restore the MTRR before Coreboot jump to the wakeup vector.

Change-Id: I9872e02fcd7eed98e7f630aa29ece810ac32d55a
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/623
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-04-16 18:22:47 +02:00
Patrick Georgi 2c2e78d845 Unify IO APIC address specification
Some places still hardcoded the address instead of using IO_APIC_ADDR.

Change-Id: I3941c1ff62972ce56a5bc466eab7134f901773d3
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/677
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-04-12 00:06:11 +02:00
Kyösti Mälkki 5c1ff9284a Intel e7505: cleanups
Fix delay loop comments. Time waited and the comments did not match
in the origin (e7501), so delays currently "just work".

Move reset detection to main raminit and don't use generic
sdram_initialize for now, as there are local debug
functions I need to use. Fix AOpen respectively.

Disable ecc scrub, until I have it fixed for cache-as-ram use.

Change-Id: I0529297f43c565d30b5fb7d1836700278ac029c4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/883
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-11 23:25:09 +02:00
Kyösti Mälkki 5bd271b9fa Intel e7505: renames only
Drop maybe-prefix in registers and tables.
Have a name in place of PCI_DEV(x,y,z) to avoid confusion.

Change-Id: I88f51b50d7fd83294aa14455a83418630e1bab85
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/882
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-04-11 23:24:52 +02:00
Bernhard Urban cab72d9b7b amdfam10: add phenom II as known cpu
Change-Id: I84a0f9e8e7a15c0aac8dc380de3ddf70b1decbd7
Signed-off-by: Bernhard Urban <lewurm@gmail.com>
Reviewed-on: http://review.coreboot.org/864
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-05 23:12:24 +02:00
Stefan Reinauer 00636b0dae Add support for Intel Sandybridge CPU (northbridge part)
Change-Id: I06228ecf9cac931ad34e32871d5a4f2a4857b2ac
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/854
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-05 20:59:31 +02:00
Rudolf Marek c0c5ac7c90 Add the support for RDC R8610 Northbridge
So far the it just setups the internal resource management for coreboot and
detects the memory size.

Change-Id: I8506390fa6656abfa40d92b8f6ede9b91fe98680
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/807
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-27 18:37:57 +02:00
Stefan Reinauer dd3b227fb9 Fix AMD Fam15 CBMEM allocation
The Fam15 northbridge.c had hardcoded the CBMEM size. It should use
the one in cbmem.h instead.

Change-Id: I8a00e05884bdb1d1a4a012433b0adfbb9eb22983
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/796
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-03-16 23:17:53 +01:00
Stefan Reinauer 30b46cefb5 Fix AMD Fam12 CBMEM allocation
The Fam12 northbridge.c had hardcoded the CBMEM size. It should use
the one in cbmem.h instead.

Change-Id: I1eca18e21fa59ae32e802d8452e42e8b7a3575cf
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/795
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-03-16 23:17:45 +01:00
Stefan Reinauer cc6c615d29 Fix AMD Fam10 CBMEM allocation
The Fam10 northbridge.c had hardcoded the CBMEM size. It should use
the one in cbmem.h instead.

Change-Id: Id6c4128d8f5f6a417f83daa3a39b2bfc8e810f8a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/794
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-03-16 23:17:28 +01:00
Kyösti Mälkki 3ae1c65127 AMD Agesa: delete no-op bootblock files
Removes files:
  src/northbridge/amd/agesa/family10/bootblock.c
  src/northbridge/amd/agesa/family12/bootblock.c
  src/northbridge/amd/agesa/family14/bootblock.c
  src/northbridge/amd/agesa/family15/bootblock.c

Change-Id: Ic3617a673b38d065ca272c4de8ef765ecd3f98b1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/793
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-16 22:40:48 +01:00
Kyösti Mälkki d11ca1d08d Rename AMD_AGESA to CPU_AMD_AGESA
Also any CPU_AMD_AGESA_FAMILYxx selects CPU_AMD_AGESA, so remove
the explicit selects from the mainboards.

Change-Id: I4d71726bccd446b0f4db4e26448b5c91e406a641
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/792
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-16 22:40:35 +01:00
Kyösti Mälkki f5bb4771de Fix AMD Agesa leaking Kconfig
Kconfig leaked XIP_ROM_SIZE to other platforms and also
defined obsolete option XIP_ROM_BASE.

Alias AMD_AGESA as NORTHBRIDGE_AMD_AGESA.
Break the circular dependency with family15 Kconfig.

Change-Id: Ic7891012220e1bef758a5a39002b66971d5206e3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/773
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-16 22:39:09 +01:00
Kyösti Mälkki eb5e28ffc6 Intel northbridge I945: Apply un-written naming rules
Use NORTHBRIDGE_INTEL_I945 to select the driver directory for build.

Use _SUBTYPE_945GC and _SUBTYPE_945GM to define at compile-time
which model of I945 the driver is built for.

Change-Id: I11b1e0998d0fc28f8946bad4f0989036a9b18af4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/684
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-16 21:40:20 +01:00
Kyösti Mälkki 35e1c861f5 VIA southbridge K8T890: Apply un-written naming rules
Use separate Kconfig option to select a driver directory for
build and the specific type of southbridge to support.

Change-Id: I9482d4ea0f0234b9b7ff38144e45022ab95cf3f3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/685
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-16 19:45:47 +01:00
Marc Jones 5750ed253a Fix AMD Fam14 cbmen allocation
The Fam14 northbridge.c had hardcoded the cbmem size. It should use
in cbmem.h instead.

Change-Id: I910329fc98a4cf04dc81ef66f3aa05a1916f5b1d
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/790
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2012-03-16 19:31:03 +01:00
Marc Jones 8d595698bf Clean up whitespace in fam14 northbridge.c
Change-Id: Id7947d7f3c67fdda67861065b1bc7a519b97208f
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/789
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2012-03-15 21:27:20 +01:00
Patrick Georgi c5fc7db355 Move C labels to start-of-line
Also mark the corresponding lint test stable.

Change-Id: Ib7c9ed88c5254bf56e68c01cdbd5ab91cd7bfc2f
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/772
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-07 17:48:03 +01:00
Marc Jones 067d22340c Fix ECC disable option for AMD Fam10 DDR2 and DDR3.
The logic was backwards on the ECC enable/disable option. Also added better
debug output when the debug RAM init feature is enabled.

Change-Id: I60bffb6149d96cac65011247ef51cd06ed2210c6
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/670
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-02 23:35:26 +01:00
Patrick Georgi 334328a51f Avoid ../../.. paths in ASL files
The current directory is always part of the search path of cpp when
using #include "..."

Change-Id: I74fe39e0c79835e4b9a927afcbeab21040d8ae52
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/648
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-17 19:25:35 +01:00
Patrick Georgi fdcd135b96 Rename i945 ACPI files to not carry an i945_ prefix
In the spirit of the earlier renames.

Change-Id: I458a42c79a164483120169d1822ffa6861cc3aff
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/647
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-17 19:24:30 +01:00
Patrick Georgi 472efa6041 Remove whitespace.
Fix issues reported by new lint test.

Change-Id: I077a829cb4a855cbb3b71b6eb5c66b2068be6def
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/646
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-17 19:04:31 +01:00
Kerry Sheh 6811f75457 AGESA F15: AGESA family15 model 00-0fh northbridge wrapper
Change-Id: I87c4d47f19161c604b0285102bb3809c8337375a
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/556
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-02-16 21:26:14 +01:00
Kerry Sheh 6b909f21af RD890: AMD RD890/SR56X0 CIMX wrapper
Support AMD RD890 CIMX support AMD RD890TV, RX780, RD780, SR56x0,
RD890 and 990FX chipsets.

Change-Id: I39dc5fc316fbb465808bac48a13a49b7d867f04f
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/559
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-02-16 19:35:09 +01:00
Sven Schnelle bdc8c83614 Remove non-existent include
Change-Id: I702d59371b4a57ce22623cbab6e936b653d57edf
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/619
Tested-by: build bot (Jenkins)
2012-02-10 14:54:36 +01:00
Sven Schnelle 332a7e91c7 i5000: halt second BSP
If both FSBs on i5000 are equipped with CPU packages, one CPU
from each package is elected as BSP. To prevent races between
both BSPs, hlt the second BSP.

Change-Id: I6bfcb17d34e9f028280acff1694309e37307ec21
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/615
Tested-by: build bot (Jenkins)
2012-02-10 10:28:18 +01:00
Sven Schnelle 17670866a0 Add Intel i5000 Memory Controller Hub
Change-Id: Ic169f3f61babfcfa2ddcb84fc0267ebcf8c5f3bb
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/491
Tested-by: build bot (Jenkins)
2012-02-02 13:49:33 +01:00
Peter Stuge 751508ab01 northbridge/intel/i945: CHECK_SLFRCS_ON_RESUME Kconfig option
Originally brought up by Sven Schnelle in March 2011
http://patchwork.coreboot.org/patch/2801/
http://www.coreboot.org/pipermail/coreboot/2011-March/064277.html

On some mainboards it may be neccessary to reset early during resume
from S3 if the SLFRCS register indicates that a memory channel is not
guaranteed to be in self-refresh.

On other mainboards, such as Lenovo X60 and T60, the check always
creates false positives, effectively making it impossible to resume.

The SLFRCS register is documented on page 197 of

Mobile Intel® 945 Express Chipset Family Datasheet
Document Number: 309219-006

which is publically available, and the register indicates if a memory
channel is guaranteed to be in self-refresh mode (if bit = 1), or that
a memory channel *may or may not be* in self-refresh mode (if bit = 0).

The register can thus only be used to positively learn that memory is
in self-refresh. It is not known for sure that memory is *not* in
self-refresh. The register is reset by the PWROK signal, which *should*
go low during S3, and go high again when resuming, so it is unsurprising
that SLFRCS has already been cleared when we read the register.

Sven's measurements of the CKE signal on a ThinkPad shows that memory
remains in self-refresh indefinitely, until coreboot re-initializes the
memory controller, even when SLFRCS bits were = 0.

Boards which require a warm reset when SLFRCS bits are cleared must now
explicitly enable the check in the mainboard Kconfig file.

This commit selects the new option in all existing i945 mainboards.
A follow-up commit will remove the option for ThinkPads.

Change-Id: I02320675efb8fde05c371ef243ba5093a4da6d11
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/590
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>
2012-01-31 14:52:22 +01:00
Nils Jacobs 976f8cc1e2 Make Geode GX2 VGA setup work.
Add MSR register write for VGA memory setup
Add missing license
Add bit explanation

Change-Id: I1cb36eeccd84f0056c829f50d9864047654ce906
Signed-off-by: Nils Jacobs <njacobs8@adsltotaal.nl>
Reviewed-on: http://review.coreboot.org/580
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-01-26 22:15:56 +01:00
Sven Schnelle 784ffb3db6 i945: fix tsc udelay()
The comparision is the wrong way round: as long as tsc
is below tsc1, the timeout is not reached

Change-Id: I75de74ef750b5a45be0156efaf10d7239a0b1136
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/530
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-01-10 12:54:09 +01:00
Nils Jacobs d0ac789e21 Update geode GX2 tree to match LX.
Change-Id: I5b99c531e44ea09990b9da0b97213fb7945f34ee
Signed-off-by: Nils Jacobs <njacobs8@adsltotaal.nl>
Reviewed-on: http://review.coreboot.org/512
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-01-07 11:46:50 +01:00
Marc Jones 84e0dfcbf2 Clean up AMD Fam14 SSDT
The old SSDT ACPI code would only include the AGESA or the coreboot SSDT. Now
include both. AGESA generates the Pstate SSDT and the second coreboot SSDT is
for TOM and TOM2. Now, generate the coreboot SSDT instead of patching it. This
fixes some ACPI errors in Linux and Windows bluescreens.

The Persimmon acpi_tables.c is where the main changes were made and then
replicated in the other Fam14 boards. Please test the other mainbords if you
have one.

Change-Id: I808c863597e024e3e8aeec0821e8618d96cc96a6
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/516
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-01-05 17:29:11 +01:00
Nils Jacobs a4f06f183b White space and coding style fixes.
Change-Id: I14f39b5666fc18e8183723ec78a40a849d337736
Signed-off-by: Nils Jacobs <njacobs8@adsltotaal.nl>
Reviewed-on: http://review.coreboot.org/511
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2011-12-31 14:56:35 +01:00
Florian Zumbiehl 36b53bf244 k8: add CONFIG_K8_FORCE_2T_DRAM_TIMING and enable it for asus k8v-x
Change-Id: Ia457f92f6fb7e287defb838db07f12d0f1766757
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/481
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2011-12-14 08:50:45 +01:00
Kyösti Mälkki 2a830d0b98 Change AMD vendorcode build
Apply the normal method of recursively including subdirectories
for src/vendorcode. Remove redundant references under
mainboard and northbridge.

Change-Id: I914a6e262ed2abe83f407df36fe5c1af5eb4bcb0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/468
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-02 08:59:26 +01:00
Florian Zumbiehl fa48b96908 k8 raminit: fix bug, improve clock selection, add clock limit for sock754
in amdk8 raminit:
- fix DDR SPD offset for (CLX - 1) (25 instead of 26)
- improve clock/CL selection algorithm
- implement load-dependent clock limiting for socket 754

Change-Id: I5eb8a3e02eaca18f3bef9a98de22f23b23650762
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/377
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2011-11-23 01:05:40 +01:00
Florian Zumbiehl 6f7b1589fa fix DDR_MASK in load-dependent clock limiting for socket 939 in k8 raminit
Change-Id: Ibdce9712f5019863b1cd61b68da11d7c46c6b6f8
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/376
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2011-11-16 22:40:21 +01:00
Florian Zumbiehl 7e9de01c47 Cycle time at CAS Latency (CLX - 2) is at 25 in DDR2 SPD, not at 26
Change-Id: Ic77854130ad43715daa7c0eb462291db48df9f84
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/370
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-11-07 11:40:55 +01:00
Stefan Reinauer 5ff7c13e85 remove trailing whitespace
Change-Id: Ib91889a374515d36a2b12b53aeb12b6ea6e22732
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/364
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-11-01 19:07:45 +01:00
Kyösti Mälkki 0a0d5e8b86 Add support for E7505 northbridge.
Adapted from northbridge/intel/e7501 with only minor changes.
This commit provides minimal patch from e7501 and I prefer any
cosmetic clean-up to be done after initial merge.

Due the incomplete register specifications, it is safer to have
e7505 as a separate directory in case I improve it to support
wider range of memory configurations. I have no e7501 to test with.

Change-Id: Iba3bf9d69ff5e9d9ef3a6ebf8259f048c55d637d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/295
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-31 15:34:04 +01:00
Kyösti Mälkki 481814d1ab Clear improper use of CONFIG_CACHE_AS_RAM
Choice between printk/print_ is related to CAR, but really
depends whether we compiled with GCC or ROMCC.

Change-Id: I9fe831a215736462e8b3f4b96ffe231133ecf79b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/347
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-28 22:13:50 +02:00
Stefan Reinauer b15975bf5a copy e7501 component to e7505
Change-Id: Ie69a6b6a040a8b0e7693083b3a2d13c327a165b3
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/310
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-28 22:01:03 +02:00
Sven Schnelle 5563959b09 I945: replace #if defined() by #if
config.h defines also unset config options (as "0") so #ifdef
matches both settings, which isn't what we want.

Change-Id: I694e1b8a8ec4c20225d7af1a13a2a336f900e643
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/293
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-19 00:09:23 +02:00
Stefan Reinauer 328a694a3f AMD CPU and chipset fixes for compilation with gcc 4.6
Change-Id: I05b08765b38d8d6cc9b7cbdaf87c127b33408c81
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/266
Tested-by: build bot (Jenkins)
Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
2011-10-15 13:40:17 +02:00
Stefan Reinauer ab87254b61 use acpi.h include instead of manually adding acpi_slp_type.
Change-Id: I2a3aaf10e453fa6cce8a993356f2a0587178209a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/276
Tested-by: build bot (Jenkins)
Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
2011-10-15 12:30:02 +02:00
Stefan Reinauer 86fc9848ae Fix compilation of AMD GX2 northbridge code with gcc 4.6
Change-Id: I71d96b7cd36dd99a3590ec311c11f67f13012e68
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/267
Tested-by: build bot (Jenkins)
Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
2011-10-14 22:54:06 +02:00
Stefan Reinauer 89fcdec972 Fix compilation of VIA CN700 northbridge code with gcc 4.6
Change-Id: Ia52d21c5c467ec08bc7b958ee1a8e37e7d3e025b
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/265
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-14 19:12:10 +02:00
Stefan Reinauer b9d60c9ac8 fix compilation of intel/sch northbridge code with gcc 4.6
Change-Id: I57804dff9e37f0127900ebb7a67118382944eb89
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/264
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-14 08:12:25 +02:00
Christoph Grenz 80311eab8c amdk8: ASL include for K8 temperature sensor support in ACPI
Add a ACPI Source Language snippet which if included as
shown in the comments in the file, exposes the 4 possible
temperature sensors in the CPU as ACPI thermal zones.

Change-Id: I94dd773108e348a0fdb9d2f8d6cfe415d5fa0339
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/222
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-12 07:54:25 +02:00
enok71 af90275a41 TINY_BOOTBLOCK problem-fix on amdk8+amd8111 platforms
The hp/dl145_g1 motherboard did not work since commit
1f7d3c5672 (svn 6124). That commit added
TINY_BOOTBLOCK for amd8111 southbridge. The result was that the boot process
stopped very early (no console output whatsoever). The same symptom was
reported on other AMDK8 based boards with amd8111 southbridge chips. This
commit seems to fix the bug. It adds a bootblock.c under
src/northbridge/amd/amdk8 that calls enumerate_ht_chains. Probably the
problem was that enum_ht_chains needs to be called before the southbridge
bootblock.c function, not after.

Change-Id: I74fb892aa39048e2d0e76c081b713f825d67f2d4
Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
Reviewed-on: http://review.coreboot.org/235
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-03 23:17:33 +02:00
QingPei Wang 8eb4273290 Add AMD Family 10h PH-E0 support
the patch file comes from
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE
/F10MicrocodePatch010000bf.c

Change-Id: If701c8a908edf1c486665d3ce4df65da0f65c802
Signed-off-by: QingPei Wang <wangqingpei@gmail.com>
Reviewed-on: http://review.coreboot.org/202
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2011-09-24 15:58:12 +02:00
efdesign98 3f5ebd6533 AMD F14 Northbridge updates
This change is warning and whitespace fixes in the
northbridge code for AMD Family 14 rev C0 cpu update.
This does not address warnings in the mainboard,
Agesa, Cimx, or southbridge code.

Change-Id: I7ee7018a292ebb2343c9b7986dd21227185879dc
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/134
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-14 23:45:40 +02:00
Noe Rubinstein 03169d3e1c Replace while with do; while to avoid repetition
Cosmetic only; replaces some 'while' loops with 'do; while' loops to
avoid repetition.

Replacement performed by the Ruby expression:
t.gsub!(/^(\s*)([^\n\{]+)\n\1(while[^\n\{;]+)\n\s*\2/,
	"\\1do \\2\n\\1\\3;")

Change-Id: Ie0a4fa622df881edeaab08f59bb888a903b864fd
Signed-off-by: Noe Rubinstein <nrubinstein@proformatique.com>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/183
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-09 11:40:48 +02:00
Stefan Reinauer 7981b940a6 Report GSE chipset and warn if the code has been compiled for the wrong chipset.
It would be nicer to unify the code so that it does all detection at runtime
instead of compile time (but that would also significantly increase code size)
so if someone else wants to give it a shot...

Change-Id: Idc67bdf7a6ff2b78dc8fc67a0da5ae7a4c0a3bf0
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/184
Tested-by: build bot (Jenkins)
2011-09-09 11:40:04 +02:00
Kerry She feed329a0c AMD F14 southbridge update
This change adds the southbridge related code to support
the update of the AMD Family14 cpus to the rec C0 level.
Some of the changes reside in mainboard folders but they
reference changed files in the southbridge folder so they
are included herein.

Change-Id: Ib7786f9f697eaf0bf8abd9140c4dd0c42927ec7e
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Signed-off-by: Kerry She <kerry.she@amd.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/135
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-07 01:08:57 +02:00
Keith Hui e089a3f68d northbridge/intel/i440bx: Registered SDRAM modules support and fixes
Adds support for initializing registered SDRAM modules on
Intel 440BX northbridge.

Drops unneeded romcc-inspired programming tricks.

Only set nbxecc flags (see 440BX datasheet, page 3-16) when
a non-ECC module has been detected in a row via SPD; also
drops an unneeded intermediate variable used in setting them.

Boot tested on ASUS P2B-LS with regular and registered ECC
SDRAM under Linux and memtest86+.

Change-Id: Idc99d49567cca55f819d6b0e98952b1c3256498a
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: http://review.coreboot.org/128
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-08-04 08:15:49 +02:00
efdesign98 00c8c4a316 Update AMD SR5650 and SB700
This updates the code for the AMD SR5650 and SB700 southbridges.
Among other things, it changes the romstage.c files by replacing a
.C file include with a pair of .H file includes.  The .C file is
now added to the romstage in the SB700 or SR5650 Makefile.inc.
file to the romstage and ramstage elements.  This particular change
affects all mainboards that use the SB700, and their changes are
include herein.  These mainboards are:
  Advansus a785e,
  AMD Mahogany, Mahogany-fam10, Tilapia-fam10,
  Asrock 939a785gmh,
  Asus m4a78-em, m4a785-m,
  Gigabyte ma785gm,
  Iei Kino-780am2-fam10
  Jetway pa78vm5
  Supermicro h8scm_fam10
The nuvoton/wpcm450 earlysetup interface is changed because the file
is no longer included in the mainboard romstage.c files.

Change-Id: I502c0b95a7b9e7bb5dd81d03902bbc2143257e33
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/107
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry She <shekairui@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-07-22 00:20:59 +02:00
efdesign98 b58640c5ef Add AMD Family 10 cpu support to northbridge folder
This change adds the AMD Family 10 cpu support to the northbridge
folder.  The northbridge/amd/agesa Kconfig and Makefile.inc are
changed as well.

Change-Id: Id76e9fa388c79ac469a673aaedaa4f1bfd7619d9
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/98
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-07-18 21:55:59 +02:00
Scott Duplichan 7d6f0bf10e ASRock E350M1: ACPI-related BSOD fix
On installing/starting Windows (tested with Win7 Ultimate)
the system crashes with a Blue Screen of Death, reporting an ACPI BIOS error.

From Scott Duplichan:
To avoid the Windows BSOD, the uninitialized value TOM1 in the SSDT
must be corrected. The attached patch does this. It uses the older
patching method, and not the (possibly preferred) AML generation
method. To simplify the patching operation, I moved the AML item
'TOM1' to the start of the SSDT. The patch also includes code to
confirm the AML variable TOM1 is at the expected offset before patching.

Also tested & working with Linux.

Change-Id: I59cedc366e09d98f690b093d6a21fc0c864559c3
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marshall Buschman <mbuschman@lucidmachines.com>
Reviewed-on: http://review.coreboot.org/91
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2011-07-10 18:31:29 +02:00
Cristian Măgherușan-Stanciu 1fe6c64ba1 Fix memory size reporting on AMD family 14h systems for >= 4GB
Applying Scott Duplichan's fix for memory >=4GB

Adjusted it to the new directory structure (agesa_wrapper was renamed to
just agesa).

Boot-tested and confirmed to work, on my board Linux can now access the
whole RAM.

Change-Id: I31d66a488a7811d214d84653860b3e0116f67d19
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marshall Buschman <mbuschman@lucidmachines.com>
Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Reviewed-on: http://review.coreboot.org/48
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2011-07-09 01:51:42 +02:00
Rudolf Marek 23b215272d Improve VIA K8M890 HT settings. Use recommended settings for ROMSIP and
for the transmit clock driving control. Unfortunately this is not enough
to make the HT1000 work reliably, therefore blacklist this for now in CPU
HT code. If ever anyone figure out what is wrong, it could be removed. The
downgrading now makes the board work on HT800, which is certainly better than
not at all with a HT1000 CPU.

Change-Id: I949bfd9b0b48ee12bd0234c2fb1deaaa773bd235
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/68
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-30 19:16:37 +02:00
efdesign98 7c0c64e103 Addition of Family12/SB900 wrapper code
This change adds the wrapper code for the AMD Family12
cpus and the AMD Hudson-2 (SB900) southbridge to the cpu,
northbridge and southbridge folders respectively.

Change-Id: I22b6efe0017d0af03eaa36a1db1615e5f38da06c
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/53
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-28 23:09:25 +02:00
efdesign98 621ca384a7 Move existing AMD Ffamily14 code to f14 folder
This change moves the AMD Family14 cpu Agesa code to
the vendorcode/amd/agesa/f14 folder to complete the
transition to the family oriented folder structure.

Change-Id: I211e80ee04574cc713f38b4cc1b767dbb2bfaa59
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/52
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-22 01:35:45 +02:00
efdesign98 05a89ab922 Rename {CPU|NB|SB}/amd/*_wrapper folders
This change renames the cpu/amd/agesa_wrapper, northbridge/
amd/agesa_wrapper, and southbridge/amd/cimx_wrapper folders
to {cpu|NB}/amd/agesa and {SB}/amd/agesa to shorten and
simplify the folder names.
There is also a fix to vendorcode/amd/agesa/lib/amdlib.c to
append "ull" to a trio of 64-bit hexadecimal constants to
allow abuild to run successfully.

Change-Id: I2455e0afb0361ad2e11da2b869ffacbd552cb715
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/51
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-22 01:27:46 +02:00
Sven Schnelle b629d14bec i945 GMA: restore tft brightness from cmos
Change-Id: Iaf10f125425a1abcf17ffca1d6e246f955f941cc
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/24
Tested-by: build bot (Jenkins)
2011-06-15 19:40:24 +02:00
Sven Schnelle d8c68a9d08 i82801gx: replace cafed00d/cafebabe by defines
We're using '0xcafed00d' all over the code as magic for ACPI S3
resume. Let's add a define for that. Also replace 0xcafebabe by
a define.

Change-Id: I5f5dc09561679d19f98771c4f81830a50202c69f
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/33
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-06-15 15:15:07 +02:00
Marc Jones 471f103e53 This patch sets max freq defaults for ddr2 and ddr3for fam10.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Scott Duplichan <scott@notabs.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6619 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-03 19:59:52 +00:00
Peter Stuge 16c8e37a2d agesa_wrapper: Avoid repetitive Kconfig depends, trivial
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6595 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-15 22:40:40 +00:00
Scott Duplichan 8c46263721 Cosmetic cleanup.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6594 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-15 22:10:15 +00:00
Scott Duplichan 5d878ad312 1) Remove unused kconfig options.
2) Correct UMA graphics PCI device ID.

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6593 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-15 22:09:09 +00:00
Scott Duplichan 9ab3c6c3a9 Build device paths for AP cores so that coreboot will report them to the OS.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6581 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-15 21:45:46 +00:00
Scott Duplichan dc312cca53 Move mmconf base from e0000000 to f8000000 to avoid conflict with UMA BAR.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6578 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-15 21:26:04 +00:00
Patrick Georgi 8d6cf3a2d7 Work around unclean CMOS handling for now
Stefan switched away from #ifdef across the tree (and is absolutely right with that), but
unfortunately there are some special cases that trigger in even more special situations.

Revert one such change selectively. It's destined to go once CMOS is reworked.

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6566 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-11 07:44:27 +00:00
Patrick Georgi b251753b4f Change read_option() to a macro that wraps some API uglyness
Simplify
read_option(CMOS_VSTART_foo, CMOS_VLEN_foo, somedefault)
to
read_option(foo, somedefault)

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6565 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-10 21:53:13 +00:00
Stefan Reinauer d4814bd41c more ifdef -> if fixes
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6536 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-21 20:45:45 +00:00
Stefan Reinauer 1d888a9784 some ifdef --> if fixes
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6535 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-21 20:24:43 +00:00
Zheng Bao b18f9b0ff4 The "temp" will be used later. So it has to be calculated correctly.
Comment by Peter,
The variable name "temp" unfortunately does not explain what the value
is. The commit message also does not have hints. Hopefully in the
future it's possible to also use a brief moment to improve the clarity
of the code, while it is already being fixed for some other
reason. Ie. fixing up variable names, writing particularly informative
commit messages, or of course both at the same time! :)

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6517 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-19 06:40:56 +00:00
Stefan Reinauer 432461ec7f cleanup wrong use of defined() after exporting all variables in Kconfig
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6514 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-19 00:36:39 +00:00
Stefan Reinauer 8902502c4a drop incorrectly used CONFIG_ROM_IMAGE_SIZE and unused CONFIG_ARCH
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6496 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-14 20:21:49 +00:00
Alexandru Gagniuc 5005bb06c1 Unify use of post_code
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>                                                                                                         
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6487 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-11 20:17:22 +00:00
Sven Schnelle 148a4f5681 i945: improve get_top_of_ram()
The current version doesn't honor TSEG, and fails to
report the correct top of RAM if IGD is disabled. This
is because it uses the BSM (base of stolen RAM) register.
In that case, we should use the TOLUD register.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6483 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-10 07:41:56 +00:00
Zheng Bao 2ca2f17724 Add AMD C32 support.
It is based on other existing Fam10 code.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6464 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-28 04:29:14 +00:00
Scott Duplichan 314dd0bee5 Enable mahogany_fam10 and Kino family 10h to run the SB HT link at the expected HT3 frequency and width by matching the BUID swap list to the production BIOS. In addition, the BUID swap list has been moved into the project-specific file romstage.c for the other 13 AMD family 10h projects as well. For projects using a desktop AMD family 10h processor, pasting in the mahogany_fam10 swap list will likely allow HT3 operation. This should be confirmed on real hardware before commiting any swap list change. A different swap list will be needed for server projects. For serengeti_cheetah_fam10, a reference BIOS swap list to try is: 0x00, 0x0A, 0x00, 0x06, 0xFF, 0x0A, 0x06, 0xFF.
The patch makes these changes:

1) Remove the BUID swap list from ht_wrapper.c and put it in each of 15
   romstage.c files where it is used (AMD family 10h projects).
2) Add a prototype to amdfam10.h.
3) Modify the swap list and test in real hardware for mahogany_fam10 and
   kino family 10h and confirm HT3 operation for the SB link.

Abuild tested.

Signed-off-by: Scott Duplichan <sc...@notabs.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6439 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-08 23:01:46 +00:00
Patrick Georgi 11ac1cfaa3 Mark non-returning function as noreturn to help some compiler versions
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6418 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-01 07:30:14 +00:00
Xavi Drudis Ferran 6bdc83bf5e Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.

I don't understand what this was doing nor find docs for these regs
Maybe it was left over from some copy & paste ?

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6410 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28 03:56:52 +00:00
Xavi Drudis Ferran c3132105bd Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.

In fact I changed coreDelay before deleting
the code in fidvid that called it. But there're
still a couple of calls from src/northbridge/amd/amdmct/wrappers/mcti_d.c
Since the comment encouraged fixing something, I
parametrized it with the delay time in microseconds
and paranoically tried to avoid an overflow at pathological
moments.

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6408 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28 03:49:28 +00:00