Commit Graph

4358 Commits

Author SHA1 Message Date
Sven Schnelle 20f7f3bf91 pci1x2x: add PCI1510 device IDs
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6525 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-20 08:58:08 +00:00
Sven Schnelle baec0346b0 pci1x2x: use devicetree register configuration
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6524 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-20 08:57:53 +00:00
Stefan Reinauer b297b4901a drop dead uart init code.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6523 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-20 01:08:25 +00:00
Stefan Reinauer 012d867f73 fix boards that still had some uart init remainders
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6522 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-20 01:03:58 +00:00
Stefan Reinauer 13508b94cb Drop baud rate init to an arbitrary baud rate from Super I/O code.
See discussion at                                                                                                                                                               
http://www.mail-archive.com/coreboot@coreboot.org/msg29394.html                                                                                                                 
                                                                                                                                                                                
config->com1, devicetree.cb cleanup and init_uart8250() removal                                                                                                                 
will follow once this patch is comitted                                                                                                                                         
                                                                                                                                                                                
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>                                                                                                                   
Acked-by: Patrick Georgi <patrick@georgi-clan.de>                                                                                                                               

Updated to drop com1, com2.... from config structure and devicetree.cb



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6521 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-19 21:33:40 +00:00
Sven Schnelle 4fff74b69f Lenovo PMH7: add pmh7_touchpad_enable()
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6520 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-19 19:57:26 +00:00
Idwer Vollering 4c50cb2457 Fix compilation of all i82371eb boards when ACPI tables aren't generated
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6518 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-19 19:21:27 +00:00
Zheng Bao b18f9b0ff4 The "temp" will be used later. So it has to be calculated correctly.
Comment by Peter,
The variable name "temp" unfortunately does not explain what the value
is. The commit message also does not have hints. Hopefully in the
future it's possible to also use a brief moment to improve the clarity
of the code, while it is already being fixed for some other
reason. Ie. fixing up variable names, writing particularly informative
commit messages, or of course both at the same time! :)

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6517 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-19 06:40:56 +00:00
Scott Duplichan 52ffb2b66d Recently the 3 projects using the new AMD reference code have been
failing the check for globals (or statics) in romstage. This causes
ASRock E350M1, AMD Inagua, and AMD Persimmon builds to fail with the
message "Do not use global variables in romstage". The message is
working as intended. It is detecting data declared as 'static' when
'static const' was intended. The code executes correctly because it
never tries to modify the data.

To make reference code updates easy, it is probably best to avoid
modifying the AMD provided code if possible. The following change
bypasses the "Do not use global variables in romstage" check for
the AMD reference code only.

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6516 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-19 01:36:24 +00:00
Stefan Reinauer 582748fbb3 Fix some more misuses of ifdef/if defined
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6515 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-19 01:18:54 +00:00
Stefan Reinauer 432461ec7f cleanup wrong use of defined() after exporting all variables in Kconfig
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6514 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-19 00:36:39 +00:00
Stefan Reinauer b3ae1867d1 * Set USBDEBUG_DEFAULT_PORT in all southbridges and use that value
to unify calls to *_enable_usbdebug()
* rename *_enable_usbdebug() to enable_usbdebug()
* move enable_usbdebug() to generic romstage console init code
  and drop it from the individual romstage.c files.

Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Peter Stuge <peter@stuge.se>

 


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6513 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-18 23:51:12 +00:00
Stefan Reinauer 261f842c1c fix copy and paste errors in ne2k.c
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6512 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-18 02:26:56 +00:00
Sven Schnelle ee4c6f7c80 Lenovo H8 EC: add missing systemstatus.asl include
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6510 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-17 14:55:21 +00:00
Sven Schnelle 1b9d2ee6ca PMH7: Add dock event control
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6509 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-17 12:54:32 +00:00
Stefan Reinauer a7163f1eb9 bootblock updates:
- allow CPU to define bootblock code, too.                                                                                                                                                                                                                               
- drop unneeded __PRE_RAM__ define                                                                                                                                                                                                                                       
- move CBFS specific code out of bootblock_common.h into cbfs.h                                                                                                                                                                                                          
                                                                                                                                                                                                                                                                         
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>                                                                                                                                                                                                            
Acked-by: Marc Jones <marcj303@gmail.com>                                                                                                                                                                                                                                



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-16 00:09:53 +00:00
Stefan Reinauer 6aef5542f8 sorry for breaking the tree.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6506 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-15 09:01:42 +00:00
Stefan Reinauer b77a73e40b comment cosmetics in bootblock.ld
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6505 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-15 04:12:03 +00:00
Stefan Reinauer e50952f532 add FILO easy payload option
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6504 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-15 03:34:05 +00:00
Stefan Reinauer d85400d805 Handle drivers/ equally to any other sub directory.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6503 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-15 03:30:03 +00:00
Stefan Reinauer 8345a194ba fix mainboards that were including earlymtrr.c without actually using it.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6502 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-15 00:19:27 +00:00
Stefan Reinauer 24ef134b37 drop half an uart8250 implementation from smiutil and use the common code
for that instead. This also allows using non-uart8250 consoles for smi
debugging.

Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6501 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-14 22:28:00 +00:00
Stefan Reinauer 40e42a824b fix coreboot compilation without serial console enabled.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6500 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-14 21:05:41 +00:00
Stefan Reinauer 23f49a82f9 earlymtrr.c: wipe some dead code, use names instead of numbers and some
cosmetics.

Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6499 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-14 20:39:49 +00:00
Stefan Reinauer 1fdfed1798 add some comments to walkcbfs.S
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6498 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-14 20:33:53 +00:00
Stefan Reinauer 31853d8976 - drop remaining CONFIG_ROM_IMAGE_SIZE
- re-enable .data section check for bootblock.
- rename ldscript_fallback_cbfs.lb to bootblock.ld

Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6497 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-14 20:30:21 +00:00
Stefan Reinauer 8902502c4a drop incorrectly used CONFIG_ROM_IMAGE_SIZE and unused CONFIG_ARCH
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6496 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-14 20:21:49 +00:00
Stefan Reinauer 6108958764 nvidia mcp55: drop unused dbg_info
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6495 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-14 20:11:34 +00:00
Stefan Reinauer 28cd29192b cosmetic cleanup of sis966 usb2 code
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6494 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-14 20:10:27 +00:00
Stefan Reinauer 139e6f9555 Use symbolic names for some MTRR bits instead of numbers in CAR code
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6493 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-14 20:06:30 +00:00
Sven Schnelle 14748a58d9 Lenovo H8 EC: add missing include for thermal.asl
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6491 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-13 09:23:45 +00:00
Sven Schnelle 3e2f6790ed Lenovo H8 EC: Set fancontrol to Automatic management
My Notebook gets far to hot without fan, so just enable automatic
fan control by default.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6490 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-12 18:18:24 +00:00
Sven Schnelle ae08c56d6c PC87384: add GPIO defines
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6489 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-12 18:18:12 +00:00
Marc Jones 484281b90f Use TOM2 for highest sysmem setting for northbound memory routing (DMA). This fixes 4GB memory issues.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Kerry she <kerry.she@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6488 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-12 01:12:46 +00:00
Alexandru Gagniuc 5005bb06c1 Unify use of post_code
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>                                                                                                         
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6487 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-11 20:17:22 +00:00
Sven Schnelle 1fa61ebb33 PMH7: Add chip config
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6486 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-11 19:43:50 +00:00
Sven Schnelle ffcd1439f3 EC: Add Lenovo H8
Move the EC support code from the X60 mainboard to a generic
driver, as this EC is used in many thinkpads. Also move the
ACPI code to this directory for this reason.

This patch also adds a chip config, so that the initial setting
for basic register can be specified in devicetree.cb

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6485 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-11 19:43:32 +00:00
Sven Schnelle 148a4f5681 i945: improve get_top_of_ram()
The current version doesn't honor TSEG, and fails to
report the correct top of RAM if IGD is disabled. This
is because it uses the BSM (base of stolen RAM) register.
In that case, we should use the TOLUD register.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6483 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-10 07:41:56 +00:00
Stefan Reinauer 61aee5f4b1 In 2007 Adrian Reber suggested that we drop ASSEMBLY in favor of __ASSEMBLER__.
http://www.coreboot.org/pipermail/coreboot/2007-September/024665.html

It's about time we follow this advice.

Also move some manually set __PRE_RAM__ defines (ap_romstage.c) to the Makefile and
drop unused CPP define

Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6482 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-10 04:15:23 +00:00
Sven Schnelle df6fd566ba X60: use pnp_write_config() instead of custom function
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6481 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-05 13:00:33 +00:00
Sven Schnelle b31eb3e4a8 X60: move ec version info code to log_ec_version()
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6480 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-05 13:00:14 +00:00
Sven Schnelle bc60833954 X60: assert audio mute before entering Suspend
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6479 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-04 15:19:59 +00:00
Sven Schnelle bdb10594aa X60: log firmware version
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6478 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-04 12:33:54 +00:00
Sven Schnelle 8099cbf764 X60: blink suspend LED during resume
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6477 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-04 10:57:17 +00:00
Sven Schnelle 5fc5a80ce3 X60: we have ACPI_RESUME
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6476 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-04 10:57:06 +00:00
Sven Schnelle 4678914d65 X60: deassert audio mute on boot
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6475 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-04 10:56:52 +00:00
Sven Schnelle b1d5d399f0 remove swp files accidently added
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6474 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-01 07:41:47 +00:00
Sven Schnelle fea6bd1690 X60: add dock code for Ultrabase X6
Move the old docking code from romstage.c to dock.c, and use that code
both in romstage and SMM code.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6473 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-01 07:28:56 +00:00
Sven Schnelle 1aba096789 Add GPIO definitions to PC87392 superio
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6472 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-01 07:28:50 +00:00
Sven Schnelle 8a539b6678 ICH7: Fix register naming error
There's an off-by-one error in the ACPI GP_LVL declaration:
it declares GL00 with a bit count of 6, and continues with GP07
afterwards. This should be GP06, as the first bitfield covers
GP00-GP05.

While at it, change it to GP00-GP05, as right now GL00 isn't used,
and single bitfield are more usable here.

Also adjust the Getac P470, as this is the only user of those defintions
right now.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6471 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-01 07:28:35 +00:00
Sven Schnelle d69438e05e BUILD: add missing config.h dependency
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6467 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-29 09:01:10 +00:00
Zheng Bao 910f4ca5c5 Add support for Supermicro H8scm.
It is AMD C32 + SR5650 + SP5100.
It is created by svn copy amd/tilapia_fam10.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6466 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-28 04:38:14 +00:00
Zheng Bao d3de3eed7b Add the SR5650 & SP5100 to the Kconfig and Makefile.inc
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6465 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-28 04:36:21 +00:00
Zheng Bao 2ca2f17724 Add AMD C32 support.
It is based on other existing Fam10 code.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6464 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-28 04:29:14 +00:00
Zheng Bao c3422235b1 SP5100's code is based on SB700. Change the legacy sb700 of sb7xx_51xx.
Since the SB700 has changed to sb7xx_51xx, change legacy name in
other mainboard.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6463 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-28 03:33:10 +00:00
Zheng Bao 98fcc09cf9 Add AMD SR56x0 support.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6462 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-27 16:39:58 +00:00
Zheng Bao 8a281880a3 This is for board Supermicro H8scm. The code was done by existing chips and
superiotool.

WPCM450 is more like an EC. SuperIO is just a part of multi-features.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6461 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-27 16:33:09 +00:00
Sven Schnelle 0446f9630b X60: Add notification for LID objects
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6458 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-21 14:43:21 +00:00
Sven Schnelle e10699905e X60: remove beep call from _Q26/_Q27
no need to trigger sound, the EC takes care of generating the annoying
AC state beep if enabled in the sound mask.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6457 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-21 14:43:09 +00:00
Marc Jones 4a46e89c75 Fix breaking the build after removing files in tthe previous checkin.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6453 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-17 23:14:24 +00:00
Frank.Vibrans 9c2fb60bfc Perform cleanup and file shrinkage of the AMD AGESA code.
Signed-off-by: Frank.Vibrans <frank.vibrans@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6452 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-17 22:19:45 +00:00
Josef Kellermann ea1c0a714d Fix power_on_after_fail handling on AMD SB600
Bit 0 of pm reg#74 have to be set turn on system after power resumes.
See '42661_sb600_rrg_nda_3.02.pdf' (or '46155_sb600_rrg_pub_3.03.pdf')
for details, look for 'PwrFailShadow'.

[Patrick: I didn't include the get_options reorganization as get_option
doesn't overwrite "on" if power_on_after_fail isn't found in CMOS.
Style changes were also left out.]

Signed-off-by: Josef Kellermann <seppk@arcor.de>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6451 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-17 12:34:15 +00:00
Sven Schnelle 08827287d6 X60: Clear EC events when wake GPE is triggered
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6448 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-15 09:52:17 +00:00
Sven Schnelle f9a0b927f5 ACPI EC: add ec_query function
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6447 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-15 09:52:07 +00:00
Sven Schnelle 07ca1c47b2 X60: LPC bus is LPCB, not LPC
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6446 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-14 15:23:44 +00:00
Sven Schnelle 91c31dac0c X60: fix typo in dsdt.asl
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6445 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-14 14:26:41 +00:00
Sven Schnelle b188a9309d X60: Add _PRW/_PSW methods to LID/SLPB objects
This patch adds the required methods for enabling/disabling
the LID and SLPB objects as wake source. On Thinkpads, the
Fn key can (and is by the Vendor BIOS) programmed as Wake source,
so let's do it the same way.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6444 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-14 13:42:08 +00:00
Sven Schnelle 0238a9caa3 ec/acpi: make ACPI register pair configurable
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6442 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-14 08:18:27 +00:00
Sven Schnelle 8d94d7c4a7 ACPI EC: add ec_set_bit() / ec_clr_bit()
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6441 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-14 08:18:17 +00:00
Scott Duplichan 314dd0bee5 Enable mahogany_fam10 and Kino family 10h to run the SB HT link at the expected HT3 frequency and width by matching the BUID swap list to the production BIOS. In addition, the BUID swap list has been moved into the project-specific file romstage.c for the other 13 AMD family 10h projects as well. For projects using a desktop AMD family 10h processor, pasting in the mahogany_fam10 swap list will likely allow HT3 operation. This should be confirmed on real hardware before commiting any swap list change. A different swap list will be needed for server projects. For serengeti_cheetah_fam10, a reference BIOS swap list to try is: 0x00, 0x0A, 0x00, 0x06, 0xFF, 0x0A, 0x06, 0xFF.
The patch makes these changes:

1) Remove the BUID swap list from ht_wrapper.c and put it in each of 15
   romstage.c files where it is used (AMD family 10h projects).
2) Add a prototype to amdfam10.h.
3) Modify the swap list and test in real hardware for mahogany_fam10 and
   kino family 10h and confirm HT3 operation for the SB link.

Abuild tested.

Signed-off-by: Scott Duplichan <sc...@notabs.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6439 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-08 23:01:46 +00:00
Patrick Georgi 57205c7e43 Add option_table.h as dependency for all C based object files if option tables are used.
This is to make sure that the file exists when it is needed. While this isn't the case for every C source file, it doesn't hurt either to create the file a bit sooner than strictly necessary.

Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6438 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-08 20:49:18 +00:00
Patrick Georgi fab35e3f73 Move cmos.default handling to bootblock
The cmos.default code wasn't actually used so far, due to an oversight
when forward-porting this feature from an old branch.

- Extend walkcbfs' use by factoring out the stage handling into C code.
- New sanitize_cmos() function that looks if CMOS data is invalid and
  cmos.default exists and if so overwrites CMOS with cmos.default data.
- Use sanitize_cmos() in both bootblock implementations.
- Drop the need to reboot after writing CMOS: CMOS wasn't used so far,
  so we can go on without a reboot.
- Remove the restriction that cmos.default only works on CAR boards.
- Always build in cmos.default support on boards that
  USE_OPTION_TABLE.

Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6436 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-08 07:50:43 +00:00
Sven Schnelle 85e666dc37 X60: add thermal zone 1
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-07 09:09:51 +00:00
Sven Schnelle b641e98839 X60: add thermal zone 0
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6434 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-07 09:00:50 +00:00
Jonathan Kollasch 09b36291f7 Add P-states for select Socket 754 processors.
States for AMA3000BEX5AR, SDA3100AIO3BX, and SDA3400AIO3BX
are from AMD document 30430 3.51.  States for ADA3200AIO4BX
derived from SSDT of a MS-7135.  States for TMDML34BKX5LD derived
from legacy PowerNow! table of a MS-7135, and therefore lack accurate
TDP information.

Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6432 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-04 20:01:15 +00:00
Patrick Georgi c9a08ddafd Redo r6099 after copy&pasted code reintroduced DIMMx #defines
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6431 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-04 17:09:21 +00:00
Jonathan Kollasch d5782f3588 Correct off-by-one problem in AMD pre-rev-F model-F PowerNow code.
With this change the last P-state entry of the last CPU in the table
is successfully conveyed into the SSDT.

Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6430 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-03 23:09:43 +00:00
Jonathan Kollasch fadb004359 Improve ck804 IOAPIC and HPET resource handling.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6429 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-03 20:52:50 +00:00
jakllsch a73ffa0a3e Configure PCIe lanes on ms7135 as original BIOS does.
Signed-off-by: <jakllsch@kollasch.net>
Acked-by: <jakllsch@kollasch.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6428 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-03 15:36:08 +00:00
Sven Schnelle 071d835976 add PC87384 SuperIO
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6427 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-03 08:29:03 +00:00
Alexandru Gagniuc 7b9bbeeed8 Fixes licensing of src/southbridge/via/k8t890/k8x8xx.h to GPLv2+ from GPLv3.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6426 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-02 19:56:28 +00:00
Sylvain "ythier" Hitier 82419413b1 Fix some subsystemid statements in r6421
Signed-off-by: Sylvain "ythier" Hitier <sylvain.hitier@gmail.com>
Acked-by: Sven Schnelle <svens@stackframe.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6425 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-01 22:02:37 +00:00
Sven Schnelle b8269e2111 Fix a simple whitespace error in src/include/device/device.h
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>
Reported-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6423 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-01 21:51:29 +00:00
Sven Schnelle 91321028ec Use subsystem id from devicetree.cb instead of Kconfig and move
all boards to the new config scheme.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6421 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-01 19:58:47 +00:00
Sven Schnelle 270a908646 Add subsystemid option to sconfig
Allow user to add 'subsystemid <vendor> <device> [inherit]' to devicetree.cb for
PCI and PCI domain devices.

Example:

	device pci 00.0 on
	       subsystemid dead beef
	end

If the user wants to have this ID inherited to all subdevices/functions,
he can add 'inherit', like in the following example:

	device pci 00.0 on
	       subsystemid dead beef inherit
	end

If the user don't want to inherit a Subsystem for a single device, he can
specify 'subsystemid 0 0' on this particular device.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6420 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-01 19:58:15 +00:00
Patrick Georgi 11ac1cfaa3 Mark non-returning function as noreturn to help some compiler versions
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6418 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-01 07:30:14 +00:00
Sven Schnelle d175f44139 add functions to set Subsystem Vendor/Device to rl5c746
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6412 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28 18:09:58 +00:00
Xavi Drudis Ferran b671172320 Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.

I don't understand what this was doing nor find docs for these regs
Maybe it was left over from some copy & paste ?

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6411 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28 03:59:34 +00:00
Xavi Drudis Ferran 6bdc83bf5e Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.

I don't understand what this was doing nor find docs for these regs
Maybe it was left over from some copy & paste ?

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6410 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28 03:56:52 +00:00
Xavi Drudis Ferran 061c89e15d Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.

I don't understand what this was doing nor find docs for these regs
Maybe it was left over from some copy & paste ?

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6409 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28 03:53:47 +00:00
Xavi Drudis Ferran c3132105bd Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.

In fact I changed coreDelay before deleting
the code in fidvid that called it. But there're
still a couple of calls from src/northbridge/amd/amdmct/wrappers/mcti_d.c
Since the comment encouraged fixing something, I
parametrized it with the delay time in microseconds
and paranoically tried to avoid an overflow at pathological
moments.

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6408 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28 03:49:28 +00:00
Xavi Drudis Ferran 6276b6f151 Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.

bits 13 - 15 of F3xd4 (StutterScrubEn, CacheFlushImmOnAllHalt and MTC1eEn
are reserved for revisions D0 and earlier, so whe should not set them
to 0 in fidvid.c config_clk_power_ctrl_reg0(...), called from prep_fid_change.
For revisions > D0 (when we support them) it is ok not ot clear them,
because they are documented as 0 on reset. bit 12 should be left alone
according to BKDG. Should I set 11:8 ClkRampHystSel to 0 in the mask
too, just to indicate we're touching them ? We'll OR them to 1111 anyway...

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6407 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28 03:35:43 +00:00
Xavi Drudis Ferran 82b241a2b5 Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.

Well, I understand it better like this, but maybe
it's only me, part of the changes are paranoic, and
the only effective change is for a factor depending on
mobile or not that I can't test.

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6406 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28 03:32:23 +00:00
Xavi Drudis Ferran 5bcedee0f8 Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.

Add an untested step in BKDG 2.4.2.8. I don't
have the hardware with Core Performance Boost and
I think it's only available in revision E that does
not even have a constant yet.

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6405 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28 03:25:07 +00:00
Xavi Drudis Ferran ce62350d8f Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.

Add to init_fidvid_stage2 some step
mentioned in BKDG 2.4.2.7 that was missing . Some lines
are dead code now, but may handy if one day we support
revison E CPUs.

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6404 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28 03:19:17 +00:00
Xavi Drudis Ferran e80ce0a134 Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.

Add to init_fidvid_stage2 some step for my CPU (rev C3)
mentioned in BKDG 2.4.2.6 (5) that was missing

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6403 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28 03:12:00 +00:00
Xavi Drudis Ferran 26f97d2cf9 Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.

Looking at BKDG the process for updating
Pstate Nb vid after warn reset seemed
more similar to the codethat was there fo
pvi than the one for svi, so I called the
pvi function passing a pvi/svi flag. I don't
find documentation on why should UpdateSinglePlaneNbVid()
be called in PVI, but since I can't test it,
I leave it as it was.

This patch showed some progress beyond fidvid in my
boar,d but only sometimes, most times it just didn't
work.

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6402 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28 03:08:06 +00:00
Xavi Drudis Ferran 19245c94c8 Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.

Factor out some common expressions.
Add an error message when coreboots hangs waiting for a pstate
that never comes (it happened to me), and throw some
paranoia at it for good mesure.

If I understood BKDG fam10 CPUs never need a software initiated vid transition,
because the hardware knows what to do when you just request
a Pstate change if the cpu is properly configured. In fact
unifying a little what PVI and SVI do was better for my board (SVI).
So I drop transitionVid, which I didn't understand either (why
did it have a case for PVI if it is never called for PVI ?
Why did the PVI case distinguigh cpu or nb when PVI is
theoretically single voltage plane ? ).

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6401 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28 03:02:40 +00:00
Marc Jones 9cbcf1ada4 Kino devicetree.cb SIO PNP devices were not matched up with the
actual SIO. This fixes the serial device  being disabled during PNP
init.

Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Scott Duplichan <scott@notabs.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6400 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28 02:36:15 +00:00
Xavi Drudis Ferran e485aa496b Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.

Contemplate the possibility of nbCofVidUpdate not being
defined, trying to get closer to BKDG

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6399 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28 02:33:59 +00:00
Xavi Drudis Ferran 6fcc961fe8 Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.

Configuration of F3x[84:80] was hardcoded for rev B.
I change that for some code that checks for revision
and configures according to BKDG. Unfinished but
hopefully better than it was.

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6398 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28 00:31:24 +00:00
Xavi Drudis Ferran 1f93fea160 Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.

BKDG says nbSynPtrAdj may also be 6 sometimes.

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6397 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28 00:24:21 +00:00
Xavi Drudis Ferran 0e5d3e16b4 Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.

I didn't understand quite why it did that iwth F3xA0 (Power
Control Misc Register) so I moved Pll Lock time to rules in defaults.h
and reimplemented F3xA0 programming. A later patch will remove
a part I don't know what's mean to do.

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6396 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28 00:18:43 +00:00
Xavi Drudis Ferran adb23a51f5 Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.

Bring F3xD4 (Clock/Power Control Register 0) more in line
with BKDG i more cases. It requires looking at the CPU package type
so I add a function for that (in the wrong place?) and some
new constants

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6395 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28 00:10:37 +00:00
Xavi Drudis Ferran 1f4fffb9cc Prepare for next patches (Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode).

No change of behaviour intended.

Refactor FAM10 fidvid . Factor out the decision whether
to update northbridge frequency and voltage because there
was the same code in 3 places and so we can later modify it
in one place.

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6394 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28 00:00:51 +00:00
Xavi Drudis Ferran f7ef421ead Prepare for next patches (Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode).

No change of behaviour intended.

Refactor FAM10 fidvid . Factor out the decision whether
to update northbridge frequency and voltage because there
was the same code in 3 places and so we can later modify it
in one place.

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6393 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-27 23:58:34 +00:00
Xavi Drudis Ferran d26e5e6bb3 Prepare for next patches (Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode).

No change of behaviour intended.

Refactor FAM10 fidvid. Factor out a little common code.
Also, our earlier  config_clk_power_ctrl_reg0
was still too long and it'd get longer with forthcoming patches.
We now take apart F3xD4[PowerStepUp,PowerStepDown]
to its own function.

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6392 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-27 23:56:00 +00:00
Xavi Drudis Ferran 40f9b4b07e Prepare for next patches (Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode).

No change of behaviour intended.

Refactor FAM10 fidvid . prep_fid_change was already long and it'd
get longer with forthcoming patches. We now take apart F3x[84:80],
ACPI Power State Control Registers, to its own function.

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6391 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-27 23:53:11 +00:00
Xavi Drudis Ferran 1d80e51017 Prepare for next patches (Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode).

No change of behaviour intended.

Refactor FAM10 fidvid . prep_fid_change was already long and it'd
get longer with forthcoming patches. We now take apart F3xDC[NbsynPtrAdj],
Northbridge/core synchronization FIFO pointer adjust, to its own function.

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6390 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-27 23:50:30 +00:00
Xavi Drudis Ferran 9683b1deb2 Prepare for next patches (Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode).

No change of behaviour intended.

Refactor FAM10 fidvid . prep_fid_change was already long and it'd
get longer with forthcoming patches. We now take apart F3xA0,
Power Control Misc Register to its own function.

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6389 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-27 23:47:57 +00:00
Xavi Drudis Ferran a5cbd25e48 Prepare for next patches (Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode).

No change of behaviour intended.

Refactor FAM10 fidvid . prep_fid_change was already long and it'd
get longer with forthcoming patches. We now take apart F3xD4,
Clock Power/Timing Control 0 to its own function.

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6388 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-27 23:45:34 +00:00
Xavi Drudis Ferran d729459621 Prepare for next patches (Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode). No change of behaviour intended.

Refactor FAM10 fidvid . prep_fid_change was already long and it'd
get longer with forthcoming patches. We now take apart VSRamp in step b
of 2.4.1.7 BKDG to its own function.

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6387 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-27 23:42:58 +00:00
Xavi Drudis Ferran 70a3733155 Add 300 MHz and 500 MHz HT frequency limits
Needed to build successfully with Expert mode enabled.

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6386 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-27 02:48:41 +00:00
Xavi Drudis Ferran 4c28a6f018 Make AMD Fam10h CPU microcode updates optional in Expert mode
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6385 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-26 23:29:44 +00:00
Rudolf Marek 837403dddf Following patch fills in the callbacks for PCIe x16 resets. This board uses GPM8,GPM9 as reset toggles.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz> 
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6384 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-26 19:46:08 +00:00
Scott Duplichan 656060d1d9 Correct error in ASRock E350M1 commit that breaks build for ASRock 939a785gmh.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6383 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-26 18:42:04 +00:00
Scott Duplichan 63896e75b4 Add support for the ASRock E350M1, an AMD family 14h Fusion board.
A video option rom must be added for UMA graphics support. It can
be extracted from the supplied UEFI BIOS.

ASRock E350M1 support is based on the AMD persimmon project. The
major differences are SIO model and DIMM SDP addressing. With this
coreboot and seabios, the board can boot DOS from a SATA drive and
can boot WinPE from a USB flash drive. I was unable to get
Windows setup to run.

The board has a socketed SPI flash BIOS chip and a serial port
header. The SIO is Nuvoton NCT5572D. Using coreboot's existing
Winbond w83627hf is a good enough match to get the serial port
and keyboard working.

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6382 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-26 17:49:49 +00:00
Rudolf Marek 199c694f49 It adds support for automatic PSS object generation for AMD pre fam Fh CPU. Those CPUs require a hardcoded table, which I managed to rewrite during one particularly boring flight. Too pity it is only for Opteron CPUs. Someone needs to finish the second PDF for All others Athlons and Semprons.
Also it enables the FID/VID changes in SB. Jakllsch had some troubles with that too but on am2 CPU. Those bits are only documented in SB600. They arent in RRG RPR and BDG.

Signed-off-by: Rudolf Marek <r.marek@asssembler.cz> 
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-26 13:34:01 +00:00
Josef Kellermann ed1d116e62 Add compile-time defaults to some K8 CMOS options in case they're absent in CMOS
This affects the CMOS options iommu, ECC_memory, max_mem_clock,
hw_scrubber, interleave_chip_selects.
If they're absent in cmos.layout, a Kconfig value is used if it exists,
or a hardcoded default otherwise.

[Patrick: I changed the ramstage CMOS handling a bit, and dropped the
reliance of hw_scrubber on ECC RAM, as it has nothing to do with it -
it's the cache that's being scrubbed here.]

Signed-off-by: Josef Kellermann <seppk@arcor.de>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6380 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-24 14:35:42 +00:00
Josef Kellermann 855224bb28 Add new option 'sata_mode' to CMOS and 'SATA_MODE' to Kconfig for AMD SB600
coreboot used to set the chipset to IDE mode unconditionally.
Now, the user has a couple of ways to choose the configuration:
- If a CMOS variable sata_mode exist, it is used to decide if IDE or
  AHCI is to be used as interface.
- If not, a Kconfig option is used.
- If unchanged, the Kconfig option is set to IDE.

So unless the cmos.layout is extended or Kconfig is modified, this won't
change behaviour.

[Patrick: Compared to Josef's version, I changed the Kconfig option to
be boolean, instead of a magic string. Also, the "IDE" default is
handled in Kconfig, instead of an additional line of code.]

Signed-off-by: Josef Kellermann <seppk@arcor.de>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6379 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-24 13:54:10 +00:00
Patrick Georgi 20bd19619e Tyan/s2735 doesn't need to define its own hard_reset function anymore.
The southbridge already provides hard_reset.

Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6378 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-24 07:43:37 +00:00
Scott Duplichan a649a96efe git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6376 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 2011-02-24 05:00:33 +00:00
Sven Schnelle 541269bc85 [i945] Add SPD adress mapping
The current code works only with dual channel if Channel 0 uses SPD address
0x50/0x51, while the second channel has to use 0x52/0x53.

For hardware that uses other addresses (like the ThinkPad X60) this means we
get only one module running instead of both.

This patch adds a second parameter to sdram_initialize, which is an array with
2 * DIMM_SOCKETS members. It should contain the SPD addresses for every single
DIMM socket. If NULL is given as the second parameter, the code uses the old
addressing scheme.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6374 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-21 09:39:17 +00:00
Rudolf Marek 0c8e664713 It turns out that the code which enables specific LDN is somewhat buggy.
Instead of enable the device the device gets disabled. However after some time the serial line gets back, most likely some "enable resources" might fix it. 
I'm attaching patch which somewhat fixes the problem and changes the function to look same in all superio code. Some boards even did not convert the dev->enabled to 0,1 values. 


Signed-off-by: Rudolf Marek <r.marek@assembler.cz> 
Acked-by: Peter Stuge <peter@stuge.se>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6373 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-19 14:51:31 +00:00
Alexandru Gagniuc 650cf237ac Fix build errors introduced in r6367
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6369 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-16 17:40:04 +00:00
Sven Schnelle e8a7df84ad Add ACPI code for Lenvo X60
It currently supports:

- Sleepbutton
- AC state
- Battery state
- Interrupt routing
- Display Brightness control
- Hotkeys

Signed-off-by: Sven Schnelle <svens@stackframe.org>

Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6368 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-16 15:04:59 +00:00
Alexandru Gagniuc 025ead7792 Extended K8T890 driver to include the K8T800 and K8M800 northbridges
The K8T800 is almost identical to the K8T800Pro, also added to this patch.
The K8T800_OLD is also defined, which is an older version of the K8T800,
but which has no driver and early HT code yet. Also extended the K8M890 VGA
driver to work for the K8M800 (not tested). According to the datasheet, the
K8T890 and K8T800 are similar enough to be able to use the same
initialization code. At least for the K8T800, this is sufficient to have
a working HT link with the CPU, and to initialise the V-Link to the
southbridge.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6367 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-16 13:43:00 +00:00
Sven Schnelle ddb3f0adaa Lenovo ThinkPad X60: Enable SMI handler
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6366 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-16 13:12:41 +00:00
Peter Stuge 7afbb9936f Remove more files and lines mistakenly copied from Roda to X60
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6365 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-15 13:07:32 +00:00
Peter Stuge 7d5966deb2 Remove ACPI mistakenly copied from Roda to ThinkPad X60
It is incorrect, and will be replaced with proper ACPI for X60.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6364 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-15 11:14:17 +00:00
Marc Jones 1c427a7a4a Remove Inagua Kconfig items for external VGA and AHCI binaries. These can be addded by the developer if needed.
Fixes abuild issues.

Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6363 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-15 00:27:24 +00:00
Stefan Reinauer dd6c1e67f6 SERIAL_POST was renamed to CONSOLE_POST a while ago
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6362 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-15 00:23:05 +00:00
Sven Schnelle e2ca71efd9 Lenovo ThinkPad X60 / X60s Support
Adds support for Lenovo X60 series ThinkPads. So far, only X60s
(Model 1703) has been tested.

It's a basic patch without SMI and ACPI, as this makes it easier to
review. SMI and ACPI patches will follow.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6360 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-14 20:02:47 +00:00
Josef Kellermann f0ccf6ed18 Errata #169 works on HT, not MC
Signed-off-by: Josef Kellermann <seppk@arcor.de>
Acked-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6355 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-14 19:21:28 +00:00
Josef Kellermann cf37a5942f Removed LPC DMA Deadlock workaround...
Setting bit#21 in k8_f0#68 is part of the errata#169
which is handled in amdk8/coherent.c

Signed-off-by: Josef Kellermann <seppk@arcor.de>
Acked-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6354 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-14 19:19:58 +00:00
Patrick Georgi 144fe88338 Fix Typo. (and why is that file, and some of its siblings per-board?)
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6353 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-14 19:15:36 +00:00
Frank Vibrans 69da1b676c Add IBASE DB-FT1 and AMD Inagua motherboards. Patch 8 of 8.
This code provides support for IBASE Technology DB-FT1 (AMD code name Persimmon) and AMD Inagua platforms. It is dependent on all other patches in this set.

Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6352 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-14 19:04:45 +00:00
Frank Vibrans 7b904d84ba This code provides support for the superio chip on the AMD Inagua platform (not commercially available). It is independent of the AMD>code.
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6351 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-14 19:00:13 +00:00
Frank Vibrans 6b4674e289 I missed a file that was part of the AMD AGESA CPU wrapper checkin, r6347.
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6350 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-14 18:56:10 +00:00
Frank Vibrans d0a8ebf053 This code provides support for the superio chip on the IBASE Technology DB-FT1 (AMD code name Persimmon) platform. It is independent of the AMD code.
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6349 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-14 18:52:15 +00:00
Frank Vibrans 0822ad8b19 This code fixes a number of build issues related to the AMD Agesa code. The particular issues are global variables existing in romstage and the use of GCC intrinsics in the build. The former issue will be addressed shortly, and the latter issue requires community assistance. This code is dependent on the AMD Family 14h mainboard code.
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6348 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-14 18:47:37 +00:00
Frank Vibrans 420faca0d0 Add AMD cpu wrapper code. Patch 4 of 8.
This code provides cpu early initialization for Family 14h cpus. It is dependent on the AMD Agesa code.

Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6347 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-14 18:42:12 +00:00
Frank Vibrans 63e62b03a8 This code provides southbridge initialization for SB800 south bridges. It is dependent on the AMD CIMx/SB800 code.
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6346 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-14 18:38:14 +00:00
Frank Vibrans 39fca80b00 This code provides cpu northbridge initialization for Family 14h cpus. It is dependent on the AMD Agesa code.
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6345 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-14 18:35:15 +00:00
Frank Vibrans 2b4c831b4d Add AMD Agesa and AMD CIMx SB800 code. Patch 1 of 8.
This code currently generates many warnings that are functionally benign.  These are being addressed, but the wheels of bureaucracy turn slowly.  This drop supports AMD cpu families 10h and 14h.  Only Family 14h is used as an example in this set of patches.  Other cpu families are supported by the infrastructure, but their specific support is not included herein.  This patch is functionally independent of the other patches in this set.

Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Marc Jones <marcj303@gmail.com>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6344 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-14 18:30:54 +00:00
Rudolf Marek 74ad66cdc1 Attached patch fixes the LPC decode ranges of SB600/SB800. We enable early only Serial/SIO/RTC.
Everything else needs to be done by lpc.c Problem was that early settings survived, because the lpc.c is doing ORs only...
Hence we decode quite a lot and even strange ranges like IO port 0x4600 etc...

Also, if some port which does not fit to predefined set is requested, like 0x290 for Hardware monitor, the wide port is done, but in our case it has range 512 bytes which means we decode in fact 0x290 - 0x490. And if we hit GPU in the 0x3bx range I receive MCE exception if I do isadump -f 0x300 which is bad.
Therefore If I detect that the requested range is small (16 bytes) I additionally set the small wide io region so only 16 bytes is decoded.

While at it, I fix spelling typos and I init the regs so we don't write random garbage to regs even if we don't enable them later.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz> 
Acked-by: Marc Jones <marcj303@gmail.com>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6343 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-12 16:24:48 +00:00
Scott Duplichan daecb1888e According to AMD documentation, cache type WP should be used for
execution from flash memory. Coreboot uses WB. While there is no
noticeable performance difference between the two settings, use
of WB can cause a problem for a jtag debugger. The attached
patch changes AMD cache as ram setting for flash execution from
WB to WP.

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6342 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-10 20:49:56 +00:00
Josef Kellermannseppk 20ecc5af40 RS690: Provide support for MMCONF.
If enabled, set up 0xe0000000..0xf0000000 as MMCONF
area. Must still be configured in per-board ACPI for
the OS to pick it up, so it's disabled by default.

Signed-off-by: Josef Kellermann<seppk@arcor.de>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6341 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-10 08:49:57 +00:00
Alexandru Gagniuc 1df854248b Implemented workaround for erratum 169, obsoleting erratum 131.
Workaround for 131 removed.
Changed workaround for erratum 110 to only include pre-revision-F
processors.

For details, check AMD publications:
#25759 (Errata for Fam F pre-revision F processors)
#33610 (Errata for Fam F revision F and later processor)

Based on work and previous patches by:
Rudolf Marek <r.marek@assembler.cz> 
Josef Kellermann <seppk@arcor.de>

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6340 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-10 07:51:51 +00:00
Josef Kellermann 31e0deac0e Fix a potential system hang by handling AMD Model F Erratum 89
a bit later.

Signed-off-by: Josef Kellermann <seppk@arcor.de>
Acked-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6339 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-10 07:48:07 +00:00
Alexandru Gagniuc 4a038ca112 Place the W83627EHG MIDI base address mask in the correct position.
Corrects "index 98 has no mask" error at runtime.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6336 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-08 02:36:39 +00:00
Peter Stuge b1d1c4d084 Reliably build arbitrary Kconfig-based revisions of SeaBIOS
Reliability is accomplished by checking out the desired SeaBIOS commitish
into a branch named 'coreboot' in the local SeaBIOS git repository. Using
a branch allows TAG-$(CONFIG_SEABIOS_..) to refer to any commitish in the
SeaBIOS git repo, not just branches and tags.

Configuration is done with make defconfig followed by enabling and
disabling of the relevant coreboot-specific SeaBIOS options by appending
to .config using echo. This works, because later entries in .config will
overwrite earlier ones.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6335 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-07 20:16:40 +00:00
Peter Stuge 1440d0880b Actually add PC87382 into Kconfig, missing from r6332
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6334 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-05 13:32:56 +00:00
Sven Schnelle 82e3617e8c Add PC87392 support
This adds support for the NSC PC87392 Super I/O. It is used in Lenovo
Docking Stations as Super I/O chip.

v2 because of:

- skip some empty files
- missing newlines in Kconfig and Makefile.inc
- add the Kconfig option in sorted order

Thanks to idwer on irc for pointing that out.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6333 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-05 12:26:07 +00:00
Sven Schnelle 92cf08c8f3 Add PC87382 support
This patch adds support for NSC PC87382 Super I/O. It is used in many
Lenovo Notebooks as Docking LPC Switch.

v2 because of:

- Skip some empty files
- Fix newlines in Kconfig and Makefile.inc
- chip.h missed uart8250.h include
- add the Kconfig option in sorted order

Thanks to idwer on irc for pointing that out.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6332 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-05 12:20:23 +00:00
Josef Kellermann a96b218c9c Fix subvendor/subdevice programming on RS690
Some RS690 devices require subvendor/subdevice IDs to
be programmed at locations other than default 0x2c.


Signed-off-by: Josef Kellermann <seppk@arcor.de>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6330 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-03 09:29:57 +00:00
Patrick Georgi 87fcffac82 Wrap CONFIG_MAINBOARD_PCI_SUBSYSTEM_{VENDOR,DEVICE}_ID in weak functions
This is so that boards can determine them on runtime based on hardware
properties, if so desired.


Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Joseph Kellermann <Joseph.Kellermann@heitec.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6329 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-03 09:14:40 +00:00
Uwe Hermann 539500ee33 pmh7.[ch]: Add missing license headers.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6328 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-02 23:56:15 +00:00
Sven Schnelle 6f92d21b12 Properly add Lenovo EC to build
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6326 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-01 19:19:53 +00:00
Sven Schnelle 4a6c9d159c Add support for the Lenovo PMH7 embedded controller
Lenovo PMH7 (Power Management Hardware Hub) is found in
most recent (starting with X60/T60 AFAIK) Lenovo/IBM Laptops.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6325 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-01 10:44:26 +00:00
Stefan Reinauer aeead274a1 Fix an infinite loop in pnp_get_ioresource(), which freezes coreboot if
a rare condition arises.

Based on findings by Alexandru Gagniuc <mr.nuke.me@gmail.com>

Signed-off-by: Stefan Reinauer <reinauer@google.com>

Acked-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6323 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-31 21:16:48 +00:00
Alexandru Gagniuc 38b1f3b772 Add PCI ID's for VIA K8T800 and K8M800 northbridges.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6322 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-31 21:14:02 +00:00
Stefan Reinauer b82673bd23 Build failure because of src/pc80/mc146818rtc_early.c unused variable
Fixes #173
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Acked-by: Stefan Reinauer <reinauer@google.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6321 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-31 21:03:14 +00:00
Patrick Georgi ff9d78c964 Replace special rules for auxiliary files by cbfs-files-y entries
VGABIOS, Intel MBI and the bootsplash image were added with special
build rules. These are replaced by generic cbfs-files-y entries now.

Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6320 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-30 16:37:39 +00:00
Patrick Georgi 5c0bca2ffd Inverse two arguments of cbfs-files-y and adapts its users (one of which already used the new order)
This is in reponse to feedback that the original setup was too complicated.

New cbfs-files-y behaviour:
cbfs-files-y contains the names of files as they appear in CBFS. The
arguments describe the on-filesystem name, the type and (optionally) the
position. Example:

cbfs-files-y += foo
foo-file := bar
foo-type := splashscreen
foo-position := 0xffff8000

This configures a CBFS file called "foo" that is marked "splashscreen",
located at 0xffff8000 in flash and contains the data of the file "bar"
in the filesystem (either in the current directory, ie. where the
corresponding Makefile.inc resides, or if that doesn't exist, relative
to the toplevel directory).


Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6319 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-30 16:31:15 +00:00
Stefan Reinauer e3509fdb68 Pass all required toolchain parts to SeaBIOS correctly
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6317 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-29 05:51:54 +00:00
Rudolf Marek 86bd99aba2 Attached patch fixes the LPC decode ranges of SB700. We enable early only Serial/SIO/RTC. Everything else needs to be done by lpc.c Problem was that early settings survived, because the lpc.c is doing ORs only...
Hence we decode quite a lot and even strange ranges like IO port 0x4600 etc...

Also, if some port which does not fit to predefined set is requested, like 0x290 for Hardware monitor, the wide port is done, but in our case it has range 512 bytes which means we decode in fact 0x290 - 0x490. And if we hit GPU in the 0x3bx range I receive MCE exception if I do isadump -f 0x300 which is bad.
Therefore If I detect that the requested range is small (16 bytes) I additionally set the small wide io region so only 16 bytes is decoded.

While at it, I fix spelling typos and I init the regs so we don't write random garbage to regs even if we don't enable them later.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz> 
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6316 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-28 20:57:48 +00:00
Stefan Reinauer 16ce01b0d8 This patch gets usbdebug console working in romstage.
- actually hook up usbdebug in printk/print_ for romstage
- make usbdebug.c more similar to the Linux kernel version it was
  originally derived from.
- increase retries and timing for usbdebug init (at least one chipset
  seems to need this)
- src/pc80/usbdebug_serial.c is not needed
- some small console cleanups

Signed-off-by: Stefan Reinauer <reinauer@google.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6315 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-28 08:05:54 +00:00
Stefan Reinauer 582d369fbd rename CONFIG_SERIAL_POST to CONFIG_CONSOLE_POST
because that is what it does.

Signed-off-by: Stefan Reinauer <reinauer@google.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>                           



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6311 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-28 07:47:35 +00:00
Stefan Reinauer 1c2734f5b6 Fix Bimini build
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6307 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-28 01:06:39 +00:00
Stefan Reinauer 2c439c3b4e rk886ex lacked EC_ACPI
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6306 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-28 01:03:18 +00:00
Stefan Reinauer f13d7f185b Only add EC code if EC is selected in Kconfig
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6305 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-27 23:56:48 +00:00
Sven Schnelle 7592e8bd9c Add new ec subdir for Embedded Controllers and common ACPI EC support
Adds a new src/ec subdir for embedded controllers (mostly found in laptops)
and converts Getac P470 and Roda RK886EX to use the new ACPI EC instead
of having their own copies of those functions.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6304 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-27 11:43:03 +00:00
Peter Stuge 4096fc5372 SMM code on i945 platforms needs udelay()
smm-y wasn't required before, because udelay.c used to be #included from
various files in src/mainboard.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6303 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-27 11:09:36 +00:00
Patrick Georgi a470019b7a Add a new CMOS variable which triggers activation of the
LPT port. With the CMOS variable set, LPT is found by SeaBIOS,
with the variable reset, it's not.

Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6302 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-27 07:39:38 +00:00
Zheng Bao a5c949eff2 Trivial. Re-indent the code.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6301 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-27 03:31:50 +00:00
Zheng Bao 066cbe0cb7 Set the phy via weak function.
As Rudolf called.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6300 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-27 02:19:55 +00:00
Stefan Reinauer ce952652a1 oops. this is weird. CAR addresses should be specified in the socket and not in
the board. I thought we did this ages ago.

Also push CAR BASE further down so it won't conflict with a 32mbit flash part.

Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6299 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-27 01:11:20 +00:00
Zheng Bao 9dcca3bc3e Set the SB800 SATA PHY correctly.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6297 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-25 06:06:58 +00:00
Josef Kellermann 679d38b7a2 This patch fixes an 'write_tables: coreboot table didn't fit (f0221)' issue.
Signed-off-by: Josef Kellermann <Joseph.Kellermann@heitec.de>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6295 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-24 21:07:57 +00:00
Zheng Bao a302b58d01 Change fadt revision back to 3.
The AcpiPmaCntBlk have to be set.
Further research is needed to find out why.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6293 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-24 07:50:07 +00:00
Patrick Georgi a3eb534f18 ... And fix the other compile time issues in cmos_layout.bin support
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6291 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-21 13:20:10 +00:00
Patrick Georgi f0bf4b5c2a Make YABEL warnings-are-errors safe
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6290 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-21 12:45:37 +00:00
Patrick Georgi 5ccbbd982b Typo. s,CMOS_COMPONENT,CBFS_COMPONENT,.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6289 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-21 11:43:06 +00:00
Zheng Bao 72cc87fba5 Now bimini can boot linux to login.
Note:
1. bimini_fam10/Kconfig: Set GENERATE_MP_TABLE in Kconfig. This will make sure the
   smp_write_config_table will run. Then intr_data will be written
   into 0xC00/0xC01.
2. bootblock: Use PCI_DEV(0, 0x14, 3) instead of
   pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB800_LPC), 0).
   The pci_locate_device will cause the system crash.
3. fadt.c: Change fadt revision to 1. 3 will cause the linux hang. Why?
4. early_setup.c: pmio 0x65 has change its meaning.


Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6288 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-21 08:46:27 +00:00
Stefan Reinauer ba185722d4 push ts5300 rom size to 1MB. In fact the flash part on that
board is 2MB and the entry point is somewhere in the middle. quite weird setup
http://www.embeddedarm.com/products/board-detail.php?product=TS-5300

We should probably wipe the board from the tree. It will not work anyways with
current coreboot and the architecture is kind of obscure.

Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6287 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-21 07:46:32 +00:00
Zheng Bao 8ae82e370b Remove the code for debugging.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6281 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-20 06:28:25 +00:00
Zheng Bao a4da254a39 S3 feanture of SB800. Compiliant with SB700.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6280 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-20 05:59:22 +00:00
Zheng Bao 79c04d559a Move some board specific functions to sb800.h.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6279 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-20 05:41:11 +00:00
Zheng Bao 8210e8972c Features of Bimini board:
RS785
SB800


Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6278 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-20 05:29:37 +00:00
Zheng Bao d098575b0e This sb800 code is derived from sb700.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6277 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-20 04:45:48 +00:00
Zheng Bao dd676ddc54 For Cx, each ChipSel need to be sent MR command.
After this patch, tilapia can run in higher memory frequency.
To test the high frequency, dont forget to change the freq limit in
mcti_d.c:
 static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
 {
	 pDCTstat->PresetmaxFreq = 800;
 }

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6276 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-20 02:09:24 +00:00
Nils Jacobs c29675f332 Add a GX2 Kconfig option to choose the framebuffer size.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6275 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-19 07:25:26 +00:00
Stefan Reinauer 7b0500c24c Revert r5902 to make code more readable again. At least three people like to
have this go away again.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>                                                                          
Acked-by: Kevin O'Connor <kevin@koconnor.net>                                                                          



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6273 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-19 06:54:42 +00:00
Kevin O'Connor 5bb9fd6e4d Now that the VIA code is run above 1Meg (like other boards), it should
cache that range instead of the first 1Meg.  This reduces boot time by
about 1 second on epia-cn.

This patch also adds a MTRRphysMaskValid bit definition.

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6272 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-19 06:32:35 +00:00
Kevin O'Connor 4adc9eb600 The cn700.c code references mainboard_interrupt_handlers() which isn't
defined if VGA_ROM_RUN is off.  Define a dummy implementation of that
function for this case.

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6271 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-19 06:31:24 +00:00
Patrick Georgi cef3b896c1 Report if cmos_layout.bin can't be found when it should.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6269 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-18 14:28:45 +00:00
Patrick Georgi 244793784c Move option table (cmos.layout's binary representation)
to CBFS and adapt coreboot to use it.

Comments by Stefan and Mathias taken into account (except for
the build time failure if the table is missing when it should
exist and the "memory leak" in build_opt_tbl)

Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6268 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-18 13:56:36 +00:00
Zheng Bao a19c622c06 remove the code which is not ready to release.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6264 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-18 09:34:31 +00:00
Zheng Bao 752ab0d785 remove the code which is not ready to release.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6263 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-18 09:32:15 +00:00
Zheng Bao 078efb5a6f remove the code which is not ready to release.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6262 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-18 09:31:29 +00:00
Zheng Bao 10219012f2 remove the code which is not ready to release.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6261 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-18 09:29:19 +00:00
Zheng Bao a7296e74f1 The code is tested on my board with register DIMMs. More tests need to be
done. Please send the testing report.

Note: The pDCTstat->PresetmaxFreq in mctGet_MaxLoadFreq() should be set
to a higher limit, otherwise the frequnce will be set as 400MHz.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Scott Duplichan <scott@notabs.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6258 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-17 02:20:33 +00:00
Rudolf Marek a1125235ec Ooops lets see if this extra comment removal fixes this.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Rudolf Marek <r.marek@assembler.cz>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6257 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-16 17:15:36 +00:00
Rudolf Marek aa55f3768a Trivial, cleanup of GPIO comments.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Rudolf Marek <r.marek@assembler.cz>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6256 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-16 16:23:51 +00:00
Patrick Georgi c3dc8f8ebc Disable CMOS recovery code for ROMCC boards as the CBFS code used for
that feature is not ROMCC compatible.
Fixes build errors introduced in r6253.


Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6255 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-14 08:36:34 +00:00
Patrick Georgi ef3296542a Improved GPIO setup for roda/rk886ex, and some documentation
on what the GPIOs are used for.

Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6254 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-14 07:41:42 +00:00
Patrick Georgi a865b17eff Allow coreboot to initialize CMOS if checksum is invalid.
If a file "cmos.default", type "cmos default"(0xaa) is in CBFS,
a wrong checksum leads to coreboot rewriting the first 128 bytes
(except for clock data) with the data in cmos.default, then
reboots the system so every component of coreboot works with the
same set of values.

Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6253 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-14 07:40:24 +00:00
Patrick Georgi 4c8e269841 Default to CRT on Kontron/986lcd-m. "default display" doesn't always
select the right output device.

Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Joseph Smith <joe@settoplinux.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6252 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-13 11:40:38 +00:00
Patrick Georgi 9144304771 Improve compatibility of YABEL with real-world VGABIOSes
Some of them do weird things to the option rom region (mapping
registers there or so) which failed as we handled these memory
region in emulation. As they were copied back to real memory
after the emulation was done, we can just as well use real
memory directly for these regions.

This affects IVT, BDA, and option ROM space.

Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Joseph Smith <joe@settoplinux.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6251 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-13 11:38:46 +00:00
Stefan Reinauer fb433bea6a drop unused files
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6249 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-12 21:09:25 +00:00
Kerry She 09e0e9a68b change a readable way to fix SB800 CIMX "multi-character constant warning".
by using 'Int32FromChar' macro, instead of the ASCII code.

Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6248 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-11 02:15:57 +00:00
Marc Bertens 965c43b4db Various Nokia IP530 fixes.
- Correct default ROM image size for this board (512KB is correct).

 - devicetree.cb: Add AUX I/O config (mainly GPIO settings).
   This allows you to control the LEDs in the front panel and JP900/JP901
   can be read.

 - irq_tables.c: Rework PIRQ table to make more onboard devices work.
   Also, avoid IRQ9.

 - mainboard.c: Drop unneeded functions, everything is done in devicetree.cb.

Signed-off-by: Marc Bertens <mbertens@xs4all.nl>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6247 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-06 23:03:46 +00:00
Zheng Bao 69436e1a8c Fix some settings fo AMD MCT. It is based on BIOS test suite.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6246 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-06 02:18:12 +00:00
Stefan Reinauer da712f3f45 uart_init is only used in romstage.
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6245 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-05 02:40:53 +00:00
Stefan Reinauer 1b342263f0 move single options out of main menu and remove stray "options"
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6244 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-05 02:27:53 +00:00
Uwe Hermann c7f0c8feab MCP55: Cosmetic fixes, switch to u8 et al.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6241 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-04 19:51:33 +00:00
Uwe Hermann 7e2fbd5dd3 CK804: Cosmetic fixes, switch to u8 et al.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6240 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-04 17:36:55 +00:00
Kerry She ecab12a09e Trivial:
add missed CIMx file to romstage. in order to link them into romstage, move all CIMx table to .rodata section.
 Run dos2unix on Makefile.inc, which is not upstream CIMx code

Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Kerry She <kerry.she@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6239 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-04 06:39:29 +00:00
Kerry She 7917f430b2 Trivial: use the IO_APIC_ADDR constant defined in ioapic.h, and spell check
Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Kerry She <kerry.she@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6238 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-04 06:15:46 +00:00
Uwe Hermann e925965034 src/southbridge/amd/cimx_wrapper: Run dos2unix on the files.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6237 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-01 23:36:03 +00:00
Uwe Hermann d6a1373da2 AMD SB800: Drop component prefix from filenames.
We did the same with other chipsets in r6150.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6236 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-01 23:30:37 +00:00
Uwe Hermann 48b8b92439 AMD Bimini: Use mptable_init() in mptable.c.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6234 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-01 18:58:39 +00:00
Uwe Hermann 26c182340f AMD Bimini: Small fixes, and updates to recent trunk conventions.
- Move CACHE_AS_RAM_ADDRESS_DEBUG #define to Kconfig, where it was renamed
   to HAVE_DEBUG_CAR in r5898.

 - Move QRANK_DIMM_SUPPORT to Kconfig, see r6028.

 - Drop obsolete/unused COMPRESS, see r6145.

 - Drop obsolete SET_NB_CFG_54, see r6086.

 - Move SET_FIDVID/SET_FIDVID_CORE_RANGE to Kconfig, see r6077.
   Actually, the default for SET_FIDVID_CORE_RANGE is 0, so drop it.

 - Rename some GENERATE_* options to HAVE_*, see r6027.

 - Drop "select CACHE_AS_RAM", this is now set in the socket, see r6151.

 - Drop ACPI_SSDTX_NUM, the global default is 0 already.

 - Random whitespace and coding style fixes.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6233 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-01 18:40:02 +00:00
Uwe Hermann f7e7519ff5 AMD Bimini: Drop duplicate ASL files as we did for other boards.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6232 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-01 18:10:07 +00:00
Kerry She ee5fcacba7 Add support for the AMD Bimini eval mainboard.
Signed-off-by: Kerry She <Kerry.she@amd.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6231 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-01 18:04:42 +00:00
Kerry She 84f59aee3c Add AMD SB800 southbridge support via cimx_wrapper.
Signed-off-by: Kerry She <Kerry.she@amd.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6230 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-01 17:52:34 +00:00
Kerry She 799fed98ea Add AMD SB800 southbridge CIMx code.
The main CIMx code is in a src/vendorcode directory and should not be
changed with regard to coding style etc. in order to remain easily syncable
with the "upstream" AMD code.

Signed-off-by: Kerry She <Kerry.she@amd.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6229 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-01 17:44:07 +00:00
Zheng Bao 40992d33b8 Add RS785(RS880) support. Just few pci_ids.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6227 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-31 01:46:12 +00:00
Nils Jacobs 8098e42944 Remove duplicated GX2 processor IIOC mode setting on CS5535 southbridge code
and fix CIS mode comments.

Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6225 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-30 19:23:29 +00:00
Nils Jacobs 8cf54c9f23 Use die() to assure the processor can't wake up from an interrupt.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6224 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-30 19:21:08 +00:00
Stefan Reinauer f1939bb29b Per default, use SeaBIOS payload instead of no payload.
Add choice to use stable or master version of seabios repository

Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6223 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-30 17:39:50 +00:00
Nils Jacobs 84be0f59b7 -Change the remaining GLIU1 port 5 register names from VIP (Video Input Port)
to FG (FooGlue). As the GX2 has no VIP port.
-Change the Memmory setup MSR register names so they correspond better to the
       databook. (Part1)
       This is less confusing for beginners.
-Add a MSR printing function to northbridge.c like in the Geode LX code.
-Remove the AES register names.(GX2 has no AES registers)
-Delete some unused code.
-Clean up GX2 northbridge code  to match Geode LX code.
-Add missing copyright header to northbridge.c.
-Move hardcoded IRQ defining from northbridge.c to irq_tables.c .


Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6221 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-29 21:12:10 +00:00
Stefan Reinauer cdcf9833e8 fix i810 boards with ram init debugging disabled.
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6220 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-29 21:02:50 +00:00
Nils Jacobs ef15ff4de4 -Clean up some comments.
-Remove some white spaces.
-Remove some leading zeros.
-Fix a typo in LX code.

Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6219 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-29 20:31:31 +00:00
Stefan Reinauer fc01e5e3bb proper printk handling in src/northbridge/intel/i82810/raminit.c
and drop some romcc relics in 440bx code too

Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6218 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-27 14:31:05 +00:00
Stefan Reinauer 50e7233689 __PRE_RAM__ is defined by the makefile
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6217 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-27 13:30:39 +00:00
Stefan Reinauer 1c2c75098e dump_spd_registers() is only defined when ram init debugging is on.
Most boards unconditionally call this. Fix it in header file instead of each single romstage.c

Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6216 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-27 13:29:38 +00:00
Stefan Reinauer 3c0bfaf7da Fix most CONFIG_DEBUG_RAM_SETUP issues.
The intel/xe7501devkit is still broken, I think the (romcc) image is too big to
fit in the bootblock if CONFIG_DEBUG_RAM_SETUP is enabled. It would make sense
to convert all CPU_INTEL_SOCKET_MPGA604 to CAR, but I have no hardware to test.

Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6215 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-27 11:34:57 +00:00
Stefan Reinauer acda2fc9ac Intel SCH: make state machine binary selection available in Kconfig for now.
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6214 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-27 08:21:23 +00:00
Stefan Reinauer a35eb2c5e2 All the values should stay untouched or be set automatically by the resource
allocator. If that does not work out, they should be set in the code. Setting
them in Kconfig is the worst possible thing to do.

Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6213 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-26 16:49:57 +00:00
Uwe Hermann 2d1d9cebff Random fixes for TI pci1x2x / Nokia IP530 / others.
- nokia/ip530/devicetree.cb, southbridge/ti/pci1x2x/pci1x2x.c:
   - Fix SMSC FDC37B787 name (was a typo).
   - Disable PS/2 keyboard/mouse LDN, the IP530 doesn't have either.
   - Fix typo: s/PCI_DEVICE_ID_TI_1420/PCI_DEVICE_ID_TI_1520/.
   - All of these are confirmed by Marc Bertens on IRC.
 
 - Fix a few CHIP_NAME HP board names.
 
 - Random whitespace and coding-style fixes.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6212 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-26 14:12:38 +00:00
Nils Jacobs 19d69e3bab Move Geode GX2 UMA video memory size to Kconfig
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6211 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-26 05:24:50 +00:00
Nils Jacobs 642509c965 Remove dead and unused Geode GX2 code
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6210 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-26 05:21:18 +00:00
Nils Jacobs 3344743215 Replace Geode GX2 MSR addresses for GLCP on GLIU1 with names
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6209 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-26 05:16:47 +00:00
Nils Jacobs 1c6d4e6055 Clean up Geode GX2 comments, whitespace and coding style. Trivial.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6208 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-26 05:12:49 +00:00
Uwe Hermann 88929f9bf4 Nokia IP530: Add missing "select SDRAMPWR_4DIMM".
This is needed for all Intel 440BX boards with 4 DIMM slots (such as this one).

Thanks Marc Bertens <mbertens@xs4all.nl> for bringing up the issue and
for the success report for this fix on IRC.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6207 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-25 22:54:41 +00:00
Keith Hui 09f5a7446a Fix build with CONFIG_DEBUG_RAM_SETUP on Intel 440BX, use printk().
It's a good thing to use printk() instead of print_*() anyway
on 440BX (and other chipsets which have been converted to CAR).

Build tested and boot-tested on ASUS P2B-LS.

Signed-off-by: Keith Hui <buurin@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6206 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-23 17:12:03 +00:00
Stefan Reinauer bccbbe6b69 The same mechanisms are used for normal and fallback images.
Hence drop the FALLBACK_ prefix

Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6204 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-19 21:20:14 +00:00
Uwe Hermann a05ddbc46d ASUS M2N-E: Enable PCI-E x16 slot.
Simple devicetree.cb fix, tested on hardware using a PCI-E x16 graphics card.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6203 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-19 01:08:40 +00:00
Rudolf Marek 2c3662710a SMM on AMD K8 Part 2/2
Signed-off-by: Rudolf Marek <r.marek@assembler.cz> 
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6202 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-18 23:30:59 +00:00
Stefan Reinauer cadc545838 SMM for AMD K8 Part 1/2
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6201 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-18 23:29:37 +00:00
Uwe Hermann 405721d45c Fix a few whitespace and coding style issues.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6200 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-18 13:22:37 +00:00
Patrick Georgi a0360af0f1 A couple of Poulsbo fixes:
- Don't include cmc.bin to the build. It's required, but we don't ship it
- mptable's API changes a bit. Adapt.
- Fix ACPI for new iasl versions with improved code validation

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6199 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-18 11:55:06 +00:00
Patrick Georgi be61a17351 Support Intel SCH (Poulsbo) and add iwave/iWRainbowG6 board
which uses it.

Compiles, but not boot tested lately.
Many things missing (eg. SMM support, proper ACPI, ...)

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6198 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-18 07:48:43 +00:00
Uwe Hermann 397ff6815f Remove some more unused/incorrect hda_verb.h files.
As discussed on the mailing list at
http://www.coreboot.org/pipermail/coreboot/2010-December/062393.html
http://www.coreboot.org/pipermail/coreboot/2010-December/062510.html

Someone who owns these boards should create correct files at some point.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6196 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-17 18:04:26 +00:00
Stefan Reinauer 3817494e08 fix the tree again.
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6194 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-17 01:51:34 +00:00
Stefan Reinauer 6559f43dd9 add license headers to some trivial files and pc87427.h
Mostly done according to initial file creator.

Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6192 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-17 00:13:54 +00:00
Stefan Reinauer 85b0fa1ace drop one more version of doing serial uart output differently.
coreboot made it kind of complicated to print a character on serial. Not quite
as complicated as UEFI, but too much for a good design. Fix it.

Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6191 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-17 00:08:21 +00:00
Stefan Reinauer efbfd501fe guard against the case that CONFIG_WAIT_BEFORE_CPUS_INIT is not defined at all.
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6190 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-17 00:03:18 +00:00
Stefan Reinauer 43c1a21733 drop unused code in div64.h
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6189 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-16 23:57:43 +00:00
Stefan Reinauer 0d3e12b51a print what make is doing (CBFS call)
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6188 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-16 23:57:00 +00:00
Stefan Reinauer 5fb62168f6 don't hardcode CONFIG_PC80_SYSTEM
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6187 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-16 23:52:04 +00:00
Stefan Reinauer 8aedcbc436 - Fix shortcoming in Kconfig when handling multiple "choice"s
- move some variables where they belong

Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6186 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-16 23:37:17 +00:00
Stefan Reinauer 259a39f393 fix according to coding guidelines
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6185 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-16 23:24:27 +00:00
Uwe Hermann b9c224e9c5 Add TINY_BOOTBLOCK support for the SiS966 southbridge.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6184 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-16 19:57:54 +00:00
Uwe Hermann c36d506a05 Get mptable OEM/product ID from kconfig variables.
We currently use "COREBOOT" unconditionally as the "OEM ID" in our
mptable.c files, and hardcode the mainboard name in mptable.c like this:

  mptable_init(mc, "DK8-HTX     ", LAPIC_ADDR);

However, the spec says

  "OEM ID: A string that identifies the manufacturer of the system hardware."
  (Table 4-2, page 42)

so "COREBOOT" doesn't match the spec, we should use the hardware vendor name.

Thus, use CONFIG_MAINBOARD_VENDOR which we have already as the "OEM ID"
(truncate/fill it to 8 characters as per spec).

Also, use CONFIG_MAINBOARD_PART_NUMBER (the board name) as "product ID",
and truncate/fill it to 12 characters as per spec, if needed.

Abuild-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6183 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-16 19:51:38 +00:00
Patrick Georgi c2c23dca8b Add support for cbfs-files-y to the build system.
That variable allows chipset components to add files to
the CBFS image, for details see
http://www.coreboot.org/pipermail/coreboot/2010-December/062483.html

Compared to the patch in that mail this commit improves dependency
tracking a bit.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6182 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-16 07:36:28 +00:00
Uwe Hermann 8d0d6718a3 Build fix.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6181 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-15 11:32:11 +00:00
Uwe Hermann 41dc1c0656 Cleanup up HD audio codec / hda_verb.h files.
Most of the current hda_verb.h files are identical (same MD5 sum) and are
intended for a specific MCP55 board with the Realtek ALC880 audio codec,
which has the vendor/device ID of 0x10ec0880. They were splitted out from the
MCP55 southbridge code and put into board dirs a long time ago (which is
correct, as those settings are indeed board-specific), but they were never
adapted to those boards.

Here's the table of which codec is soldered onto which board, based on
checking the vendor website board spec pages, and the board manuals:

 - GIGABYTE GA-M57SLI-S4: Realtek ALC883
 - MSI MS-7260: Realtek ALC883
 - MSI MS-9652: Realtek ALC888
 - MSI MS-9282: Server board, doesn't have audio at all
 - Tyan S2912: Server board, doesn't have audio at all
 - All Supermicro boards: Server boards, don't have audio at all
 - NVIDIA l1_2pvv: No public info to be found, but I assume this was the
   original MCP55 eval board for the port and it's probably has the Realtek
   ALC880 codec used in the original hda_verb.h.

These are the codec vendor device/IDs involved:
Realtek ALC880: 0x10ec0880
Realtek ALC883: 0x10ec0883
Realtek ALC888: 0x10ec0888

The following files are marked as incorrect / TODO, as the ID of the codec
doesn't match and thus will never get actually used (you'll see
"HDA: no verb!" or similar in the coreboot logs). Even if the ID matched,
the rest of the table would be incorrect anyway because the values are
highly board-specific.

./src/mainboard/gigabyte/m57sli/hda_verb.h
./src/mainboard/msi/ms9652_fam10/hda_verb.h
./src/mainboard/msi/ms9282/hda_verb.h

The following files can be safely dropped as these are server boards and
don't have HD audio (or other audio) at all:

./src/mainboard/supermicro/h8dmr/hda_verb.h
./src/mainboard/supermicro/h8qme_fam10/hda_verb.h
./src/mainboard/supermicro/h8dme/hda_verb.h
./src/mainboard/supermicro/h8dmr_fam10/hda_verb.h
./src/mainboard/tyan/s2912/hda_verb.h
./src/mainboard/tyan/s2912_fam10/hda_verb.h

The following two are correct and can stay:

./src/mainboard/nvidia/l1_2pvv/hda_verb.h
./src/mainboard/getac/p470/hda_verb.h

Abuild-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6180 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-15 08:56:19 +00:00
Zheng Bao bb9bceebc1 Set the ROMSIZE as 4MB.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6178 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-14 01:47:18 +00:00
Stefan Reinauer dd6619f5e9 no leading zeroes.
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6177 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-13 22:16:45 +00:00
Rudolf Marek cc1e645248 Attached patch implements the memory speed reductions (and 2T/1T clock logic) for DDR1 memory (939 sockets). The details can be found in BKDG chapter 4.1.3.3.
The patch looks at certain DDR configurations (dual rank/single rank) and lowers the clocks to 2T or frequency as guide suggest. It sets the DualDIMMen bit which I believe should be set for non-dual channel configs.

The patch does not implement support for three dimm configurations supported from revE.
On the other hand it should improve greatly memory stability across the 939 platform.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz> 
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6176 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-13 20:43:33 +00:00
Rudolf Marek 52ff06580d This patch just turns on the ACPI resume.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz> 
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6175 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-13 20:04:25 +00:00
Rudolf Marek 475916ddbf Compile cbmem.c instead of including it in romstage,
and do that only if resume is done.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6174 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-13 20:02:23 +00:00
Rudolf Marek c4369536da Following patch adds support for suspend/resume functions. I had to change the get_cbmem_toc because macro magic did not work well.
The writes to NVRAM are not used in asrock board (k8 pre rev f) but they should work when used with am2 boards. In fact maybe the suspend will work on mahogany or others ;) - with some  simple patch which follows for asrock.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz> 
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6173 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-13 19:59:13 +00:00
Rudolf Marek 59f410fa43 Following patch adds support to bring out the memory out of self refresh when doing resume.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>

The patch is based on my 2008 patch. 
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6172 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-13 19:53:58 +00:00
Rudolf Marek 97be27ebba We hardcode highmemory size in every northbridge! This is bad, and especially if suspend to ram is involved. Let the default be taken from cbmem.h which also handles the suspend logic.
Abuild tested. Please check all changes if I did not make any wrong while converting this to bytes.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz> 
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6171 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-13 19:50:25 +00:00
Uwe Hermann 29c7dfcadc Add support for the ASUS M2N-E board.
This is an AMD K8 + NVIDIA MCP55 + ITE IT8716F mainboard.

It has a working hda_verb.h file for HD audio, and a fanctl.c file is
used to enable the CPU fan (among others) so that we don't kill the
CPU due to excessive heat.

Even though some TODOs remain of course, it works good enough to
successfully boot Linux (e.g. via SeaBIOS).

The full status report is available at:
http://www.coreboot.org/ASUS_M2N-E

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6170 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-13 13:44:33 +00:00
Stefan Reinauer dfeb04d463 fix model 106cx
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6168 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-12 00:37:41 +00:00
Rudolf Marek 4041925039 Fix the build failure. We have now common fadt.c.
[PATCH] SB700 common FADT was not applied to this board because it was in the meanwhile added.


Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Rudolf Marek <r.marek@assembler.cz>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6167 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-11 23:28:17 +00:00
Rudolf Marek e8191b4b2a I was bitten by the rename, this is part of r6165.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz> 
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6166 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-11 22:41:31 +00:00
Rudolf Marek 3310934f32 Following patch makes just one fadt.c file. For SB700.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6165 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-11 22:26:10 +00:00
Stefan Reinauer 2a27b20226 factor out cpu power management base into a separate file. And fix a bug in
model_1067x

Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6164 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-11 22:14:44 +00:00
Stefan Reinauer 2b9070a610 catch some illegal configurations (trivial)
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6163 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-11 22:12:32 +00:00
Stefan Reinauer 8677a23d5b After this has been brought up many times before, rename src/arch/i386 to
src/arch/x86. 

Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6161 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-11 20:33:41 +00:00
Uwe Hermann 198cb96387 Two hda_verb.h files: Add more comments.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6160 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-10 12:52:50 +00:00
Uwe Hermann 6e7efb7cab Add TINY_BOOTBLOCK support for AMD SB700.
Factor out the ROM decode enable functionality into bootblock.c and
handle it via the usual TINY_BOOTBLOCK mechanism.

Use "select TINY_BOOTBLOCK" in the southbridge, not individual boards.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6159 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-10 09:02:50 +00:00
Uwe Hermann 42b1c43c4d Merge enable_rom.c files into bootblock.c files.
All southbridges using TINY_BOOTBLOCK have a bootblock.c files which
simply includes an enable_rom.c files. As discussed on the mailing
list, drop the enable_rom.c file by merging it into bootblock.c.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6158 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-09 18:09:14 +00:00
Uwe Hermann d6ecfdbc84 Build fix, forgot to run abuild on the latest tree.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6157 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-09 13:10:57 +00:00
Uwe Hermann f8ba64d7b7 Deduplicate various ACPI .asl files.
The files debug.asl, globutil.asl, and statdef.asl are duplicated in
many K8/Fam10h boards. However, they're neither board-specific nor
K8/Fam10h-specific nor AMD-specific, so move them to src/arch/i386/acpi.

debug.asl contains generic chunks for I/O port 0x80 handling, and debug
output over serial port (init COM port, send byte, send string, etc).

globutil.asl contains utility methods for string comparison, string length
and similar stuff.

statdef.asl contains generic ACPI bit definitions / status codes from
the ACPI spec (not board- or chipset-specific).

This patch was mostly generated by:

mkdir src/arch/i386/acpi
svn add src/arch/i386/acpi
svn cp src/mainboard/amd/dbm690t/acpi/debug.asl src/arch/i386/acpi/
svn cp src/mainboard/amd/dbm690t/acpi/globutil.asl src/arch/i386/acpi/
svn cp src/mainboard/amd/dbm690t/acpi/statdef.asl src/arch/i386/acpi/
cd src/mainboard
find . -name debug.asl -exec svn rm {} \;
find . -name globutil.asl -exec svn rm {} \;
find . -name statdef.asl -exec svn rm {} \;

Abuild-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6156 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-09 12:39:48 +00:00
Zheng Bao 4a778db86e Add missing instruction break.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6155 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-09 06:18:29 +00:00
Tobias Diedrich abebf5ca92 These empty files sneaked in from another patch and shouldn't have been included in r6153, remove them.
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6154 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-08 21:45:57 +00:00
Tobias Diedrich b672d94ce0 Tobias Diedrich wrote:
> Definitively a iasl problem, it can't even disassemble it's own
> output back to something equivalent to the input file.
> It seems to be generating Bytecode for the Add where it shouldn't.

Here is a solution using the SSDT.

Unfortunately iasl does not resolve simple arithmetic at compile
time, so we can not use Add(DEFAULT_PMBASE, PCNTRL) in the
Processor statement.
This patch instead dynamically generates the processor statement.
I can't use the speedstep generate_cpu_entries() directly since the
cpu doesn't support speedstep.
For now the code is in the southbridge directory, but maybe it
should go into cpu/intel/ somewhere.
IIRC notebook cpus of the era can already have speedstep, so it
would probably be possible to pair the i82371eb with a
speedstep-capable cpu...
Also, I don't know if multiprocessor boards (abit bp6?) would need
to be handled differently.

Abuild-tested.

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6153 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-08 21:40:12 +00:00
Uwe Hermann d351925446 Move "select CACHE_AS_RAM" lines from boards into CPU socket.
All K8/Fam10h boards use CAR, so move the "select CACHE_AS_RAM"
into the socket directories, and remove it from the individual boards.

Do the same for Intel CPUs/sockets where all boards use CAR.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6151 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-08 08:22:04 +00:00
stepan 8301d8348a second round name simplification. drop the <component>_ prefix.
the prefix was introduced in the early v2 tree many years ago
because our old build system "newconfig" could not handle two files with
the same name in different paths like /path/to/usb.c and
/another/path/to/usb.c correctly. Only one of the files would end up
being compiled into the final image.

Since Kconfig (actually since shortly before we switched to Kconfig) we
don't suffer from that problem anymore. So we could drop the sb700_
prefix from all those filenames (or, the <componentname>_ prefix in general)

- makes it easier to fork off a new chipset
- makes it easier to diff against other chipsets
- storing redundant information in filenames seems wrong

Signed-off-by: <stepan@coresystems.de>

Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6150 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-08 07:07:33 +00:00
stepan 836ae29ee3 first round name simplification. drop the <component>_ prefix.
the prefix was introduced in the early v2 tree many years ago
because our old build system "newconfig" could not handle two files with
the same name in different paths like /path/to/usb.c and
/another/path/to/usb.c correctly. Only one of the files would end up
being compiled into the final image.

Since Kconfig (actually since shortly before we switched to Kconfig) we
don't suffer from that problem anymore. So we could drop the sb700_
prefix from all those filenames (or, the <componentname>_ prefix in general)

- makes it easier to fork off a new chipset
- makes it easier to diff against other chipsets
- storing redundant information in filenames seems wrong

Signed-off-by: <stepan@coresystems.de>

Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6149 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-08 05:42:47 +00:00
Myles Watson 1bc5ccac51 Move MMCONF resource into the domain for fam10 for the resource allocator.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Scott Duplichan <scott@notabs.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6148 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-07 19:34:01 +00:00
Uwe Hermann 4028ce7b76 Get rid of some unneeded function prototypes in romstage.c files.
Abuild-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6147 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-07 19:16:07 +00:00
Zheng Bao 7f20d73eba Trivial. Fix typo.
sh> find -name "acpi_tables.c" | xargs sed -i "s/FDAT/FADT/g"

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6146 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-07 06:27:44 +00:00
Uwe Hermann d421c81d72 Drop unused/obsolete CONFIG_COMPRESS from a few board Kconfigs.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6145 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-06 20:27:12 +00:00
Uwe Hermann 0f08c643fa Get rid of some useless/empty *_fixups.c files.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6144 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-06 18:20:48 +00:00
Uwe Hermann 9b9791c29d Winbond W83627HF: Use existing functions instead of open-coding.
Use w83627hf_set_clksel_48() where needed instead or open-coding the same
functionality, and also use w83627hf_enable_serial() instead of 
w83627hf_enable_dev() (which does exactly the same, but isn't wrapped in the
enter/exit config mode functions).

Abuild-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6143 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-06 18:17:01 +00:00
Zheng Bao 29cb06abca Before lane reversal,
De-asserts STRAP_BIF_all_valid for
PCIE-GFX core.
After lane reversal,
Asserts STRAP_BIF_all_valid for
PCIE-GFX core.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: QingPei Wang <wangqingpei@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6142 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-06 08:19:38 +00:00
Juhana Helovuo a8c8490c11 Add initial support for the ASUS M4A78-EM.
Signed-off-by: Juhana Helovuo <juhe@iki.fi>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6141 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-06 01:11:12 +00:00
Uwe Hermann 3a4ed157dc W83627DHG/W83627EHG fixups for virtual LDNs.
W83627DHG:

 - Add proper "virtual LDN" handling for the LDNs that need it (i.e., those
   that don't have their "enable" bit in bit 0 of the 0x30 register).

 - Fix various I/O masks in the pnp_dev_info[] array as per
   datasheet. Add missing PNP_IRQ0 to the W83627DHG_ACPI LDN.

W83627EHG:

 - Similar to W83627DHG, improve the "virtual LDN" setup a bit (it was
   mostly implemented already, though).

 - Add missing PNP_IRQ0 to the W83627EHG_ACPI LDN.

Also: Fix up devicetree.cb of all boards using W83627DHG/W83627EHG to adapt
for the virtual LDNs.

include/device/pnp.h: Add comment that 'function' (which refers to the
LDN and should probably be renamed later) has to be at least 16 bits
wide. In theory LDNs could use u8, but due to the virtual LDN info being
encoded in the "high byte" of 'function' it must be at least u16.

asrock/939a785gmh/romstage.c: Drop unused GPIO6_DEV.

ibase/mb899/romstage.c: Use DUMMY_DEV instead of a specific LDN (serial
port 1 in this case) to avoid confusion. The global registers
manipulated there are accessible from any LDN.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6140 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-05 22:36:14 +00:00
Rudolf Marek 0bafd964b7 Following patch removes the cut-and-paste stuff from Mahagony and fixes the _CRS object to make it work (same code as on M2V-MX SE)
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Marc Jones <marcj303@gmail.com>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6138 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-04 10:08:55 +00:00
Zheng Bao ea62e9b47d More explicite and straight way to set seed.
The read-modify-write wasn't needed. This is easier to understand.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6136 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-02 01:50:38 +00:00
Rudolf Marek 9c9ae3ae8f The patch just make the power LED on.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz> 
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6135 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-30 21:21:33 +00:00
Rudolf Marek f41752c192 Fix the SPD to channel mapping. Please note that there is something wrong with UMA.
Single channel (in slot DDR1 and DDR3) produces strange artefacts on screen (and hang)
Dual Channel (in DDR1 and DDR2 aka blue slot) - works nice
All slots populated - same case as Single channel - must be something wrong with UMA.

Tested with 2x 512MB CAS 2.5 DDR400

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Rudolf Marek <r.marek@assembler.cz>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6134 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-30 20:18:53 +00:00
Zheng Bao 6b8c721e20 Trivial. Reindent and dos2unix.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6133 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-30 02:05:17 +00:00
Tobias Diedrich ca6d8084dd Tobias Diedrich wrote:
> Stefan Reinauer wrote:
> > The specified IO port is most likely wrong. As the comment mentions, the
> > SSDT is a good place for that. A preprocessor define used both in the
> > CPU init code and in the asl would solve the problem without an SSDT.
> > For some info on CPU SSDT creation on intel check out
> > src/cpu/intel/speedstep/acpi.c
> 
> The IO port is ok (and I wrote the comment myself ;)):
> DEFAULT_PMBASE is 0xe400
> PCNTRL reg offset is 0x10
> 
> Using the preprocessor will probably work too if iasl can do simple
> arithmetic (likely yes), I'll look into that.

BTW, my first idea was to use an acpi method that looks up pmbase in
the pci cfg space, but when I define a method like this:

        Method(TEST, 2)
        {
                Return (Add(Arg0, Arg1))
        }

I get:
|build/mainboard/asus/p2b/dsdt.ramstage.asl     9:   Processor (CPU0,
|0x01, TEST(0xe400, 0x10), 0x06) {}
|Error    4096 -       syntax error, unexpected PARSEOP_NAMESEG,
|expecting ')' ^ 

While using the builtin Add() directly works.

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6132 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-29 20:40:33 +00:00
Stefan Reinauer 6fc7d27983 fix typo
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6130 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-29 00:20:20 +00:00
Uwe Hermann d73c50565b devicetree.cb: Only add as many entries as there are DIMM slots.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6129 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-28 14:24:07 +00:00
Tobias Diedrich e87c38e0af After finding the missing bit poweroff works now.
I cleaned up the patch and moved most of the dsdt.dsl and
acpi_tables.c into the southbrige/northbridge directory.
Updated patch should fix abuild error and incorporates suggestions
on irc by uwe (thanks for the comments).
Thanks to Idwer Vollering <vidwer@gmail.com> for the original patch.

Tested:
  Linux (poweroff, powerbutton event)
  XP (poweroff, powerbutton event)

Abuild-tested

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6127 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-27 09:40:16 +00:00
Uwe Hermann 39124dd6c5 Broadcom BCM5785: Add TINY_BOOTBLOCK support.
In bcm5785_enable_rom(): Use PCI IDs from pci_ids.h instead of hardcoding,
and use 'dev' instead of 'addr' as device_t variable name.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6126 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-26 22:42:41 +00:00
Uwe Hermann e89d8a57ac AMD SB600: Add TINY_BOOTBLOCK support.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6125 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-26 22:39:40 +00:00
Uwe Hermann 1f7d3c5672 AMD-8111: Add TINY_BOOTBLOCK support.
Also, add missing license header to amd8111_enable_rom.c, add some more code
comments and use PCI IDs from pci_ids.h instead of hardcoding.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6124 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-26 22:35:11 +00:00
Uwe Hermann df323fcefd MCP55: Add TINY_BOOTBLOCK support.
Also, move CONFIG_HT_CHAIN_END_UNITID_BASE #ifdef block to mcp55.h to make
the build work (but this is a good idea anyway, as it's used in
multiple files).

Abuild-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6123 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-25 09:03:55 +00:00
Tobias Diedrich 48ae6086da S3 support for ASUS M2V
This adds the board-specific parts for S3 support on the M2V board.

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6122 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-24 20:03:09 +00:00
Tobias Diedrich ba9f0b30fb With low serial console loglevels a pcie graphics card is not
initialized properly because the pcie link takes some time to come
up.

I set the timeout rather arbitrary to 100ms, this is what a BIOS_ERR
and higher only boot looks like on my system (with pcie printks set
to BIOS_ERR so they show up):

|Device error
|Device error
|PCI: 00:02.0 PCIe link up after 35800 us
|PCI: 00:03.0 PCIe link up after 12900 us
|PCI: 00:03.1 PCIe link timeout
|PCI: 00:03.2 PCIe link up after 32000 us
|APIC: 00 missing read_resources
|I2C: 01:50 missing read_resources
|I2C: 01:51 missing read_resources
|I2C: 01:52 missing read_resources
|I2C: 01:53 missing read_resources
|Start bios (version pre-0.6.2-20101025_023503-nukunuku)

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6121 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-24 19:57:08 +00:00
Scott Duplichan 88dc531781 This patch solves crashes and BSODs that occur when booting Win7 with
AMD RS780 uma graphics. Tested with frame buffer sizes 64m through 1GB
by running dxdiag and Windows media player at 1600x1200 true color.
Additional changes needed to boot Win7 on Mahogany_fam10 will follow.

-- Enable and program the debug bar as required by the ATI graphics driver.
   First, make the debug bar writable and allow resource allocation code
   to program it. Once programmed, enable its operation.
-- Disable the family 10h processor mmconf while the RS780 mmconf is in use.
-- Make strap programming more closely follow the reference BIOS.
-- Disable PCIe bar 3 after using it.
-- UMA size is no longer hardcoded.
-- Disable write combining for all steppings to eliminate stability problem.
-- Correct task file data.
-- Improve the accuracy of the Atom table that passes information to the driver.

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Rudolf Marek <r.marek@assembler.cz>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6120 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-24 00:39:44 +00:00
Patrick Georgi patrick 612fcc3955 Make smp_write_bus static (local scope), to prevent new boards from
using it directly again.

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6118 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-23 07:19:54 +00:00
Rudolf Marek bcaea142f3 1) wraps the s3 parts of chipset code/memory init code with if CONFIG_HAVE_ACPI_RESUME == 1 getting rid of ugly define in romstage.c
2) the patch implements get_cbmem_toc in chipset specific way if defined.
On Intel targets it should be unchanged. On K8T890 the the cbmem_toc is read from NVRAM. Why you ask? Because we cannot do it as on intel, because the framebuffer might be there making it hard to look for it in memory (and remember we need it so early that everying is uncached)

3) The patch removes hardcoded limits for suspend/resume save area (it was 1MB) on intel. Now it computes right numbers itself.

4) it impelements saving the memory during CAR to reserved range in sane way. First the sysinfo area (CAR data) is copied, then the rest after car is disabled (cached copy is used). I changed bit also the the copy of CAR area is now done uncached for target which I feel is more right.

I think I did not change the Intel suspend/resume behaviour but best would be if someone can test it. Please note this patch was unfinished on my drive since ages and it would be very nice to get it in to prevent bit rotten it again.
Now I feel it is done good way and should not break anything. I did a test with abuild and it seems fine.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz> 
Acked-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6117 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-22 22:00:52 +00:00
Uwe Hermann 9b5295f522 Drop unused ACPI_WRITE_MADT_IOAPIC #define.
This should probably be C code in some .c file anyway.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6116 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-22 16:23:54 +00:00
Uwe Hermann 0d5a6accc8 Drop per-board ram_check() calls for now.
Every board had a slightly different invokation, very often commented out
anyway. We could either decide that this is only to be used by developers
during bringup (and thus added manually to romstage.c and removed before
the board gets committed). This method seems to be preferred from what I
have heard on IRC / mailing list in the past.

Or, we add the ram_check() somewhere globally and allow the user to enable
it via menuconfig (possibly only if EXPERT is selected).

Either way, the current method of spreading the calls all over the place is
not really the way to go.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6115 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-22 15:57:57 +00:00
Patrick Georgi 7411eabcdb Final set of smp_write_bus -> mptable_write_buses changes.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6114 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-22 14:14:56 +00:00
Patrick Georgi 394965dd64 Workaround to get die.c to work with romcc.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6113 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-22 13:07:10 +00:00
Uwe Hermann 6e9ab97106 i855: Remove useless memctrl indirection.
This needlessly complicates the code and increases register pressure on romcc
chipsets. We did the same conversion on i440BX, i830, and others.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6112 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-22 12:59:36 +00:00
Stefan Reinauer abc0c85516 Printing coreboot debug messages on VGA console is pretty much useless, since
initializing VGA happens pretty much as the last thing before starting the
payload. Hence, drop VGA console support, as we did in coreboot v3.

- Drop VGA and BTEXT console support. 
  Console is meant to be debugging only, and by the time graphics comes up
  99% of the risky stuff has already happened. Note: This patch does not remove
  hardware init but only the actual output functionality. 

  The ragexl driver needs some extra love, but that's for another day
- factor out die() and post()
- drop some leftover RAMBASE < 0x100000 checks.

Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: QingPei Wang<wangqingpei@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6111 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-22 08:09:50 +00:00
Uwe Hermann e9c447326a acpi.h: Small fixes and adding comments.
- Mention full name of all the tables (SSDT, FADT, etc).

 - Drop obsolete / incorrect "LXBIOS" reference.

 - Add missing ACPI address space type #defines specified in newer versions:
   ACPI_ADDRESS_SPACE_EC, ACPI_ADDRESS_SPACE_SMBUS.

 - Add missing "enum acpi_apic_types" entries: Localx2Apic, Localx2ApicNMI.
   
 - Add ACPI_FACS_64BIT_WAKE_F #define.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6110 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-22 00:42:42 +00:00
Jonathan Kollasch fae0d6c12b Move CK804_PCI_E_X and CK804B_PCI_E_X defines (which have been 4 by
default on all boards) into Kconfig.

Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6109 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-21 22:55:46 +00:00
Uwe Hermann 7b997053eb Simplify a few code chunks, fix whitespace and indentation.
Also, remove some less useful comments, some dead code / unused functions.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6108 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-21 22:47:22 +00:00
Uwe Hermann 57b2ff886e Drop excessive whitespace randomly sprinkled in romstage.c files.
Also drop some dead or useless code snippets.

Abuild-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6107 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-21 17:29:59 +00:00
Patrick Georgi 5244e1ba63 Convert more boards to use mptable_write_buses.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6106 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-21 14:41:07 +00:00
Patrick Georgi 8cda9699d4 Convert boards to use mptable_write_buses.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6105 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-21 14:40:09 +00:00
Patrick Georgi d8a789f6df Move MCP55_PCI_E_X_* to Kconfig. Any useless values in romstage.cs were
not brought over to Kconfig (this applies to all #defines to 4, as
that's the default anyway)

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6104 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-21 14:38:24 +00:00
Uwe Hermann 6dc92f0d1a Use DIMM0 et al in lots more places instead of hardocding values.
The (0xa << 3) expression equals 0x50, i.e. DIMM0.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6103 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-21 11:36:03 +00:00
Uwe Hermann 86a571797d Build fix.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6102 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-21 10:26:04 +00:00
Uwe Hermann 26535d6e28 Merge all spd_addr.h into the resp. romstage.c files.
Except for one instance the spd_addr.h were now very tiny, there's not
much point in keeping that stuff in an extra file. The only user of those
files is the romstage.c file anyway.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6101 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-20 20:36:40 +00:00
Uwe Hermann d773fd370a Some more DIMM0 related cleanups and deduplication.
- VIA VT8235: Do the shift in smbus_read_byte() as all other chipsets do.

 - spd.h: Move RC00-RC63 #defines here, they were duplicated in lots of
   romstage.c files and lots of spd_addr.h files. Don't even bother for
   those spd_addr.h which aren't even actually used, drop them right away.

 - Replace various 0x50 hardcoded numbers with DIMM0, 0x51 with DIMM1,
   and 0xa0 with (DIMM0 << 1) where appropriate.

 - Various debug.c files: Replace SMBUS_MEM_DEVICE_START with DIMM0,
   SMBUS_MEM_DEVICE_END with DIMM7, and drop useless SMBUS_MEM_DEVICE_INC.

 - VIA VX800: Drop unused SMBUS_ADDR_CH* #defines.

 - VIA VT8623: Do the shift in smbus_read_byte() as all other chipsets do.
   Then, replace 0xa0 (which now becomes 0x50) with DIMM0.

 - alix1c/romstage.c, alix2d/romstage.c: Adapt to recent bit shift changes.

 - Various files: Drop DIMM_SPD_BASE and/or replace it with DIMM0.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6100 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-20 20:23:08 +00:00
Patrick Georgi 9bd9a90d6a Unify DIMM SPD addressing. For Geode, change the
addressing scheme to match the rest of the tree
(0x50 instead of 0xa0).

abuild tested.

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-20 10:31:00 +00:00
Uwe Hermann 622824cadb Cosmetic fixes and comment additions in acpi.c.
- Fix whitespace, coding style, and indentation in some places.

 - Add comments for less obvious entries and hardcoded numbers (e.g. 'type').

 - Add comments for all/most 'revision' fields, mention in which version
   of the ACPI spec which revision number is to be used.

 - Add URLs to a few external documents which describe tables that are
   not mentioned in the ACPI spec (or where the external document may
   provide further info), e.g. SRAT, SLIT, HPET, MCFG, etc.

 - Use the ASLC #define instead of hardcoding "CORE" in one instance
   (ASLC is already used everywhere else).

 - Add some TODOs for additional stuff which is in the spec but not yet
   handled by our code / #defines.

Abuild-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6098 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-19 15:14:42 +00:00
Uwe Hermann 607614d0a9 Fix/drop some obsolete comments,
- s/Options.lb/devicetree.cb/
 
 - s/Config.lb/devicetree.cb/

 - s/cache_as_ram_auto.c/romstage.c/
 
 - h8dmr_fam10/README: Drop obsolete comment, we have mc_patch_01000086.h in
   the tree now.
 
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6095 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-18 20:12:13 +00:00
Uwe Hermann 24f324cb85 Drop unused and incorrect RTC_DEV for Winbond W83627EHG.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6094 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-18 19:40:33 +00:00
Patrick Georgi 8c107bc9e4 Move DIMM_MAP_LOGICAL to Kconfig.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-18 11:36:16 +00:00
Patrick Georgi 9e180387bd Move register block definitions out of board code into
chipset code (where it belongs)

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6088 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-18 10:48:15 +00:00
Patrick Georgi d4917692ec For completeness sake: License header.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6087 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-18 00:46:53 +00:00
Patrick Georgi d28c2986d6 Eliminate SET_NB_CFG_54 option. There was no board that
deselected it, and very likely there won't ever be any
hardware that requires it deselected.

Keep the "selected" code path around, leading to no
functional change.

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Scott Duplichan <scott@notabs.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6086 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-18 00:11:32 +00:00
Patrick Georgi 361bd10bce Move Intel power management related defines to some central location.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6085 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-17 21:52:15 +00:00
Tobias Diedrich 0fe6e9a9a4 Dynamically generate PNP0C02 mainboard resources in SSDT
Updated patch with improved comments and small bugfix (use same
value for min and max on io resource).

While adding the area between TOM1 and 4GB to \SB.PCI0._CRS seems to be the
easiest way to get both Linux and Windows happy, it is not quite correct
because reserved areas like APIC, MMCONF etc. ranges need to be excluded.

This is a proof of concept patch for the M2V board that dynamically creates a
ResourceTemplate() containing these in the SSDT and adds a corresponding
PNP0C02 device to the DSDT.

All resources that have IORESOURCE_RESERVE and (IORESOURCE_MEM or IORESOURCE_IO) set
are added.

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>

Added M2V-MX SE too.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Rudolf Marek <r.marek@assembler.cz>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6084 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-17 16:27:06 +00:00
Tobias Diedrich 8520e01af7 Linux also needs the MMCONF area to be reserved either in E820 or
as an ACPI motherboard resource or it will not enable MMCONFIG
and the extended pcie configuration area will be unaccessible:

This patch adds the IORESOURCE_RESERVE flag to the APIC and MMCONF
resource flags to do this.
I also added a new resource for the mapped bios rom area just below 4GB.
I'm not sure if the choice for the index parameter of new_resource()
is correct though.
Note that the bios rom decode is enabled in
src/southbridge/via/vt8237r/vt8237r_early_smbus.c
for the whole 4MB area (even though the comment says 1MB).

Ruik: I extended the flash range to 16MB (This is what VT8237S can decode)
Remove the MMCONFIG region reserve in the mainboard file (this patch makes it obsolete)

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz> 




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6083 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-17 11:30:50 +00:00
Tobias Diedrich e0c0a82954 This problem was introduced with
http://tracker.coreboot.org/trac/coreboot/changeset/3953

Note that all corresponding DSDTs only ever check TOM2 against 0.

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6082 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-17 11:02:05 +00:00
Tobias Diedrich 8a71dcd321 The only southbridge having a pirq_assign_irqs function (needed for
CONFIG_PIRQ_ROUTE) so far is the amd cs5530.
Add one for vt8237 too.
Setting up the pci routing is important in case you want to boot DOS,
OSes that don't support ACPI or MP tables and ROMs for add-in storage
controllers may depend on this too.
TODO: Fix the 4 routing links limitation in
      src/arch/i386/boot/pirq_routing.c

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6081 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-17 10:58:13 +00:00
Uwe Hermann 2b6e93bd7a Drop W83627THF, it's the same device as W83627THG.
The only difference is that the "G" version is in a Pb-free package, which
is not relevant from a programmer's view.

We keep W83627THG (and drop W83627THF) because:

 - The W83627THF had a CIR device / LDN which doesn't actually exist.

 - The W83627THF had no GPIO2, GPIO3 LDNs (were commented out).

 - The W83627THF didn't use the PNP_MSC0/1 which is needed/used by boards.

This also fixes an issue on MSI MS7135's devicetree.cb:

  device pnp 4e.6 off end           # XXX keep allocator happy

The line above can be (and is) removed, as it was only needed due to the
incorrect CIR LDN in the W83627THF.

In the iwill/dk8x target: Drop incorrect LDNs 4 and 6, add 0xb.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6080 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-16 23:15:37 +00:00
Patrick Georgi 3226cf8b9c Drop commented out debug defines
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6079 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-16 22:15:09 +00:00
Patrick Georgi 5876d06b96 Forgot to remove one set of SET_FIDVID defines
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6078 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-16 22:10:55 +00:00
Patrick Georgi 76e8152c39 Move the SET_FIDVID* family of configuration options to Kconfig and
make their defaults more obvious.

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6077 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-16 21:25:29 +00:00
Stefan Reinauer 0f02daf19b back out parts of #6073
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6076 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-16 00:41:17 +00:00
Stefan Reinauer 20c3d77d98 fix random breakage
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6075 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-15 21:09:57 +00:00
Patrick Georgi c2bf26d247 Move RCBA defines to northbridge (instead of mainboard)
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6074 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-15 19:44:42 +00:00
Uwe Hermann a69d978be8 C and other Super I/O cosmetic fixes.
- Random coding style, whitespace and cosmetic fixes.
 
 - Consistently use the same spacing and 4-hexdigit port number format
   in the pnp_dev_info[] arrays.
 
 - Drop dead/unused code and less useful comments.
 
 - Add missing "(C)" characters and copyright years.
 
 - Shorten and simplify some code snippets.
 
 - Use u8/u16/etc. everywhere.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6073 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-15 19:35:14 +00:00
Uwe Hermann 2e9323e5be Add a target for the ASUS A8V-E Deluxe (trivial).
For now this is a plain copy of the ASUS A8V-E SE target, I reported
that most of the code also works (sort of) for the ASUS A8V-E Deluxe
a long while ago, see

  http://www.coreboot.org/pipermail/coreboot/2008-March/031866.html
  http://www.coreboot.org/ASUS_A8V-E_Deluxe

There will be a bunch of changes necessary though (devicetree.cb, mptable.c,
ACPI, etc) which do not apply to the A8V-E SE, so we need an extra target.

Also: Increase ID_SECTION_OFFSET on the VIA K8T890/K8M890 southbridge, as
otherwise there will be build errors if the MAINBOARD_PART_NUMBER string
gets too long (as is the case for "A8V-E Deluxe"). The error is:

  ld: section .id loaded at [00000000ffffffd2,00000000ffffffef] overlaps
  section .romstrap loaded at [00000000ffffff80,00000000ffffffd3]

(both with stock Debian gcc and with xgcc)

Increase ID_SECTION_OFFSET (default 0x10) to 0x80 as other southbridges do.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6072 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-14 21:48:14 +00:00
Uwe Hermann 0675d5c34f CK804/MCP55 devicetree.cb cosmetic and indentation fixes.
Add a few more comments for the entries, and also change the devicetree.cb
files to the more compact and better readable variant with indentation level
of 2 spaces (instead of random mix of tabs and spaces).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6071 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-14 20:10:11 +00:00
Rudolf Marek 727edb0b32 Return 0, (as for 40pin cable if SB not found)
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Rudolf Marek <r.marek@assembler.cz>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6070 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-14 14:39:29 +00:00
Tobias Diedrich 5d72eb5e8e Move cable detect logic to a weak function in vt8237r_ide.c and add
an override function in m2v/mainboard.c

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6069 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-14 14:17:29 +00:00
Tobias Diedrich d441afda91 Currently the
cablesel |= (sb->ide0_80pin_cable << 28) |
                    (sb->ide0_80pin_cable << 20) |
                    (sb->ide1_80pin_cable << 12) |
                    (sb->ide1_80pin_cable << 4);
in vt8237r_ide.c ends up doing
	cablesel |= 0xfffffff0;
(with both bits set to 1) which is probably not the intended result. ;)

After a short discussion on irc the consensus was to change the
bitfields to u8 as it's probably not worth it using bitfields here.

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6068 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-14 14:12:14 +00:00
Scott Duplichan f3cce2f3c4 MTRR related improvements for AMD family 10h and family 0Fh systems
-- When building for UMA, reduce the limit for DRAM below 4GB
   from E0000000 to C0000000. This is needed to accomodate the
   UMA frame buffer.
-- Correct problem where msr C0010010 bits 21 and 22 (MtrrTom2En
   and Tom2ForceMemTypeWB) are not set consistently across cores.
-- Enable TOM2 only if DRAM is present above 4GB.
-- Use AMD Tom2ForceMemTypeWB feature to avoid the need for 
   variable MTRR ranges above 4GB.
-- Add above4gb flag argument to function x86_setup_var_mtrrs. Clearing
   this flag causes x86_setup_var_mtrrs() to omit MTRR ranges for
   DRAM above 4GB. AMD systems use this option to conserve MTRRs.
-- Northbridge.c change to deduct UMA memory from DRAM size reported
   by ram_resource. This corrects a problem where mtrr.c generates an
   unexpected variable MTRR range.
-- Correct problem causing build failure when CONFIG_GFXUMA=1 and
   CONFIG_VAR_MTRR_HOLE=0.
-- Reserve the UMA DRAM range for AMD K8 as is already done for AMD
   family 10h.
Tested with mahogany on ECS A780G-GM with 2GB and 4GB.
Tested with mahogany_fam10 on ECS A780G-GM with 2GB and 4GB.
 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6067 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-13 19:07:59 +00:00
Tobias Diedrich 5960fb3dbd mainboard/asus/m2v: Set DDR2 voltage to 1.8V
The power-on default is 1.95V, set the DDR2 voltage to
standards-conforming 1.8V.

I also measured with a multimeter to confirm this.

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6066 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-12 20:46:02 +00:00
Jonathan Kollasch ab940df331 Add support for Fintek F71872 superio.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6064 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-11 22:25:55 +00:00
Uwe Hermann 5330dd9174 Remove superfluous Super I/O res0/res1 lines.
The pc_keyboard_init() function no longer takes any base addresses
since r5152 (passed in via res0/res1 variables previously), so drop them.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6063 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-11 13:14:55 +00:00
Tobias Diedrich 1dcd26cddc Add VT8237A id to src/southbridge/via/vt8237r/bootblock.c
I missed this one since it was working anyway, since
"The LPC BIOS ROM is always accessed when ISA addresses
 FFF80000-FFFFFFFF and 000F0000-000FFFFF are decoded" (VT8237R datasheet)
And the rom I use for testing is smaller than this 512KB default range.

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6062 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-11 05:12:01 +00:00
Tobias Diedrich e080bcabd0 Add pci id and ops for VT8237A SATA controller
Needed to change class from raid to ide so seabios can boot from it.

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6061 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-11 05:08:33 +00:00
Tobias Diedrich 5f00e0c800 Use the new mptable_write_buses() on the ASUS M2V.
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6060 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-10 22:09:42 +00:00
Tobias Diedrich ca033311f9 Add mptable for ASUS M2V.
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6059 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-10 19:08:52 +00:00
Uwe Hermann d1a1d57adc Restructure i3100 Super I/O driver to match the rest of the codebase.
- i3100_early_serial.c:

    - Split out enter/exit functions as the other Super I/Os do.

    - Make i3100_enable_serial() take a device_t as usual, and convert
      it to use the standard pnp_* function instead of open-coding
      the same functionality by hand.

    - Factor out i3100_configure_uart_clk() from i3100_enable_serial(),
      we do the same in various other Super I/Os, e.g. ITE ones.

 - Add some #defines for register / bit values and some comments.

 - Only functional change: Don't set bit 1 of SIW_CONFIGURATION, it's
   marked as "READ ONLY, WRITES IGNORED" in the datasheet.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6058 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-10 18:22:11 +00:00
Uwe Hermann 340fa9396b Random Winbond Super I/O cosmetic and coding-style fixes.
- Whitespace, coding style, and typo fixes.

 - Drop unused/obsolete "#config chip.h".

 - Use u8/u16/etc. everywhere.

 - Use pnp_read_config()/pnp_write_config() instead of open-coding them.

 - Use pnp_set_logical_device() instead of open-coding it.

 - W83627EHG: Fix incorrect enable_hwm_smbus() code comment.

 - Use ARRAY_SIZE.

 - w83627hf/superio.c: w83627hf_16_bit_addr_qual(): Bugfix, the code was using
   'dev->path.pnp.port >> 8' as config port, which is incorrect in superio.c
   (which has a "real" device_t struct, in contrast to *_early_serial.c which
   uses "unsigned" as device_t where 'dev >> 8' is required).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6057 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-10 14:53:36 +00:00
Peter Stuge 02d66fd1bf Make amdk8 printk_raminit() accept just a single string parameter
The function is called with no format specifiers in the first parameter
throughout the code, so it needs to work also with just one parameter.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6056 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-10 02:12:05 +00:00
Peter Stuge 5015f79857 Ensure that config options hidden by r6054 have defaults, and fix MALLOCDBG()
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6055 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-10 02:00:32 +00:00
Uwe Hermann a953f371dd Debugging facility improvements.
- Hook up malloc() debug code via CONFIG_DEBUG_MALLOC. Only show it in
   menuconfig if at least DEBUG or SPEW are selected as loglevel, as this
   code does additional printk(BIOS_DEBUG, ...) calls which would otherwise
   not be visible anyway.

 - Similarly, make DEBUG_CAR and REALMODE_DEBUG only visible if thr DEBUG or
   SPEW loglevel is selected.

 - Get rid of a custom "debug" macro, use printk() as usual.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6054 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-10 00:14:32 +00:00
Uwe Hermann f228a6cf93 ITE IT8661F changes to match the common code structure.
- it8661f_enable_serial() is now in the usual format, using pnp_* functions.
 
 - Factor out pnp_enter_ext_func_mode()/pnp_exit_ext_func_mode().
 
 - Factor out it8661f_set_clkin() to set the CLKIN to 24/48MHz.
 
 - Factor out it8661f_enable_logical_devices(), might not be needed though.
   We leave it here until it's confirmed on hardware that it's not needed.

 - Move some #defines to it8661f.h.

 - Drop no longer used it8661f_sio_write().

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-10 00:08:42 +00:00
Tobias Diedrich c29246739a This fixes a FIXME in src/cpu/amd/mtrr/amd_mtrr.c and shuts up the
Linux kernel, which was previously complaining that the MTRR setup
is wrong, if the cpu supports more than CONFIG_CPU_ADDR_BITS bits of
address space.

Shamelessly copied from Linux arch/x86/kernel/cpu/mtrr/main.c

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Scott Duplichan <scott@notabs.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-09 22:31:11 +00:00
Tobias Diedrich 8b3cac2a6c Add acpi tables and dsdt.
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6051 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-09 22:18:28 +00:00
Tobias Diedrich 6222fe0443 Add pirq table for ASUS M2V.
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6050 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-09 22:11:00 +00:00
Uwe Hermann 7fa0819ecf Add #include guards to all Super I/O header files (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6049 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-08 20:55:24 +00:00
Ward Vandewege f648d619c9 We can't print this early.
This patch fixes a hang on

  supermicro/h8dme
  supermicro/h8dmr
  supermicro/h8dmr_fam10

and possibly on other mcp55-based boards.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6048 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-08 17:41:43 +00:00
Uwe Hermann 5c6bae213e Random ITE Super I/O fixes.
- Drop some of the less useful / outdated / duplicated comments.

 - Simplify and streamline some code to look like the other Super I/Os.

 - Use u8/16/etc. everywhere.

 - ITE IT8718F: Add missing GPIO LDN.
 
 - Add missing braces around SIO_DATA #defines, potential bug even.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6047 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-08 15:16:30 +00:00
Scott Duplichan 6018e1ba7f DSDT.asl should not report the AMD SB600/SB700 RTC as Intel PIIX4
compatible. The extended cmos is accessed differently for AMD
and Intel RTCs. Not sure what if any OS cares about this distinction,
but non-Intel compatible seems like a safer way to report the AMD RTC.
Tested with Win7 on Mahogany_fam10 and kino-780am2-fam10.

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6046 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-07 20:11:39 +00:00
Tobias Diedrich 4e6305f4ab Should be part of 6044. I forgot to add the directory :/
This adds the m2v directory and necessary files to src/mainboards/asus and
adjusts the Kconfig.

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6045 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-07 20:08:45 +00:00
Tobias Diedrich 4a6dfebf39 This adds the m2v directory and necessary files to src/mainboards/asus and
adjusts the Kconfig.

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6044 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-07 19:27:45 +00:00
Tobias Diedrich a151f27cb0 Depends on the "Introduce get_vt8237_lpc() function" and
"Use get_vt8237_lpc() in vt8237_sb_enable_fid_vid()" patches.

This adds VT8237A specific VLINK/LPC init in vt8237r_early_smbus.c
I ran some tests and apparently both the

|			/* So the chip knows we are on AMD. */
|			pci_write_config8(devctl, 0x7c, 0x7f);

and

|	/*
|	 * Allow SLP# signal to assert LDTSTOP_L.
|	 * Will work for C3 and for FID/VID change.
|	 */
|	outb(0x1, VT8237R_ACPI_IO_BASE + 0x11);

in vt8237r_early_smbus.c are needed on VT8237A, otherwise I get a (non-fatal)
fid/vid change error on boot.

While vt8237a_vlink_init() in vt8237_ctrl.c is a modified vt8237r_vlink_init(),
vt8237a_init() in vt8237r_lpc.c is a modified vt8237s_init().

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6043 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-07 19:17:18 +00:00
Tobias Diedrich 7714cd0515 This adds the VT8237A LPC pci_locate_device call in vt8237r_early_smbus.c
Depends on the "Introduce get_vt8237_lpc() function" patch.

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6042 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-07 18:57:10 +00:00
Tobias Diedrich e165d41b08 Use get_vt8237_lpc() in vt8237_sb_enable_fid_vid() too.
I broke this out into a seperate part to keep the other half as
straight-forward as possible.

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6041 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-07 18:51:13 +00:00
Tobias Diedrich ef2928e708 Instead of duplicating the pci_locate_device calls multiple times,
add a get_vt8237_lpc() function.

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>

Acked-by: Rudolf Marek <r.marek@assembler.cz>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6040 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-07 18:46:13 +00:00
Tobias Diedrich 6953eeb342 Add pointer to public PCIe bridge documentation on
http://linux.via.com.tw/ as VX800 seems to be compatible.

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6039 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-07 18:37:39 +00:00
Tobias Diedrich 113b29f3c1 This adds VT8237A specific VLINK/LPC init functions in vt8237_ctrl.c
and vt8237r_lpc.c.

While vt8237a_vlink_init() in vt8237_ctrl.c is a modified vt8237r_vlink_init(),
vt8237a_init() in vt8237r_lpc.c is a modified vt8237s_init().

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6038 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-07 18:28:34 +00:00
Rudolf Marek b9e16dffd3 Remove empty files added by accident. Sorry about that.
Rudolf

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Rudolf Marek <r.marek@assembler.cz>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6037 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-07 18:25:11 +00:00
Patrick Georgi 7bbd7f2318 Move K8_ALLOCATE_IO_RANGE to Kconfig.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6036 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-07 18:20:51 +00:00
Tobias Diedrich 2210135468 This adds the VT8237A LPC device id and the pci_driver struct in
vt8237r_lpc.c

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6035 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-07 18:20:32 +00:00
Patrick Georgi 9fb2e3ab76 FIRST_CPU, SECOND_CPU, TOTAL_CPUS are only used in one
other place, and that defines these symbols itself (and
identical, too). Drop them.

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6034 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-07 17:49:05 +00:00
Uwe Hermann 168acf9bb6 Fix a few incorrect GIGABYTE board names (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6033 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-07 17:47:01 +00:00
Uwe Hermann fbd85a13ae ECS P6IWP-Fe: Fix typo, add missing license header.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6032 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-07 16:49:31 +00:00
Patrick Georgi 68854f3cc9 Remove unused defines (UART_*)
All other uses of these symbols have their own (identical)
definitions.

abuild-tested and trivial

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6031 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-07 08:15:13 +00:00
Uwe Hermann 8c02368e2d Various Super I/O fixes and corrections.
- VIA VT1211:
   - Add missing LDNs and respective code to handle them.
   - Add some TODOs for other stuff that needs fixing.
   - Use VT1211_SP1 instead of hardcoding the LDN number (2).
   - Fixup pnp_dev_info[] as per datasheet, but some TODOs remain.
   - Various coding style fixes and changes to u8/u16/etc.
 
 - Serverengines Pilot: Various coding style fixes and changes to u8/u16/etc.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6030 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-06 23:36:49 +00:00
Uwe Hermann 9915944b18 Remove comments that are obsolete since r6028.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6029 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-06 00:57:19 +00:00
Patrick Georgi 00e1460a83 Move QRANK_DIMM_SUPPORT to Kconfig, removing it from romstage.c
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6028 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-05 22:59:49 +00:00
Uwe Hermann d51122df4e Various PIRQ/MPTABLE/ACPI Kconfig fixes.
- Use HAVE_ACPI_TABLES, HAVE_MP_TABLE, and HAVE_PIRQ_TABLE (instead of
   GENERATE_*) in the board's Kconfig file, as all other boards do.

 - Add missing HAVE_ACPI_TABLES/HAVE_MP_TABLE/HAVE_PIRQ_TABLE to boards
   which have the respective files. The only exception: EPIA-M700 doesn't
   select ACPI, as it doesn't have dsdt.asl. Added a comment that the user
   is supposed to run the 'get_dsdt' script and edit Kconfig afterwards.

 - Fix minor warning/error in
   src/mainboard/msi/ms9652_fam10/acpi_tables.c,
   now that the file is actually used.

 - msi/ms9652_fam10: use #include instead of Include() as we usually do
   now.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6027 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-05 16:17:46 +00:00
Uwe Hermann adc975098d Follow-up for r6025, do 0x87 twice in superio.c, too.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6026 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-05 12:44:25 +00:00
Zheng Bao 27770c93d4 According to the description in datasheet of f71889,
"To enable configuration, the entry key 0x87 must be written to
the index port"

"
 -o 4e 87
 -o 4e 87	(enable configuration)
 -o 4e aa	(disable configuration)
"
This piece of text appears in most of the datasheet of fintek superio.
It doesnt say it quite clear, but it seems that the 0x87 should
be written twice. I tried on f81865, which is not in the coreboot tree
yet. If the 0x87 is only written once, you can only R/W the index/data
port once. All the subsequent RW will fail. Writing twice will be ok.

Plus, in the superiotool, the function enter_conf_mode_winbond_fintek_ite_8787
also write 8787.

The fintek superio chips seem to enable the UART automatically when the
power is on. So I didnt find it failed to access.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6025 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-05 07:59:06 +00:00
Nils Jacobs eca32808cb Add Kconfig CPU speed selection to Geode GX2 boards.
This is Abuild and boot tested.

Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6023 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-05 00:23:11 +00:00
Nils Jacobs f29b3b68c8 GX2: Define the unused DIMM1 to 0xFF to make it obvious it is a bogus value.
This is Abuild and boot tested.

Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6022 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-05 00:19:21 +00:00
Nils Jacobs a1e2c56079 Remove banner wrapper function and unify print(k) usage.
- Drop banner(), use printk()s instead.

 - Uncomment a few printk()s, if a users doesn't want to see them he/she
   can lower the debug level.

 - Replace print_emerg() with printk(BIOS_EMERG) etc.

Also change 'Assymetirc' into 'Asymmetric', thanks to Idwer for spotting.

This is Abuild and boot tested.

Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6021 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-05 00:13:14 +00:00
Uwe Hermann 7d3418849d Fintek and Intel i3100 Super I/O cleanups.
- Drop commented out "config chip.h" and a duplicate link to a datasheet.

 - F71805F -> F71805F/FG, to mention all variants.
 
 - Use u8/u16/ etc. everywhere.
 
 - Add a missing (C) line.
 
 - Fix up a bunch of pnp_dev_info[] structs according to the datasheets.
 
 - Fintek F71889: Drop res1/PNP_IO1 from KBC, there's no 0x62/0x63 register
   pair on this Super I/O.
   
 - Fintek F71863FG: This Super I/O _does_ have a keyboard/mouse LDN, add the
   respective code in superio.c. Also: Add missing LDNs to f71863fg.h.
   
 - i3100: Add some more comments and datasheet infos.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6020 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-05 00:07:13 +00:00
Uwe Hermann e4870474b9 Various cosmetic and coding style fixes in src/devices.
Also:

 - Improve a few code comments, fix typos, etc.

 - Change a few more variable types to u8/u16/u32 etc.

 - Make some very long lines fit into 80chars/line.

 - Drop a huge duplicated comment, use "@see" to refer to the other one.

 - Reduce nesting level a bit by restructuring some code chunks.

 - s/Config.lb/devicetree.cb/ in a few places.

Abuild-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6019 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-04 23:23:47 +00:00
Uwe Hermann 305e8861d6 Add a rom_enable() function to via/vt8231 and call it from via/epia/romstage.c
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6018 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-04 18:33:42 +00:00
Alec Ari 0ae7131f2e Add Fintek F71889 Super I/O support.
Untested, but should work mostly (even though some TODOs remain).

Signed-off-by: Alec Ari <neotheuser@ymail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6017 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-03 21:46:41 +00:00
Nils Jacobs a215b0f0be Remove some unused code from gx2/raminit.c.
This is Abuild and boot tested.

Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6016 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-03 13:24:29 +00:00
Nils Jacobs e98db798c9 Clean up some more comments and white space in model_gx2/cpureginit.c.
This is Abuild and boot tested.

Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6015 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-03 13:21:41 +00:00
Nils Jacobs 5beac7f996 Clean up some comments and white space in gx2/northbridgeinit.c
and gx2/raminit.c.

This is Abuild and boot tested.

Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6014 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-03 13:19:50 +00:00
Tobias Diedrich b54585244b Need to clear downstream read cycle retry bit, or the bus scan will
hang.  Also need to set lane config to 0x00 for autonegotiation.

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6013 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-02 21:24:29 +00:00
Tobias Diedrich d50b43a128 This adds pci device ids and pci_driver structs for the K8T890 CF
variant. It also adds additional dev_find_device calls in k8t890_ctrl.c for
subfunctions 3 and 7.

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6012 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-02 20:54:37 +00:00
Nils Jacobs 76890dde14 Change Geode GX2 to use the auto DRAM detect code from Geode LX.
Also, change the GX2 boards to use it.

Add a processor speed setting function in human readable MHz and remove
the useless and broken PLLMSR settings (the processor speed was hardcoded
to 366MHz in pll_reset.c).

Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6011 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-01 15:20:27 +00:00
Nils Jacobs 9644623934 Remove some unused code.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6010 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-01 14:39:49 +00:00
Nils Jacobs 809e29ec8f GX2: Clean up some white space and comments.
Also, add a copyright header to pll_reset.c.

Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6009 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-01 14:36:54 +00:00
Nils Jacobs fc9fcf7414 GX2: Change MSR register numbers into more descriptive names.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6008 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-01 14:18:11 +00:00
Uwe Hermann e5b60bcf04 Remove definitions of ACPI_SSDTX_NUM to 0, that's the default anyway.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6007 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-31 23:24:18 +00:00
Uwe Hermann f9892166d5 Remove incorrect IOAPIC lines from some mptable.c files.
- via/epia-n/mptable.c
 - intel/eagleheights/mptable.c (commented out anyway)
 - asus/p2b-d/mptable.c
 - asus/p2b-ds/mptable.c

Some files still incorrectly contain some smp_write_ioapic() lines from
the original mptable utility target (Supermicro P4DPE), which has one
IOAPIC in the southbridge (Intel ICH3-S), two IOAPICs contained in
the first P64H2, and two more in the second P64H2, i.e. 5 IOAPICs in total.

However, none of the boards where this chunk of code is present has
multiple IOAPICs (and even if they had, the PCI devices where those are
located would probably be different anyway), so drop the incorrect
mptable.c contents.

Also drop the lines from the mptable utility, so that future mptable.c files
don't incorrectly inherit any of this stuff.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6006 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-31 19:37:50 +00:00
Scott Duplichan 27612ed4f2 Fix AMD family 10h engineering sample is reported as 'thermal test kit'.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6005 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-31 14:17:51 +00:00
Uwe Hermann da22d2190d Mptable related fixes for ASUS P2B-DS.
- Add "select IOAPIC" in the board's Kconfig file.

 - Set CONFIG_MAX_PHYSICAL_CPUS to 2 on the board. There are two
   CPU sockets (Slot 1) and each CPU can only have one core, multi-core CPUs
   didn't exist in that era (CONFIG_MAX_CPUS was set to 2 already).

 - Drop useless/duplicated enable_lapic() call from ASUS P2B-DS's romstage.c,
   that function is always called if either CONFIG_SMP and/or CONFIG_IOAPIC
   are set.

 - Rework ASUS P2B-DS mptable.c to fix a number of things:

   - Convert it to use mptable_write_buses() as all mptable.c files should do.

   - Fix incorrect IOAPICID (it's 0x11 for the external 82093AA IOAPIC).

   - Fix a bunch of hardcoded bus IDs, remove incorrect entries, etc.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6004 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-30 21:27:13 +00:00
Jonathan Kollasch dca8b1b599 Use common code to set PCI subsystem in mcp55.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6003 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-29 20:40:06 +00:00
Jonathan Kollasch c7f3f80cf0 Deduplicate ck804 subsystem-setting functionality.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6002 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-29 15:56:04 +00:00
Uwe Hermann bb42300f03 Drop duplicate HAVE_ACPI_TABLES (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6001 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-29 14:26:27 +00:00
Jonathan Kollasch d23f275aa1 The no point in having a non-NULL ops_pci pointer when the set_subsystem operation within is NULL anyway.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6000 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-28 19:57:52 +00:00
Uwe Hermann b34ff66a7a Fix broken build due to missing #if CONFIG_IOAPIC.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5999 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-28 14:22:20 +00:00
Uwe Hermann 77180546c8 Add IOAPIC support for Intel 82371EB and fixup SMP on ASUS P2B-D.
- Add enable_intel_82093aa_ioapic() which enables IOAPIC usage in the
   Intel 82371EB southbridge (sets the proper chip-select) and sets an
   IOAPIC ID.

 - We only call enable_intel_82093aa_ioapic() if a board does "select IOAPIC"
   as on 82371EB-based boards the IOAPIC is an external chip (not integrated
   in the southbridge) and it's only populated on multi-CPU boards.
   That is, we cannot unconditionally enable it, only on SMP-capable boards.

 - Due to the reason explained above, remove "select IOAPIC" from
   src/southbridge/intel/i82371eb/Kconfig, and add it to
   src/mainboard/asus/p2b-d/Kconfig.

 - Also set CONFIG_MAX_PHYSICAL_CPUS to 2 on ASUS P2B-D. There are two
   CPU sockets (Slot 1) and each CPU can only have one core, multi-core CPUs
   didn't exist in that era (CONFIG_MAX_CPUS was set to 2 already).

 - Drop useless/duplicated enable_lapic() call from ASUS P2B-D's romstage.c,
   that function is always called if either CONFIG_SMP and/or CONFIG_IOAPIC
   are set.

 - Rework ASUS P2B-D mptable.c to fix a number of things:

   - Convert it to use mptable_write_buses() as all mptable.c files should do.

   - Fix incorrect IOAPICID (it's 0x11 for the external 82093AA IOAPIC).

   - Fix a bunch of hardcoded bus IDs, remove incorrect entries, etc.

This is build-tested on ASUS P2B-D, and also boot-tested successfully there.
On Linux I now get two entries in /proc/cpuinfo (where only one appeared
before this patch), i.e. both populated CPUs are found.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-28 08:19:22 +00:00
Jonathan Kollasch 706b350be8 Enable CK804 AC'97 audio interface and explicitly enable NIC on A8N-E.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5997 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-27 20:32:49 +00:00
Jonathan Kollasch 5433a83832 Correct an apparent copy-paste error that shows up at compile time on
boards using ck804_early_setup.c that select CK804_USE_NIC.

Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5996 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-27 20:30:32 +00:00
Jonathan Kollasch 2585d2db24 Drop referenced-yet-does-nothing static function from ms7135 romstage.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5995 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-27 17:41:40 +00:00
Jonathan Kollasch d8bed0a4c1 Convert ck804_early_smbus.c to a separately compiled unit.
Additionally, make the second SMBus more accessible in romstage.

Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se> 


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5994 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-27 17:26:57 +00:00
Uwe Hermann b69cb5a310 Convert some comments to proper Doxygen syntax.
Also, make them all fit in 80chars/column, fix some whitespace issues
and also some typos I noticed.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5993 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-26 22:46:43 +00:00
Tobias Diedrich b907d321a5 We need to call smp_write_lintsrc() instead of smp_write_intsrc() for
local ints. This is wrong in most coreboot mptables, probably all
generated by util/mptable/mptable.c.

After fixing this now XP can boot in MPS mode on my M2V.

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5992 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-26 22:40:16 +00:00
Jonathan Kollasch 4a8d9938b2 Convert all ck804-based boards to tiny bootblock.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5991 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-26 16:10:20 +00:00
Patrick Georgi 9d4212fff2 Move bcm5785_enable_rom.c include to where it's used.
Right now, it breaks the build of bootblock enabled boards
with that chipset.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5990 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-26 15:51:57 +00:00
Patrick Georgi f3e8542cc4 reg is only used inside the #if clause, so declare it there. trivial.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5989 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-26 15:11:45 +00:00
Scott Duplichan 45057d2753 When gcc 4.5.0 is used, compiling mcp55_early_setup_car.c fails. This change eliminates the compiler warning that causes the build to fail.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5988 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-26 05:26:01 +00:00
Uwe Hermann 55dc223ccd Factor out common mptable code to mptable_init().
- Drop sig[], oem[], and productid[] fields in all mptable.c files, no
   longer needed. The sig[] is always the same ("PCMP"), the oem[] is
   currently also always the same ("COREBOOT"), and productid is being
   passed into mptable_init() directly as string now.

 - LAPIC_ADDR is passed in as parameter, too. While at the moment it's
   always the same value that is passed in, the LAPIC base address could
   also be relocated theoretically, so keep it as parameter for now.

 - Fix a few productid entries, they were (partially) incorrect:

   - DK8S2 (was "DK8X", copypaste)
   - 939A785GMH (was "MAHOGANY", copypaste)
   - X6DHE-G (was "X6DHE", incomplete board name)
   - H8DME-2 (was "H8DMR", copypaste)
   - H8QME-2+ (was "H8QME", incomplete board name)
   - X6DHE-G2 (was "X6DHE", incomplete board name)
   - X6DHR-iG2 (was "X6DHR-iG", incomplete board name)
   - GA-M57SLI-S4 (was "M57SLI", incomplete board name)
   - KINO-780AM2 (was "KINO", incomplete board name)
   - DL145 G1 (was "DL145G1", small fix as per vendor website)
   - DL145 G3 (was "TREX", wrong board name)
   - DL165 G6 (was "HP DL165 G6", drop vendor)
   - S2912 (was "S2895", copypaste)
   - VT8454c (was "VIA VT8454C", drop vendor, lower-case "c")
   - EPIA-N (was "P4DPE", copypaste)
   - pc2500e (was "PC2500", incorrect name)
   - S1850 (was "S2850", copy-paste)
   - MS-7135 (was "MS7135")
   - MS-9282 (was "MS9282")
   - MS-9185 (was "MS9185")
   - MS-9652 (was "K9ND MS-9652")
   - Ultra 40 (was "ultra40")
   - E326 (was "E325", copypaste)
   - M4A785-M (was "TILAPIA", copypaste)
   - P2B-D (was "ASUS P2B-D", drop vendor)
   - P2B-DS (was "ASUS P2B-DS", drop vendor)

 - Adapt the mptable utility to use mptable_init() too.

Abuild-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5987 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-25 15:32:07 +00:00
Scott Duplichan 7c1fb7b798 Running a checked build of Windows is needed for understanding its various BIOS related BSODs. Win7 checked build complains when running coreboot+seabios:
FADT revision inconsistent with length.
     Revision:        0x1
     Length:          0xf4
     Expected Length: 0x74

Change the FADT revision from 1 to 3 to match its length and prevent the Windows checked build assert.

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5985 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-24 16:22:11 +00:00
Uwe Hermann 1c009276f1 Revert sblk/sblink change, use sblk like the rest of the codebase does.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5978 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-20 20:21:27 +00:00
Myles Watson fa78d998d5 Now that no boards set RAMBASE < 1M, get rid of some dead code. Trivial.
It's probably time to reconsider moving all fam10 boards to RAMBASE = 1M.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5977 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-20 19:23:22 +00:00
Scott Duplichan bda153be73 For AMD family 10h processors, msr c0010058 is always programmed
for 256 buses, even if fewer are configured. This patch lets msr
c0010058 programming use the configured bus count, CONFIG_MMCONF_BUS_NUMBER.

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5976 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-19 21:08:11 +00:00
Jonathan Kollasch 115e66018a Drop duplicate SB_HT_CHAIN_ON_BUS0 in Kconfig for MS-7135.
Trivial.

Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5975 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-19 15:25:06 +00:00
Jonathan Kollasch 6f566b7a60 Use the correct (W83627THF, not W83627HF) superio code in MS-7135 romstage.
This is consistent with the device tree and the chip actually on the board.
Trivial.

Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5974 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-19 15:17:18 +00:00
Jonathan Kollasch 4e6f4cfa9c Copy ICH4 hard_reset() for 6300ESB.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5973 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-19 14:02:10 +00:00
Jonathan Kollasch 7b8700b502 Remove unused variables from 6300ESB smbus_write_block().
#ifdef DEADCODE out smbus_write_byte() and smbus_write_block() as
they are static and nothing uses them or are incompletely implemented.

Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5972 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-19 13:49:11 +00:00
Jonathan Kollasch 9fe5069584 Correct spelling of "spacing" (in comments).
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5971 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-19 13:39:38 +00:00
Jonathan Kollasch d208c1aa2c Use mptable_write_buses().
Remove unhelpful comment.

Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5970 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-19 13:11:56 +00:00
Jonathan Kollasch 6b0ade7550 Modernize socket_754 Kconfig with CAR and address bits information.
Also, update the board that uses this socket to match.

Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5969 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-19 13:03:34 +00:00
Scott Duplichan 1ba2eee2b4 Revision 5966 changed the end of line style of the 3 modified files. This change restores the original end of line style.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Scott Duplichan <scott@notabs.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5968 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-19 04:58:49 +00:00
Scott Duplichan 236aef238f To reduce boot time, remove the double startup IPI and 10 ms delay from lapic_cpu_init.c. The change is
currently restricted to recent model AMD processors, though it could be applied to others after successful testing.

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Myles Watson <mylesgw@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-19 04:36:42 +00:00
Scott Duplichan af786b618d When debug logging is enabled, a message such as '* AP 02 timed out:02010501'
is sometimes logged. The reason is that the AP first sets a completion value
such as 0x13, which is what function wait_cpu_state() is waiting for. Then a
short time later, the AP calls function init_fidvid_ap(). This function sets
a completion value of 01. When logging is off, wait_cpu_state is fast enough
to see the initial completion value for each of the APs. But with logging
enabled, one or more APs may go on to complete function init_fidvid_ap, which
sets the completion value to 01. While mostly harmless, the timeout does
increase boot time. This patch eliminates the timeout by making function
wait_cpu_state recognize 01 as an additional valid AP completion value.

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5966 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-19 04:26:17 +00:00
Scott Duplichan d7acdfb44a This patch enables SB700 option PrefetchEnSPIFromHost in early setup.
It affects only systems booting from SPI flash, not those booting from
LPC flash. By default, the SB700 reads dwords from the SPI flash chip.
Setting PrefetchEnSPIFromHost causes the SB700 to read entire cache
lines from the flash chip. 

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5965 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-18 04:01:12 +00:00
Stefan Reinauer c104cb0d9d update intel microcode files.
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-18 00:21:39 +00:00
Uwe Hermann 321ebe0953 Make update-microcodes.sh executable.
This also has an additional benefit:

I was running "sh update-microcodes.sh" previously which broke with

  update-microcodes.sh: 102: Bad substitution

due to the script requiring /bin/bash instead of /bin/sh (uses bash-specific
stuff). Running "bash update-microcodes.sh" works fine.

Making the script executable in svn reduces the likelyhood of people
running the script with differing shells that may not work.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5963 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-18 00:20:40 +00:00
Uwe Hermann d453dd0c4d Cosmetics and coding style fixes in devices/*.
- Whitespace and indentation fixes in various places.
 
 - Fix various typos.
 
 - Use u8, u16 etc. everywhere.

Abuild-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5962 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-18 00:00:57 +00:00
Stefan Reinauer a600a3f700 update intel microcode update script
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5961 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-17 23:55:17 +00:00
Keith Hui a14b117269 Removes model_65x CPUIDs from model_6xx code.
They now have their own home at cpu/intel/model_65x.

Signed-off-by: Keith Hui <buurin@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5960 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-17 22:07:08 +00:00
Liu Tao 676d0298a1 In the RS780/RS690 ProgK8TempMmioBase() function, the dst-link field is set
to zero, so for boards with RS780 not on CPU's HT chain 0, the function will
mis-configure the MMIO dst-link routing, and the following enable_pcie_bar3()
function will hang when it visits the MMIO.

The following patch fixes the problem, and is tested on a K8 board with RS780
on HT chain 1.

Signed-off-by: Liu Tao <liutao1980@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5959 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-17 21:59:43 +00:00
Liu Tao dfecd2740b We currently read the CPU HT speed from HT chain 0's register.
Fix that to read the register from the chain where the SB chip is on.

Signed-off-by: Liu Tao <liutao1980@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5958 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-17 21:34:45 +00:00
Uwe Hermann c6a106286b Add more missing GPL-headers, fix inconsistencies in others.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5957 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-17 19:30:58 +00:00
Uwe Hermann 8af6d5574b Use common GPL-header format in CK804 files, add missing ones (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5956 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-17 19:13:18 +00:00
Uwe Hermann c1ee429135 Various Doxygen comment fixes, typo fixes, etc.
- Fix incorrect argument names for @param entries.

 - Add missing @param and @return entries, partly as TODOs.

 - s/@returns/@return/, that's a typo.
 
 - Small whitespace fixes while I'm at it.
 
 - Drop useless @brief commands, they just clutter the comments and make them
   harder to read. Doxygen has an option to always use the first sentence
   of a Doxygen-comment as @brief automatically (should be on per default).
   
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5955 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-17 19:01:48 +00:00
Keith Hui b14fb6abd6 Move support for Deschutes Slot 1 CPUs (model_65x) into its own directory.
abuild-tested. I have no Deschutes CPUs to boot test this with.

Signed-off-by: Keith Hui <buurin@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5954 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-16 08:45:31 +00:00
Uwe Hermann af8b2b91b4 Drop unused DCACHE_RAM_BASE from intel/car/cache_as_ram.inc-using sockets.
This CAR implementation hardcodes the Cache-as-RAM base address to:

  0xd0000 - CacheSize

so the DCACHE_RAM_BASE is never actually used for this implementation
and these sockets.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5953 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-15 07:47:51 +00:00
Uwe Hermann e49903650c Cosmetics in ioapic.c (trivial, no functional changes).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5952 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-14 23:40:10 +00:00
Uwe Hermann 212d0a2eae Remove various .c #includes from Intel i810/i82801ax/i82801bx boards.
This is pretty much the same mechanism as in r5929.

 - Use 'romstage-y' to turn i82801ax_early_smbus.c and i82801bx_early_smbus.c
   into distinct compilation units, and don't #include the files anymore
   in romstage.c files.

 - Ditto for northbridge/intel/i82810/raminit.c, and
   northbridge/intel/i82810/debug.c.

 - Add various header files which are now needed, drop unused includes.

 - Make functions that need to be visible non-static.

Abuild-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5951 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-13 23:00:41 +00:00
Keith Hui 6529c2a717 Move out Katmai Slot 1 CPUs (model_67x) from model_6xx to model_67x.
abuild-tested. Boot tested on P2B-LS.

Signed-off-by: Keith Hui <buurin@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5950 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-13 17:00:42 +00:00
Uwe Hermann ab50d62ea6 Convert all Intel i810 boards to CAR.
- Drop "select ROMCC" from the boards, as well as early_mtrr stuff.

 - Add "select CACHE_AS_RAM" to socket_PGA370/Kconfig, as well as the
   usual DCACHE_RAM_BASE and DCACHE_RAM_SIZE variables.

 - In socket_PGA370/Makefile.inc add:
   cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc

 - Other smaller related fixes.

Abuild-tested and boot-tested on MSI MS-6178.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5949 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-13 08:21:44 +00:00
Peter Stuge 51eafdeae6 Enable or disable the power button in Kconfig
Some mainboards need to disable the power button to avoid turning off
right after being turned on, while other boards ship with a jumper over
the power button and should allow the user to configure the behavior.

This adds infrastructure in the form of four mutually exclusive options
which can be selected in a mainboard Kconfig (power button forced on/off,
and user-controllable with default on/off) and one result bool which
source code can test. (Enable the button or not.)

The options have been implemented in CS5536 code and for all mainboards
which select SOUTHBRIDGE_AMD_CS5536, but should be used also by other
chipsets where applicable. Note that if chipset code uses the result
bool ENABLE_POWER_BUTTON, then every board using that chipset must
select one out of the four control options in order to build.

All touched boards should have unchanged behavior, except
pcengines/alix1c, traverse/geos and lippert/hurricane-lx where the
power button can now be configured by the user.

Build tested for alix1c, alix2d, hurricane-lx and wyse-s50. Confirmed
to work as advertised on alix1c both with button enabled and disabled.

Includes additional traverse/geos changes from Nathan and
lippert/hurricane-lx changes from Jens to correctly use the new
feature on those boards.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Aurelien Guillaume <aurelien@iwi.me>
Acked-by: Nils Jacobs <njacobs8@hetnet.nl>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5948 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-13 06:23:02 +00:00
Zheng Bao f2573bd237 Fix a stupid bug in rs780 and rs690 code.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Scott Duplichan <scott@notabs.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5947 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-13 05:16:48 +00:00
Zheng Bao 89122856e0 Trivial. Clean up code and add some comments.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5946 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-13 02:46:59 +00:00
Keith Hui 5e9c1cd693 Add missing include of model_6bx for slot_1.
I could no longer boot my P3B-F with my Tualeron and r5938. Dies with
"unknown CPU". I believe it will happen with any Slot 1 440BX boards
that supports model_6bx CPUs.

I need to make the change below to make it work. abuild tested. Boot
tested on P2B-LS and P3B-F.

Signed-off-by: Keith Hui <buurin@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5945 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-12 23:22:08 +00:00
Uwe Hermann f1aa9841a9 Move translate_spd_to_i82810[] from .h to .c file (trivial).
This is in preparation of further i810 fixes and switching it to CAR.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5944 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-12 21:37:03 +00:00
Uwe Hermann 74d1a6e8a1 We define IO_APIC_ADDR in <arch/ioapic.h>, let's use it.
As both ioapic.h and acpi.h define a macro named "NMI", rename one
of them (NMI -> NMIType in acpi.h).

Abuild-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5943 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-12 17:34:08 +00:00
Warren Turkal 4ffde94c4e Reduce duplicate definition in CAR code.
Macros for the register addresses for the MTRR MSRs are already defined
in include/cpu/x86/car.h. This patch uses those macros instead of
creating a second instance of that same data.

I also added a few macros to the amd mtrr.h to make the MSR naming more
consistent.

Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5942 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-12 06:13:40 +00:00
Warren Turkal 9c814d2e9e Build bootblock.S instead of bootblock.c.
The file is actually just including a bunch of assembly. The build rule
for bootblock.c even states that the file will be "assembler-with-cpp."

Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5941 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-12 06:12:00 +00:00
Sylvain Hitier 5b2fd1ea15 Fix typo after r5925.
BTW, embed the always-the-same string instead of referencing it through "%s".

Do the same for i82371EB while we're at it.

Signed-off-by: Sylvain Hitier <sylvain.hitier@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5940 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-11 23:22:24 +00:00
Uwe Hermann e62fc0d355 Build fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5939 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-11 22:49:39 +00:00
Uwe Hermann 0ea281f700 First round of ICH2/ICH2-M cleanups after split from i82801xx.
- Drop all non-ICH2 "struct pci_driver" entries from all files.

 - Kconfig: Add missing USE_WATCHDOG_ON_BOOT.

 - Drop i82801bx_sata.c and i82801bx_usb_ehci.c, ICH2 doesn't have SATA/EHCI.

 - Simplify lots of code, getting rid of i82801xx remainders.

 - Use u8 et al (instead of uint8_t) in a few more places.

 - Use #defines from header files where possible.

 - Various other fixes and updates.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5938 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-11 21:38:49 +00:00
Uwe Hermann 4b42a62966 Factor out a few commonly duplicated functions from northbridge.c.
The following functions are moved to devices/device_util.c:

 - ram_resource()

 - tolm_test()

 - find_pci_tolm()

There are only two tolm_test() / find_pci_tolm() which differ from the
defaults, one of them can easily be eliminated in a follow-up patch,
maybe even both, but for now keep it simple and only eliminate the majority.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5937 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-11 19:36:13 +00:00
Stefan Reinauer c4f98b63a7 don't include unused code, we only need the header.
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5935 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-10 21:15:53 +00:00
Stefan Reinauer 0a58a7b3ed fix typos found by zbao in other files.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5934 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-10 21:15:01 +00:00
Rudolf Marek 470e1821c3 Same applies for SB600.
Following patch enables UDMA on ALL IDE devices. The current code enables it only for primary master, which causes my DVD drive to fail under windows install
and even after hard reset in linux (DMA seems lockup).

The fix should not have any influence for Linux because the IDE driver will
correctly reprogram this bit. 


Signed-off-by: Rudolf Marek <r.marek@assembler.cz> 
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5933 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-10 20:43:00 +00:00
Rudolf Marek e522164ae1 Following patch fixes the boot_switch_sata_ide logic. It can swap
primary / secondary IDE channel with SATA (in IDE mode).
 
The bug was that setup was done in wrong device.
 
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5932 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-10 19:55:32 +00:00
Rudolf Marek 14cc927178 Following patch enables UDMA on ALL IDE devices. The current code enables it only for primary master, which causes my DVD drive to fail under windows install
and even after hard reset in linux (DMA seems lockup).

The fix should not have any influence for Linux because the IDE driver will
correctly reprogram this bit. 

Signed-off-by: Rudolf Marek <r.marek@assembler.cz> 
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5931 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-10 19:54:15 +00:00
Zheng Bao 2a5101aba4 Trivial. Spelling check.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5930 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-10 15:18:53 +00:00
Uwe Hermann 115c5b9824 Remove various .c #includes from Intel 440BX/82371EB boards.
- Use 'romstage-y' to turn i82371eb_early_pm.c and i82371eb_early_smbus.c
   into distinct compilation units, and don't #include the files anymore
   in romstage.c files.

 - Ditto for lib/debug.c, northbridge/intel/i440bx/raminit.c, and
   northbridge/intel/i440bx/debug.c.

 - Add various header files which are now needed.

 - Make functions that need to be visible non-static.

 - Drop a remaining "select ROMCC" from a 4440BX board.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Idwer Vollering <vidwer@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5929 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-09 17:00:18 +00:00
Zheng Bao 53b52f356a Trivial. Spell checking.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5928 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-09 07:18:50 +00:00
Zheng Bao 1dcf66896d Trivial. Spell checking.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5927 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-09 02:31:10 +00:00
Uwe Hermann 713ae2c090 Drop unused i82801ax_early_lpc.c and i82801bx_early_lpc.c.
Nothing ever calls the functions in these files, and we already have
i82801ax_watchdog.c and i82801bx_watchdog.c which basically do the same
_and_ are hooked up correctly in the Makefile.inc and via the
USE_WATCHDOG_ON_BOOT mechanism.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5926 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-08 20:09:21 +00:00
Uwe Hermann ab06fb0cae Round 2 of i82801AX fixes to get it into a usable shape.
- Remove left-overs from more generic code in i82801xx times, and fix
   register names as needed.
 
 - Simplify IDE init code (and save some ROM space too).
 
 - Simplify PIRQ code.
 
 - Use u8 et al instead of uint8_t everywhere.
 
 - Random other fixes.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5925 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-08 19:24:56 +00:00
Uwe Hermann 3b8db81380 Intel 82801ax/82801bx: Fix and hook up i82801xx_smbus.c.
- Fix incorrect #includes, add missing ones.

 - Drop unused do_smbus_write_block() and smbus_wait_until_blk_done().

 - Pass smbus_io_base to all functions as the other ICH implementations do.

 - Random other fixes which are required to make it build.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5924 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-08 16:40:23 +00:00
Zheng Bao c3af12fb8a Trivial. Spell checking.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5923 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-08 05:08:47 +00:00
Zheng Bao 3d682fe888 Trivial. Fix the typo.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5922 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-08 03:35:12 +00:00
Uwe Hermann 554c052b48 Remove some duplicate #include files (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5921 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-07 23:42:17 +00:00
Jonathan Kollasch e5b7507882 Remove duplicate line from pci_ids.h.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5920 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-07 23:02:06 +00:00
Scott Duplichan a3bd1b1b25 RS780 function ProgK8TempMmioBase is setting a reserved
bit in the AMD processor 'MMIO Limit Address Register'.
I suspect it is because of a typo where 0x80 was entered
as 0x8. If 0x80 is used, then the strap configuration
register accesses become non-posted, which is how the
Shiner reference BIOS does it.


Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Rudolf Marek <r.marek@assembler.cz> 



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5919 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-07 18:25:04 +00:00
Uwe Hermann 6798b47802 Convert all Intel 82371AB/EB/MB based boards to TINY_BOOTBLOCK.
Also:

Unfortunately Intel 440BX + 82371AB/EB/MB boards can have their ISA device
on various PCI bus:device.function locations.
Examples we encountered: 00:07.0, 00:04.0, or 00:14.0.

Thus, instead of hardcoding PCI bus:device.function numbers such as
PCI_DEV(0, 7, 0), we now simply find the ISA device via PCI IDs, which
works the same on all boards.

As an additional benefit this patch also gets rid of one .c file include
in romstage.c.

Abuild-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5918 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-07 16:24:28 +00:00
Uwe Hermann 6f2d20ec49 Convert all Intel 440BX boards to Cache-as-RAM (CAR).
- Add "select CACHE_AS_RAM" in src/cpu/intel/slot_1/Kconfig.

 - Add the following in src/cpu/intel/slot_1/Makefile.inc:
   cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc

 - Remove "select ROMCC" from all 440BX board Kconfig files.

 - Drop all early_mtrr_init() calls, that's done by CAR code now.

Various small fixes were needed to make it build:

 - Drop do_smbus_recv_byte(), do_smbus_send_byte(), do_smbus_write_byte(),
   those were never called anyways.

 - Remove the "static" from the main() functions in romstage.c files.

 - Always call dump_spd_registers() from the 440BX debug.c, but use
   "#if CONFIG_DEBUG_RAM_SETUP" to only have that code if RAM debugging
   is enabled in menuconfig.

 - Drop all "lib/ramtest.c" #includes and ram_check() calls (even if
   commented out) from romstage.c's, as we've done for most other boards.

 - Add missing #includes or prototypes. Some of the prototypes will be
   removed later when we get rid of the #include'd .c files.

Abuild-tested for all boards, and boot-tested on A-Trend ATC-6220.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5917 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-06 19:32:39 +00:00
Jonathan Kollasch 5225520172 Remove duplicate line from pci_ids.h.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5916 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-05 19:39:35 +00:00
Jonathan Kollasch b7a7b7903b Use %p instead of %x to print void *.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5915 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-05 19:38:04 +00:00
Myles Watson 5f89d0a7a4 Add second CK804 for tyan/s2895 and sunw/ultra40.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5913 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-05 18:21:58 +00:00
Patrick Georgi abc0c7791e attached patch moves a couple more config flags out of romstage:
CK804_USE_NIC, CK804_USE_ACI, CK804_NUM.
MCP55_USE_NIC, MCP55_USE_ACI, MCP55_NUM.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Pter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5912 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-05 17:59:12 +00:00
Patrick Georgi 5692c57336 - move EHCI_BAR_INDEX to ehci.h - it's constant as per EHCI spec 2.3.1
- move EHCI_BAR and EHCI_DEBUG_OFFSET to Kconfig to be set by USB debug port enabled southbridges
- drop USB debug code includes from romstage.cs and use romstage-srcs in the build system instead

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5911 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-05 13:40:31 +00:00
Patrick Georgi d083595350 Remove lib/ramtest.c-include from all CAR boards.
Remove many more .c-includes from i945 based boards.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5910 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-05 09:07:10 +00:00
Uwe Hermann cc0dc7f839 Add missing Intel Pentium II/III era CPU IDs.
Add links to the respective Intel specification updates or manuals where
the IDs are listed. Mention the possible core steppings of each CPU ID.

There are duplicate IDs in model_6xx and model_68x for now, not sure if
those should be eliminated, but there were already duplicates before this
patch, so that's probably an extra issue to look into.

Abuild-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5909 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-04 20:43:55 +00:00
Uwe Hermann 36455aade4 Add comments to make it clear why these two lines are written like that:
movl    $REAL_XIP_ROM_BASE, %eax
  orl     $MTRR_TYPE_WRBACK, %eax

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5908 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-02 20:51:29 +00:00
Uwe Hermann ae3f2b3706 Allow selecting the physical USB Debug Port on AMD SB700.
The AMD SB700 allows changing the physical USB port to be used as
USB Debug Port, implement support for this.

Also, fix incorrect PCI device of the SB700 EHCI device. Actually, the
SB700 has _two_ EHCI devices (D18:F2 and D19:F2), but for now we only use
D18:F2. Our generic USBDEBUG code cannot handle multiple EHCI PCI devices
currently, AFAICS.

Hook up all SB700 boards to the CONFIG_USBDEBUG_DEFAULT_PORT facility.

Untested, but should work.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5907 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-02 20:36:26 +00:00
Uwe Hermann fa7efe9f40 AMD SB600 uses a hardcoded USB Debug Port number.
It cannot be changed via software according to the datasheet, whereas
this is indeed possible on AMD SB700. I tested using the SB700 mechanism
on SB600 but it didn't work, so I suspect the datasheet is indeed correct.

Thus, don't show the kconfig option for selecting the physical USB port
on the AMD SB600 southbridge.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5906 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-02 20:33:56 +00:00
Jonathan Kollasch df67c674a0 Don't define K8_4RANK_DIMM_SUPPORT, nothing uses it.
All these boards define QRANK_DIMM_SUPPORT anyway,
which is probably what was meant.

Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5905 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-02 14:10:08 +00:00
Jonathan Kollasch ebe6d5820a Fix spelling/typos in comments.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5904 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-02 12:51:38 +00:00
Uwe Hermann dd8367006c Factor out common CAR asm snippets.
This makes the CAR implementations a lot more readable, shorter and
easier to follow, and also reduces the amount of uselessly duplicated code.

For example there are more than 12 open-coded "enable cache" instances
spread all over the place (and 12 "disable cache" ones), multiple
"enable mtrr", "save BIST", "restore BIST", etc. etc.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5902 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-01 21:46:04 +00:00
Uwe Hermann 2ba2b553b5 Cosmetics, whitespace and coding-style fixes for Intel CAR (trivial).
This is abuild-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5901 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-01 17:37:45 +00:00
Myles Watson d3f620299c Fix make warnings:
Makefile:261: warning: overriding commands for target `coreboot-builds/a-trend_atc-6220/lib/lzma.ramstage.o'
Makefile:261: warning: ignoring old commands for target `coreboot-builds/a-trend_atc-6220/lib/lzma.ramstage.o'

lzma.c is already included unconditionally in the same file.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5900 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-01 15:23:41 +00:00
Myles Watson c7e982bbef Fix some breakage from 5890.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5899 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-01 15:16:20 +00:00
Patrick Georgi e82618d037 Move CACHE_AS_RAM_ADDRESS_DEBUG out of romstage.c into Kconfig,
rename it slightly, make it visible only on relevant northbridges,
drop it entirely from via boards (as they seem to have picked it
up from AMD code without using it themselves), and make it
default to false for all boards.

Some romstages used to set this to "true" (ie. "print debug output"),
but I didn't follow up on it in Kconfig - if you need it to debug CAR,
enable it yourself.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5898 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-01 14:50:12 +00:00
Stefan Reinauer f11b81d18d fix VIA C7 code.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5897 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-01 12:24:57 +00:00
Patrick Georgi 6c05bf4114 ICS951462_ADDRESS defined but _never_ used. Drop it.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5896 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-01 11:34:05 +00:00
Peter Stuge 76d914391c Make i945/raminit.c:fsbclk() return u16 rather than int
This is needed for Gentoo gcc-4.1.2 to build the i945 code. A warning is
thrown because the comparison in the last hunk is between u16 and -1 and
can never be true.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5895 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-01 10:02:33 +00:00
Patrick Georgi 6f56ad2d2e Remove a couple of defines that seem to be the result of
copy&paste, without actually being used.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5894 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-01 09:58:44 +00:00
Peter Stuge e4bc0f6480 Split NORTHBRIDGE_INTEL_I945 into more precise _I945GC and _I945GM
Both chipsets use the src/northbridge/intel/i945 code but that code
needs to know which chipset is actually used. Having separate
NORTHBRIDGE_ options allows the I945GC/I945GM choice to be removed
since code can test the NORTHBRIDGE_ option directly.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5893 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-01 09:13:18 +00:00
Uwe Hermann c2d0bfb470 Add missing parenthesis (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5892 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-01 09:11:15 +00:00
Patrick Georgi 77d6683edd Move several i945 config #defines from romstage.c to Kconfig.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5891 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-01 08:02:45 +00:00
Uwe Hermann 66d1687b92 CAR simplifications, typos, readability improvements (trivial).
- Use some more #defines instead of hard-coding values.

 - Merge multiple movl/orl or movl/andl lines into one where possible.

 - Add some TODOs in places which seem to have either an incorrect
   code or incorrect comment.

 - Fix typos: s/for/from/, s/BSC/BSP/, s/size/carsize/.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5890 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-01 07:27:51 +00:00
Zheng Bao 52000e1688 Trivial. Re-indent the code.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5889 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-01 06:27:35 +00:00
Uwe Hermann 4292684e1a Various cosmetic and coding style fixes in CAR code (trivial).
Also, whitespace fixes, consistency fixes, and drop some of the less
useful comments.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5888 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-30 23:15:36 +00:00
Uwe Hermann 1d36d6df7d Use existing, readable MTRR #defines instead of hardcoding numbers.
Replace $0x200 with $MTRRphysBase_MSR(0) etc. Also, move some #ifdef stuff
a little bit around (should not affect any functionality) to make the
Intel/AMD/VIA CAR implementations more similar and easier to compare.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5887 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-30 21:22:40 +00:00
Patrick Georgi 8463dd9db0 Rename build system variables to be more intuitive, and
at the same time let the user specify sources instead
of object files:
- objs becomes ramstage-srcs
- initobjs becomes romstage-srcs
- driver becomes driver-srcs
- smmobj becomes smm-srcs

The user servicable parts are named accordingly:
ramstage-y, romstage-y, driver-y, smm-y

Also, the object file names are properly renamed now, using
.ramstage.o, .romstage.o, .driver.o, .smm.o suffixes consistently.

Remove stubbed out via/epia-m700 dsdt/ssdt files - they didn't
easily fit in the build system and aren't useful anyway.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coreystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5886 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-30 16:55:02 +00:00
Stefan Reinauer d4d0a456d3 fix Kontron KT690 and clean up socket S1G1 boards accordingly.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5885 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-30 07:56:12 +00:00
Stefan Reinauer 011d0d86b0 drop unneeded earlymtrr.c include
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5884 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-30 07:45:58 +00:00
Warren Turkal 98a8c0ca7f Move CAR settings to board config for socket 940 boards.
For the a number of the socket 940 based machines, I collapsed their CAR
configurations into the socket config.

However, I have kept a number of overrides in place for the following
machines:
* broadcom/blast
* ibm/e32{5,6}
* newisys/khepri
* sunw/ultra40
* tyan/s488{0,2}

These machines used different setting than the defaults for socket 940
systems.

Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5883 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-30 03:35:00 +00:00
Warren Turkal 7a59a44e17 Move VIA C7 board CAR config to VIA C7 instead of boards.
This change is somewhat dangerous as it enables CAR for some boards that
it was not enabled for before.

Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5882 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-30 03:13:21 +00:00
Uwe Hermann 17cae3599f Forgot to 'svn add' src/cpu/x86/name (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5880 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-29 10:51:05 +00:00
Uwe Hermann aac8f661f5 Factor out fill_processor_name() and strcpy() functions.
The fill_processor_name() function was duplicated in multiple
model_*_init.c files, move it into a new src/cpu/x86/name
directory.

The strcpy() function was also duplicated multiple times, move it
to <string.h> where we already have similar functions.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5879 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-29 09:54:16 +00:00
Uwe Hermann 5c9bc138ec Drop some unneeded "#if CONFIG_USBDEBUG" (trivial).
We don't surround the <usbdebug.h> #include with those checks in other
places either. Abuild-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5876 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-28 17:48:24 +00:00
Myles Watson 24a5213a39 Remove redundant HW_MEM_HOLE_SIZEK and HW_MEM_HOLE_SIZE_AUTO_INC settings.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5875 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-28 16:16:58 +00:00
Zheng Bao 7b1a3c334c Trivial. re-Indent the code.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5874 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-28 04:43:16 +00:00
Warren Turkal 3bd792947b I missed these boards in a previous commit.
Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5873 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-27 21:28:21 +00:00
Stefan Reinauer c0bde289c2 Good bye, OLPC...
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Nils Jacobs <njacobs8@hetnet.nl>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5872 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-27 21:26:46 +00:00
Warren Turkal e0afe735a0 All these boards already had the CACHE_AS_RAM option in their individual
configs. I just moved it the the CPU that they all use.

Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5871 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-27 21:18:26 +00:00
Warren Turkal 768d8ea098 Move CAR config from mainboard to CPU config for AMD GX2 boards.
Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5870 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-27 21:15:56 +00:00