Commit Graph

8030 Commits

Author SHA1 Message Date
Alexandru Gagniuc fa840676f5 ec/compal/ene932: Update to use coreboot EC-mainboard API
This patch implements a simple interface between the EC and mainboard
ASL code. This interface does not rely on the preprocessor, and
prevents name conflicts by scoping the interface methods. As this
interface is documented on the coreboot wiki, an in-tree documentation
is not provided.

Change-Id: If0b09be4f5e17cc444539a30f0186590fa0b72b5
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5515
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-19 03:49:48 +02:00
Alexandru Gagniuc 91b6d3a6b9 hp/pavilion_m6_1035dx: Rename "LID0" ACPI object to "LID"
There is only one lid switch, so it does not make sense to number it.
This naming is also consistent with the examples in the ACPI spec.

Change-Id: Ida0a4a89ca03b2aad4fc77e52996e86332d370cd
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5545
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-04-19 03:14:35 +02:00
Alexandru Gagniuc 489ff7ef87 hp/pavilion_m6_1035dx: Shutdown when lid is closed on non-ACPI OS
This is handled by generating an SMI when GEVENT22 goes low. This pin
is driven by the EC when the lid opens or closes. This SMI is
disabled when switching to ACPI mode, so ACPI OSes are not affected.

Change-Id: I38193572bf0416fd642002dba94c19257f0f6f5b
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/171
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-18 21:58:50 +02:00
Alexandru Gagniuc 599d668cdd southbridge/hudson: Compile refactored SMI setup utilities in SMM
Refactor hudson_enable_gevent_smi() to allow configuring the interrupt
mode and trigger level. Move the utilities which are useful in SMM to
a separate file that is included in both ramstage and SMM. This is
useful for SMI handlers which need to enable or disable GEVENT SMIs
on-the-fly. A follow-up patch makes use of this infrastructure.

Change-Id: Ifa4c300c00c178b18d7280690cfc4b8367c669b8
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/170
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-18 21:58:39 +02:00
Alexandru Gagniuc dbe6336f90 hp/pavilion_m6_1035dx: Shutdown on low battery with non-ACPI OS
Intercept the low battery SMI from the EC, and shut down the system
immediately. The EC only sends this SMI when the OS did not enable
ACPI mode, so ACPI OSes are not affected by this.
On the other hand, payloads such as GRUB or SeaBIOS will experience
the shutdown. This behavior is helpful for protecting the battery, for
example, when the OS fails to boot and we are stuck in the payload.
The low battery SMI is triggered at 10% charge, at which point the risk
of cell degradation exists.

Change-Id: I4c6c1a4feed8576cbdbb1945768de0805a1f5e42
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5527
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-18 21:16:24 +02:00
Kyösti Mälkki f339086265 console: Simplify the enable rules
Consoles on CBMEM and USB have somewhat complex rules and dependencies
when they can be active. Use simple variables to test which stage
of boot is being built for each console.

Change-Id: I2489e7731d07ca7d5dd2ea8b6501c73f05d6edd8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5341
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-18 16:41:09 +02:00
Kyösti Mälkki e8792be223 build rules: Identify build stage with simple variables
Provide simple environment variables telling which stage of boot is
being built. Also move this to arch-agnostic location.

Change-Id: I8cbb5cf91f53e01c06e7d672b5be3f5c235f911d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5410
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2014-04-18 16:40:32 +02:00
Kyösti Mälkki efb0b51e62 console: Split ROMCC helpers
These are potentially useful with GDB or SerialICE too.
Also it reduces the amount of actual code we put in romcc_console.

Change-Id: Id8c56e979660ad9f4eef39c648f68c7ec60edfba
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5339
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-18 16:39:40 +02:00
Kyösti Mälkki 4076072b6c console: Use romstage code for ramstage and SMM
Console is arch-agnostic and there is no need for separate
implementations for romstage and ramstage.

For SMM there is console only if DEBUG_SMI is selected.

Change-Id: I7028eeeff8bfbb9c8552972436b29a7508834d87
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5338
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-18 16:39:19 +02:00
Kyösti Mälkki fd95624dae console: Drop driver list in ramstage
This framework was only available in ramstage. So we had to define
console output functions separately for bootblock, romstage and SMM.
Follow-up patches will re-enable all the consoles removed here,
in a more flexible fashion, and with less lines-of-code and copy-paste.

Also the driver list is not in a well-defined order and some of the
loops could exit without visiting all drivers.

NOTE: This build has no console in ramstage.

Change-Id: Iaddc495aaca37e2a6c2c3f802a0dba27bf227a3e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5337
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-18 16:39:09 +02:00
Patrick Georgi aece3c931e msi/ms9652_fam10: minor Kconfig cleanup
SMP and IOAPIC shouldn't need to be redefined here, select is enough

Change-Id: I8a66374205b671498ce21b3f174af14e98dbfe48
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5541
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-18 15:09:41 +02:00
Edward O'Callaghan f951d66d31 southbridge/sb800: Strip obsolete commentary
Change-Id: I5cd9e1fcf197eae966be710b2ab24f49c6885eb0
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5529
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-18 11:51:36 +02:00
Kyösti Mälkki 43cb7ca922 AMD hudson yangtze: Drop MAX_PHYSICAL_CPUS in comments
Change-Id: I81de291da7b3db8d04a127d5a304b558f1c75b34
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5535
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-17 23:56:33 +02:00
Alexandru Gagniuc fa4cb6d606 southbridge/hudson: Remove unused function set_sm_enable_bits()
This function isn't used on hudson, and seems to be copy-paste from
older southbridges. It is used in sb700 to enable or disable certain
PCI devices. On hudson, these configuration bits are moved to the PM
space.

Change-Id: I9b967a2d0a5dddc8341204dadeed90460251915c
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5513
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-17 23:20:12 +02:00
Alexandru Gagniuc 09fe3f83c5 hp/pavilion_m6_1035dx: Remove code which dumps ACPI tables
Dumping ACPI tables in canonical form has very little value, and is
of questionable use except when debugging acpigen. Remove the code
which dumps the tables.

Change-Id: Id13c88cee8674b13e5cf5b5ed32c26283e586fd9
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5526
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-17 16:50:01 +02:00
Alexandru Gagniuc 73639e2717 hp/pavilion_m6_1035dx: Add SMI handler and handle EC requests
The EC may disable some functionality, such as Caps Lock LED and
battery charging if it never receives a command to go in APM mode. If
we start it in APM mode, then immediately switch to ACPI mode, it will
not get its SCIs serviced until an ACPI OS boots. If its SCIs are not
serviced, it may assume the OS has hung.

The way we solve this is to initalize the EC in APM mode, and only
switch it to ACPI when an ACPI-capable OS issues the ACPI_ENABLE
command. The switch has to be handled in SMM.

Although we aren't yet processing SMIs from the EC, we are reading the
status in order to satisfy the EC that the event is handled.

Change-Id: Iffaeb9a6f57841f456c4bce8337dc09b287f8758
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5512
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-17 16:48:57 +02:00
Kyösti Mälkki 62abbe909d roda/rk9: Drop MAX_PHYSICAL_CPUS
Change-Id: I9c41cccf9058c48006b247aca705a3f869ae82a6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5524
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-17 08:20:24 +02:00
Alexandru Gagniuc 288c95882d southbridge/hudson: Add support for ACPI enable/disable via SMI
This enables the ACPI SMI command port in the FADT table, and sets up
the hardware accordingly. If we have SMI enabled, then we don't set
the SCI_EN bit at boot, causing the OS to send the ACPI_ENABLE
command, as required by the ACPI spec. This gives us a chance to hook
into the mainboard_smi_apmc() handler.

Change-Id: Ib4c63d55b3132578dcae48bfe2092d4ea35821dd
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5511
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-17 04:42:44 +02:00
Alexandru Gagniuc 22d90e34f9 southbridge/hudson: Pass GEVENT SMIs to mainboard_smi_gpi()
Change-Id: Ifc368974a7a0dc0756431654fb89668e3846801a
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5502
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-17 04:42:10 +02:00
Alexandru Gagniuc 2dbd08faf4 southbridge/amd/agesa/hudson: Add initial support for SMM
This sets up the infrastructure to handle SMIs generated by the Hudson
southbridge. An API for interfacing to mainboard handlers is not
defined at this point. A few functions are defined to allow mainboard
code to enable SMIs from GEVENT pins. These are the only functions which
I expect to be needed anytime in the foreseeable future.

SMIs are always acknowledged and cleared, as not clearing an SMI will
cause us to re-enter the SMI, effectively bricking the machine if a
southbridge-generated SMI without a handler occurs.

Change-Id: Ibceb21ac5423eb134d3eb7d24800280b183f7619
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5494
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Tested-by: build bot (Jenkins)
2014-04-17 04:41:49 +02:00
Alexandru Gagniuc 065b7da298 cpu/amd/agesa/family15tn: Add udelay implementation for SMM
This is a small implementation which uses only MSRs and rdtsc, without
relying on northbridge or other system hardware. It's SMM safe in that
it only reads registers, and doesn't modify the state of the hardware.

Change-Id: Ifa02ca73455b382f830c9b30b80b4f1bb18706b4
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5501
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-16 23:42:19 +02:00
Alexandru Gagniuc 53072d869a cpu/amd/agesa/family15tn: Add initial support for SMM mode
This is the minimal setup needed to be able to execute SMI handlers.
Only support for ASEG handlers is added, which should be sufficient
for Trinity (up to 4 cores).

There are a few hacks which need to be introduced in generic code in
order to make this work properly, but these hacks are self-contained.
They are a not a result of any special needs of this CPU, but rather
from a poorly designed infrastructure. Comments are added to explain
how such code could be refactored in the future.

Change-Id: Iefd4ae17cf0206cae8848cadba3a12cbe3b2f8b6
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5493
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-16 23:42:00 +02:00
Alexandru Gagniuc 342ac64a5d southbridge/hudson: Use MMIO instead of PIO to access PM space
The MMIO region is set up by AGESA very early on, so we can use it to
access the PM register space in ramstage. 16-bit accessors are also
provided to simplify some setup tasks. 16-bit accesses are not
possible via PIO.
The pm2_iowrite/read accessors are removed, as they are not used.

Change-Id: Ie7967b5086eb004525c39721338c6495aedc8165
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5503
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-16 22:29:33 +02:00
Kyösti Mälkki f3e82f7969 AMD AGESA fam15tn/fam16kb: Remove unused source files
Change-Id: I45084ffe84fef4dd43acea843d7c93a81c255472
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5523
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2014-04-16 14:39:11 +02:00
Kyösti Mälkki 72a1768aba AMD hudson yantgze: Drop MAX_PHYSICAL_CPUS
Not used with AGESA vendorcode.

Change-Id: I4de7e49d513a1bc8d6d4da1eea630b9eedf5de80
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5522
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2014-04-16 14:38:58 +02:00
Kyösti Mälkki fd478f92a4 AMD hudson yantgze: Drop APIC_ID_OFFSET
Not used with AGESA vendorcode.

Change-Id: I1c4e1dea8836143334d336f99afcee2ca326b0c9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5521
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2014-04-16 14:38:55 +02:00
Kyösti Mälkki 740862c7d3 AMD AGESA: Drop SB_HT_CHAIN_UNITID_OFFSET_ONLY
Not used with AGESA vendorcode.

Change-Id: Ic9a0513641bf76d748bb106675bccc33c7abe21e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5520
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-04-16 14:38:30 +02:00
Kyösti Mälkki aeb48934d4 AMD AGESA: Drop LIFT_BSP_APIC_ID
Not used with AGESA vendorcode.

Change-Id: Ie99abf5bcffd740e2e7ed6d78937ab32935ef214
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5519
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-04-16 14:38:05 +02:00
Kyösti Mälkki ef5ce9a832 AMD AGESA: Drop AMDMCT
This config option is fam10 only.

Change-Id: I7f4619d2d4e7e7695a8ee691d879df2748f1c0c7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5518
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-16 14:37:56 +02:00
WANG Siyuan 65f0dbc064 AMD Thatcher: add IMC fan control
There are 3 steps to enable the IMC fan control:
1. Enable fan control related registers on Hudson using oem_fan_control().
2. Set EcStruct.
3. Enable thermal zone using enable_imc_thermal_zone().
I have tested on Thatcher.

Change-Id: I959721b4fd8787ac0824f9f873efd4788682eedb
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/5359
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-04-16 13:35:51 +02:00
Patrick Georgi 9b0de71459 buildsystem: check for coreboot toolchain by default
Other toolchains just don't cut it.

Change-Id: I7a0bdf60d89b5166c9a22c9e9f3f326b28f777b8
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/4584
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-04-16 08:20:06 +02:00
Alexandru Gagniuc 6ac7f5301f hp/pavilion_m6_1035dx: Add EC keyboard controller to devicetree
This causes coreboot to call the keyboard initialization code for the
KBC. This is only needed for payloads which do not initialize the
keyboard.

Change-Id: Id0bb77f2a8115fafc0cd6165a8431a7e07f0fac1
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5514
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-04-16 03:05:10 +02:00
Edward O'Callaghan e07cb65c20 vendorcode/amd/agesa/fam14: Build as a static library
Following the same reasoning as commit
ee905a8 vendorcode/amd/agesa/fam15tn: Build as a static library
Since AGESA is stage-independent, we can build it just once, and use
the resulting static library in both rom and ram stages.

Change-Id: I8b78c462f4963fbb3a40d739196529fffedccb4c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5441
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-15 17:23:37 +02:00
Edward O'Callaghan 00b6146030 hp/pavilion_m6_1035dx: Use hexdump() for dumping ACPI tables
Following the rational of:
5188d40 jetway/nf81-t56n-lf: Use hexdump() for dumping ACPI tables
Use "Debugging -> Output verbose ACPI debug messages" in menuconfig to
toggle.

Change-Id: Ibf03ef916a789d0f049190755213ba93191d4662
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5507
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-15 17:21:53 +02:00
Edward O'Callaghan ef4dcc09bb mainboard/jetway/nf81-t56n-lf: Make ACPI debug menuconfigable
Turns out we have a CONFIG_DEBUG_ACPI definition under:
Debugging -> Output verbose ACPI debug messages
Hence, let us make use of this definition.

Change-Id: I1b673feb6d9b2ee51c832a1cef159cd80e5c3517
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5506
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-15 17:21:31 +02:00
Edward O'Callaghan feebd86ad2 mainboard/jetway/nf81-t56n-lf: Documentation cosmetics
Keep under 80 colums and Doxygen'ify inline documentation somewhat.
Strip some whitespace bulk while here and refactor a little as to line
wrap.

Additionally, following the reasoning of:
0b2fa34 hp/pavilion_m6_1035dx/buildOpts.c: Remove commented out tables
remove some fluff from buildOpts.c

Change-Id: Icb38f087724d3e3511df1d554a620eb637ce286a
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5481
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-04-15 05:16:21 +02:00
Edward O'Callaghan c12db59bce superio/ite/it8728f: Fix headers and prototype location
Try to conform to some kind of standard/consensus for prototype
location. Correct headers while here.

Change-Id: Ie99b1801fa42ddefb9f25d54f326ba7131bd7089
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5499
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-15 04:35:20 +02:00
Alexandru Gagniuc 01e0adf267 southbridge/amd/agesa/hudson: Clean up AGESA #includes
Just like in commit
* 1d87dac hp/pavilion_m6_1035dx: Sanitize #includes

Include AGESA headers specifying the path relative to AGESA_ROOT. The
path is specified relative to AGESA_ROOT as opposed to src/ since this
code may include headers from different AGESA families, depending on
the board.

Change-Id: Ide38cc34e207a8b617d1d319fd9c17a785f55833
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5423
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-04-15 01:33:07 +02:00
Alexandru Gagniuc ee905a8161 vendorcode/amd/agesa/fam15tn: Build as a static library
Up until now, we were building AGESA by specifying each AGESA source
file and adding it to the list of romstage and ramstage source files.
As a result, we were compiling each AGESA source twice, despite the
fact that it does not depend on the stage we're in.

Since AGESA is stage-independent, we can build it just once, and use
the resulting static library in both rom and ram stages.

We still keep the practice of specifying every single AGESA directory
as an include dir and adding the AGESA CFLAGS to our global CFLAGS;
this is needed due to the way AGESA builds.

Change-Id: I9b23264129d1c08cb67cabc31d15a68d43ed7624
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5430
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-04-15 01:30:25 +02:00
Alexandru Gagniuc 5405d3fe91 hp/pavilion_m6_1035dx: Fix GPIO map and add WLAN pin
Change-Id: I07725b71508c8b08451022307ae934c1b227f7f9
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5491
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-14 16:31:34 +02:00
Edward O'Callaghan 5188d4008b jetway/nf81-t56n-lf: Use hexdump() for dumping ACPI tables
Use hexdump() instead of a local implementation for dumping ACPI_TABLES.

Change-Id: I20354a4f9dff4105de5af696bb9da4a4f6cca788
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5466
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-04-14 06:59:38 +02:00
Alexandru Gagniuc cd96e829f1 hudson boards: Don't require ide.asl file on boards without IDE
Not all boards which use the AMD Hudson southbridge have IDE. However,
the southbridge's asl included an 'ide.asl' file which had to be
present in $(mainboard_dir)/acpi.

Address this issue by removing the inclusion of 'ide.asl' from the
southbridge 'fch.asl' and remove 'ide.asl' from Hudson boards, none
of which have IDE.

If future hudosn board will come with IDE, the device can be declared
in the PCIO scope of dsdt.asl, right below the inclusion of 'fch.asl'.

Change-Id: Ie2efb7ebf8f5b527e26d7aaaeafbd3053a9a6b28
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5459
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-13 21:51:19 +02:00
Edward O'Callaghan 10b834374b cimx/sb800/cfg.c: Cut out purposeless ROM reading noise.
Follow along hudson, cut out "SLP_TYP type was 0" excessively filling
the buffer. We could make this conditional on non-zero?

Change-Id: Iffd4c146b2ac4f57dbc3a011a683c92b6e132e39
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5495
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-13 17:15:04 +02:00
Alexandru Gagniuc b4417fb139 hp/pavilion_m6_1035dx: Add basic EC initialization
The EC is now set to ACPI mode, and properly generates SCIs on
external events. This fixes the issue where battery notifications were
not working.
The keyboard matrix type is also explicitly set up.

Change-Id: Ib6f0d23984d4ed1320340282469b8325c83547d1
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5471
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-04-13 15:29:50 +02:00
Edward O'Callaghan 99e2bf87ef cimx/sb800 boards: Don't require ide.asl on boards without IDE
Not all boards which use the AMD cimx/sb800 southbridge have IDE.
However, the southbridge's asl included an 'ide.asl' file which had to
be present in $(mainboard_dir)/acpi.

Address this issue by including ide.asl only in boards which have IDE,
and remove it from all other cimx/sb800 boards.

Change-Id: I57fcb4db9f85234b05ae1705ef81a576c478cee6
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5460
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-13 09:06:15 +02:00
Edward O'Callaghan 0e3ca27315 mainboard/*/acpi/ide.asl: Serialize ACPI methods to avoid races.
Serialize methods against the construction of same (named) objects by
competing threads. See ACPICA BZ 909 for further details.

This change fixes issues that show up with the Ubuntu firmware test
suite (fwts) ACPI table sanity checker.

Change-Id: I49e3050a2a5aece6f031122b0211c056938d1a89
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5458
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-13 08:25:44 +02:00
Alexandru Gagniuc 374251d901 cpu/amd/agesa/s3_resume.c: Specify include paths from AGESA_ROOT
Following the same reasoning as in commit
* 1d87dac hp/pavilion_m6_1035dx: Sanitize #includes
include AGESA files with a path relative to AGESA_ROOT. We cannot
with more than one generation of AGESA, hence the path being relative
to AGESA_ROOT.

Change-Id: If15c4cbfd42e0264264fdb3e8c426a47609ad41f
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5426
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-13 08:25:23 +02:00
Edward O'Callaghan c21bd8839b jetway/nf81-t56n-lf: Replace AGESA types with stdint types
Try to use void and uint*_t type specifiers in place of VOID and UINT*
respectively. Use const in place of CONST type modifier. Remove some
useless type casts.
A few unneeded comments containing the AGESA redefenied types are also
removed.

Change-Id: I4bff96a222507fc35333488331c3f35ef1158132
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5486
Tested-by: build bot (Jenkins)
2014-04-13 05:32:09 +02:00
Edward O'Callaghan e2f3bfc5b3 jetway/nf81-t56n-lf: Use std memset/memcpy func over AGESA
Replace usage of AGESA poor reinvention of memset/memcpy functions with
the usual standard ones.

Change-Id: Ibfe9ee253d57140b06a4fca6b47b2051308ad012
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5484
Tested-by: build bot (Jenkins)
2014-04-13 05:31:51 +02:00
Alexandru Gagniuc ac138976df hp/pavilion_m6_1035dx: Add ACPI support for lid switch
This is sufficient to at least allow linux to recognize the lid switch
and read its state correctly.

Change-Id: Id5bd92466c72559f263c7ca8d23cbc741377a762
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5464
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-12 21:37:38 +02:00
Alexandru Gagniuc 27bb6ad046 hp/pavilion_m6_1035dx: Declare GPIO control block in ACPI
Only the WLAN control pin and the lid switch input are declared, as
those are the only pins whose function is known and tested.

Change-Id: Ia5871882884ba9bb6d63418b34e33f92ead669eb
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5463
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-12 21:16:19 +02:00
Alexandru Gagniuc f0504352b1 hp/pavilion_m6_1035dx: Add ACPI support for reading battery level
Hook in the EC ASL code. This provides just enough information for the
OS to be able to read the battery information.

EC notifications (_Qxx) do not yet work, and it is unclear if the
issue is in the ACPI code, or if the EC is not set up properly. Thus,
the OS must boot with the battery inserted in order to be able to read
its status.

The _L03 ACPI method is also removed, as the EC SCI uses this event.

Change-Id: I85cbaeb9c77e60bd1c68d928412f897de50c6329
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5445
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-04-12 20:31:22 +02:00
Alexandru Gagniuc 1a3872f7a4 ec/compal/ene932/acpi: Let mainboard define the ACPI lid object
The GP15 ACPI object was used to get the state of the lid. However
GP15 is specific to certain Intel chipsets, and will not always be in
the ACPI namespace. Instead of hardcoding this object, let the
mainboard define it.

Also, document the ACPI interface for the EC.

Change-Id: I02a2eb3116af61ea5701f84507327aa40218597a
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5444
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-04-12 20:26:04 +02:00
Patrick Georgi 5d41c1a7f9 agesa: Always include family* Kconfig
Otherwise we generate a recursive dependency because
CPU_AMD_AGESA depends on the per-family configurations
while those only exist if CPU_AMD_AGESA is selected.

Change-Id: Ic08d517ff4ca8bb76afc1574b55c54b28ec3f1b0
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5490
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-12 13:34:36 +02:00
Martin Roth 4e6881f0ba Add the Rangeley FSP include & srx directories
These are the .h and .c files from Intel that support interaction
with the FSP.  These have been modified from the FSP distribution
only to strip trailing whitespace.

Intel® Firmware Support Package for Intel® Atom™ Processor C2000
Product Family (Formerly Rangeley)

"Intel® Firmware Support Package (Intel® FSP) provides key
programming information for initializing Intel® silicon and can be
easily integrated into a boot loader of the developer’s choice.
It is easy to adopt, scalable to design, reduces time-to-market, and
is economical to build."

http://www.intel.com/fsp

Change-Id: I9ed94cb92909c3681cc88bf10b85a9ba25e8fc55
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/5457
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-04-11 17:29:40 +02:00
Martin Roth 954f3882f1 Add the Bay Trail FSP include & srx directories
These are the .h and .c files from Intel that support interaction
with the FSP.  These have been modified from the FSP distribution
only to strip trailing whitespace.

Intel® Atom™ processor E3800 product family (formerly Bay Trail)

"Intel® Firmware Support Package (Intel® FSP) provides key
programming information for initializing Intel® silicon and can be
easily integrated into a boot loader of the developer’s choice.
It is easy to adopt, scalable to design, reduces time-to-market, and
is economical to build."

http://www.intel.com/fsp

Change-Id: I0fa64dbaf640493cdb5e670e8d213a49d9e7dcfb
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/5456
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-04-11 17:29:25 +02:00
Martin Roth debd765754 Add the ivybridge i89xx FSP include & srx directories
These are the .h and .c files from Intel that support interaction
with the FSP.  These have been modified from the FSP distribution
only to strip trailing whitespace.

Intel® Firmware Support Package for Intel® Xeon® E3-1125C v2,
E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™
i3-3115C Processors for Communications Infrastructure with
Intel® Communications Chipset 89xx Series Platform Controller Hub
(formerly Crystal Forest Refresh: Ivy Bridge Gladden and Cave Creek

"Intel® Firmware Support Package (Intel® FSP) provides key
programming information for initializing Intel® silicon and can be
easily integrated into a boot loader of the developer’s choice.
It is easy to adopt, scalable to design, reduces time-to-market, and
is economical to build."

http://www.intel.com/fsp

Change-Id: Ib76e89b2d2f6407cf55a5a664da989c7a7e0eb23
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/5455
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-04-11 17:27:32 +02:00
Martin Roth 18a40e0533 Update vendorcode/intel/makefile for coming FSPs
Other FSPs have more than just the initial fsphob.c source file.
Add any .c files in the srx directory to the ramstage build.

Change-Id: I5118bdcca44935b579809c4fc9566ab7914a6e4b
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/5454
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-11 17:24:39 +02:00
Paul Menzel eb4920df32 intel/*bd82x6x/acpi/pch.asl: Correct name of field unit to GP03
GP0e does not fit into the naming scheme of the field units surrounding
this field unit definition. Also the keys for e and 3 are close to each
other supporting the theory that this is indeed a typo.

Change-Id: I43cf288fe1e0240b33971073c1aa8a1db5762e31
Reported-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5483
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-11 15:21:03 +02:00
Alexandru Gagniuc 6b583a454c vendorcode/amd/agesa: Do not hardcode ROM base address
The ROM address range is set up in the LPC PCI device, register 0x6c.
Coreboot already sets that up correctly in the bootblock, however
AGESA overrides that to 0xffffff00, which will always map the ROM from
0xff000000. This may conflict with other devices which are assigned
address space in that range.

If a device is assigned a range between 0xff000000 and the real ROM
base, accesses to that device will be diverted to the system ROM,
regardless of how other BARs are set up. Since we already need to set
up the ROM address range in the bootblock, before calling AGESA, just
remove the override from AGESA.

Note that not all AGESA versions override this mapping.

Change-Id: I592e5d087ed830c9604a04a356912c7654ce56d2
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5467
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-04-09 21:54:53 +02:00
Konstantin Aladyshev 8395e90bc0 supermicro/h8qgi/dsdt: Use PIC as default interrupt model
According ACPI specification:

"""
The \_PIC optional method is used to report to the BIOS the current
interrupt model used by the OS. The argument passed into the method
signifies the interrupt model OSPM has chosen, PIC mode, APIC mode,
or SAPIC mode. Notice that calling this method is optional for OSPM.
If the method is never called, the BIOS must assume PIC mode.

Arguments: (1)
Arg0 – An Integer containing a code for the current interrupt model:
0 –PIC mode
1 –APIC mode
2 –SAPIC mode
"""

In current configuration with default value of interrupt model
PMOD equal 1 (APIC mode), Linux can't boot with "noapic" option.
Kernel never call _PIC method and PMOD stays equal 1, indicatind
that APIC routing objects should be evaluated. This mix of PIC
and APIC leads to boot fail.

Change default value of interrupt model PMOD to 0, for correct
"noapic" boot.

Change-Id: I7fa6f0c24802751202ed2e7f13411001a600e772
Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru>
Reviewed-on: http://review.coreboot.org/5473
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-09 20:52:12 +02:00
Edward O'Callaghan fe365ac7e8 mainboard/lenovo: [2/2] implement initial T530 support
Step 2: change the Lenovo X230 code to adapt it to the new board's
hardware with the great guidance from Vladimir (phcoder) to find the
correct GPIO's.

The machine has:
 - Chipset: Intel QM77
 - GPU's: Intel Integrated HD Graphics
        : Discrete NVIDIA NVS 5400M (1 GB VRAM) with Optimus Technology

Change-Id: Iee12c3edc22df4a7935b7fb7ff4a320c21c4239b
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5391
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-09 16:41:14 +02:00
Edward O'Callaghan 956c298233 mainboard/lenovo: [1/2] fork X230 to T530
Step 1: copy all files unmodified from Lenovo X230.  This makes it much
easier later to see how the two boards actually and deliberately differ
when porting bugfixes from one to the other.

Change-Id: I3151c7848440ea6c240b959379a8eb369d35f3de
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5390
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-04-09 16:40:55 +02:00
Idwer Vollering a09dad0c77 asus/f2a85-m: conditionally show POST codes
Change-Id: I61e55601676c0825815d6520a874ccade8942379
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/5362
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-09 14:04:01 +02:00
Duncan Laurie 1a25c9cdfd lynxpoint: Fix SerialIO ACPI compile issue with recent IASL
The SerialIO DwordIo() definition is fixed up before returning
it in the serialio device _CRS method, so the values that are set
in the raw ASL are not actually used.

However modern versions of IASL do not like that the RangeLength is
set to zero and will fail to compile.  Set this value to 1 to make
IASL stop complaining, but the real value is still fixed up in _CRS
so this has no real effect on the end result.

Change-Id: Iceb888e54dd4d627c12d078915108a11f45b1a2d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/5182
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-09 13:59:16 +02:00
Paul Menzel 69813febbc sb/amd/amd8111/acpi.c: Remove set but unused variable `dword`
Removing `-Wno-unused-but-set-variable` from `CFLAGS` results in the error
below, when building for example the HP DL145 GL1.

	    CC         southbridge/amd/amd8111/acpi.ramstage.o
	src/southbridge/amd/amd8111/acpi.c: In function 'acpi_init':
	src/southbridge/amd/amd8111/acpi.c💯11: error: variable 'dword' set but not used [-Werror=unused-but-set-variable]

Removing the variable `dword` fixes this error.

The read is left in the code, as I do not know if it has an effect or
not.

Change-Id: I9957cef3a996c5974c275423c9de63ccf230974e
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5315
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-09 13:31:31 +02:00
Kyösti Mälkki dbc7bd9dce console: Refactor uart8250/NE2K
Do this for symmetry with romstage_console.c.

Change-Id: If17acfc3da07b1dbefa87162c3c7168deb7b354a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5330
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-09 13:28:33 +02:00
Kyösti Mälkki 77f43e9b43 console: Remove old fix for DEBUG_SMI
No longer needed as wrap_putchar() survives SMM relocation to TSEG.

Change-Id: I6143844b0b9902ef63baf3e5781a5dc4f54234be
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5335
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-09 13:26:48 +02:00
Kyösti Mälkki b04e0fff7d console: Simplify vtxprintf
We do not need ROMCC support here and using wrappers for
console_tx_byte we can simplify this code.

Change-Id: I7f3b5acdfd0bde1d832b16418339dd5e232627e7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5334
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-09 13:25:14 +02:00
Kyösti Mälkki 657e0be464 console: Move newline translation outside console_tx_byte
This gives us completely transparent low-level function to transmit
data.

Change-Id: I706791ff43d80a36a7252a4da0e6f3af92520db7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5336
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-09 13:21:25 +02:00
Kyösti Mälkki b3356bbff4 console: Add printk helper for ChromeOS
Do not expose console_tx_flush() to ChromeOS as that function
is part of lower-level implementation.

Change-Id: I1e31662da88a60e83f8e5d307a4b53441c130aab
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5347
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-09 13:21:13 +02:00
Kyösti Mälkki 56ae13983b console: Hide global console_loglevel
Change-Id: I7bdc468bc3f74516abb2c583bdb5b6d7555d987c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5333
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-09 11:38:12 +02:00
Kyösti Mälkki b2d2596714 console: Unify do_printk()
Change-Id: I6c50e47d9d2d0d1f42beee477e49b2a0054d1786
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5332
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-09 11:36:06 +02:00
Kyösti Mälkki 21333f96c7 console: Split console_init()
Splitting the version prompt satisfies some requirements ROMCC
sets for the order in which we include source files. Also GDB
stub will need console hardware before entering main().

Change-Id: Ibb445a2f8cfb440d9dd69cade5f0ea41fb606f50
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5331
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-09 11:34:06 +02:00
Kyösti Mälkki d53d96dddd OxPCIe uart: Move under drivers/uart
This driver is only a thin shell for uart8250mem and we could extend it
with further compatible PCI IDs from other vendors/brands.

Change-Id: Ic115b1baa0be0dbaa81e4a17a2e466019d3f4a67
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5329
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-09 11:30:53 +02:00
Kyösti Mälkki 4c686f2106 OxPCIe uart: Split PCI bridge control
None of the PCI bridge management here is specific to the PCI UART
device/function. Also the Kconfig variable defaults are not globally
valid, fill samsung/lumpy with working values.

Change-Id: Id22631412379af1d6bf62c996357d36d7ec47ca3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5237
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-09 11:29:45 +02:00
Kyösti Mälkki afa7b13b93 uart: Redefine Kconfig options
Option DRIVERS_UART builds with support for UART hardware.
Option CONSOLE_SERIAL enables the console output for UART.

Those x86 boards that do not have serial port on SuperIO should select
NO_UART_ON_SUPERIO to disable 8250 UART for the default configuration.

Removes:
  CONSOLE_SERIAL_UART
  HAVE_UART_IO_MAPPED
  HAVE_UART_MEMORY_MAPPED

Renames:
  CONSOLE_SERIAL8250     ->  DRIVERS_UART_8250IO
  CONSOLE_SERIAL8250MEM  ->  DRIVERS_UART_8250MEM

Change-Id: Id3afa05f85c0d6849746886db8b6c2ed6c846b61
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5311
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-09 11:24:43 +02:00
Kyösti Mälkki bbf6f3d384 console uart: Fill coreboot table entries
Also fixes the reported baudrate to take get_option() into account.

Change-Id: Ieadad70b00df02a530b0ccb6fa4e1b51526089f3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5310
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-09 11:19:27 +02:00
Kyösti Mälkki c2610a4a18 uart: Prepare to support multiple base addresses
Prepare low-level register access to take UART base address as a
parameter. This is done to support a list of base addresses defined
in the platform.

Change-Id: Ie630e55f2562f099b0ba9eb94b08c92d26dfdf2e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5309
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-09 11:13:03 +02:00
Patrick Georgi e5760af398 cpu/amd/car: Use define MSR_MCFG_BASE rather than hardcoded value
Change-Id: I0b40c9811115b204f1cae70546d236049c1b3d30
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5431
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-09 10:55:27 +02:00
Edward O'Callaghan 597cc45aa9 jetway/nf81-t56n-lf: Simplify agesawrapper_amdinitcpuio()
Follow same reasoning as:
12fd779 hp/pavilion_m6_1035dx: Simplify agesawrapper_amdinitcpuio()
Use coreboot variants for PCI and MSR access over AGESA's.

Change-Id: Ic0d8bbd0faf6423605567564ad216b79e1331cc9
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5472
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-09 07:13:43 +02:00
Alexandru Gagniuc b1e63e42e7 ec/compal/ene932/ec.h: Include stdint.h for definition of 'u8'
Change-Id: I7ffa8e8f807e7d8a778eb80c12a0dc984bdb3f8b
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5470
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2014-04-09 05:38:11 +02:00
Alexandru Gagniuc 0b2fa34d31 hp/pavilion_m6_1035dx/buildOpts.c: Remove commented out tables
Change-Id: I181da410490a92760ae1328a4286e805f5388886
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5462
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-04-09 05:25:21 +02:00
Konstantin Aladyshev 05ba1bb6d4 supermicro/h8qgi/dsdt: Move _PIC method to root scope
_PIC method should be declared under root scope (\_PIC),
otherwise Linux kernel doesn't use it.

Change-Id: I29b6ca60191507ac8edf99fdf173617bd6446934
Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru>
Reviewed-on: http://review.coreboot.org/5478
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-04-09 05:00:06 +02:00
Alexandru Gagniuc 12fd779176 hp/pavilion_m6_1035dx: Simplify agesawrapper_amdinitcpuio()
TRIVIAL. Rather than using the AGESA functions for PCI and MSR access,
use the coreboot variants, which are cleaner and more readable.

Change-Id: I4f24820606900e16f0d159df019f4560f1592489
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5468
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-04-09 04:59:14 +02:00
Idwer Vollering 7c1a49bcc0 SeaBIOS: have coreboot pass the choice to run optionroms in parallel
Introduce the tunable CONFIG_SEABIOS_THREAD_OPTIONROMS.

Change-Id: Ifd4d9fca7316eb739ff184e54bdc1cdb0262f0c6
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/5443
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-07 11:54:26 +02:00
Alexandru Gagniuc 011341d126 hp/pavilion_m6_1035dx: Remove inexistent devices from devicetree
This removes ominous "PCI: xx:xx.x not found" messages from coreboot
console.

Change-Id: I13a6f2497c04464e8dd0c4c5e7f40a1582f7f26c
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5461
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-04-07 01:40:37 +02:00
Idwer Vollering fa02e16c76 asus/f2a85-m: Sanitize #includes
Based on the same reasoning as this commit:
1d87dac hp/pavilion_m6_1035dx: Sanitize #includes

Change-Id: I383f79b5392ee1ca244e403f755213fa7b32c0af
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/5420
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-04-06 18:18:46 +02:00
Rudolf Marek 6181e3dcd7 amd/agesa/hudson: Implement PNP resource setup in LPC bridge
The previous SBxxx generations were setting up LPC bridge based
on the PNP resources. Implement it also for AGESA Hudson.
The AGESA itself opens one big region DFLT_SIO_PME_BASE_ADDRESS
(512 bytes). Make the code smart enough to detect already used
region and if any resource fits into AGESA defined region, do nothing.

Change-Id: I718d034bc4c778697a7bd0506d4550c8f5a43159
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/4497
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-04-06 18:03:52 +02:00
Edward O'Callaghan 4f5a5254c5 superio/winbond/w83627thg: Avoid .c includes
Following the same reasoning as commit
d304331 superio/fintek/f81865f: Avoid .c includes
Clean up the early_serial #include directives in mainboard/romstage
code.

Change-Id: I1f7c20ac7841874125b6bfcd9f9db25d96355881
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5449
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-06 06:23:08 +02:00
Edward O'Callaghan 5ff4b086ba jetway/nf81-t56n-lf: Sanitize #includes
Following the same reasoning as commit
1d87dac hp/pavilion_m6_1035dx: Sanitize #includes
Clean up the #include directives in this board support.

Change-Id: I97b73a349ca7e49b413d7c04900f25076488dde4
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5414
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-06 06:12:45 +02:00
Edward O'Callaghan 3c04917a00 superio/nuvoton/nct5104d: Avoid .c includes
Following the same reasoning as commit
d304331 superio/fintek/f81865f: Avoid .c includes
Clean up the early_serial #include directives in mainboard/romstage
code.

Change-Id: I14c438968bfed917977862efd8a393ec48cb04c9
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5446
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-06 06:08:37 +02:00
Edward O'Callaghan 793a429eb5 superio/winbond/w83627ehg: Avoid .c includes
Following the same reasoning as commit
d304331 superio/fintek/f81865f: Avoid .c includes
Clean up the early_serial #include directives in mainboard/romstage
code.

Change-Id: Ib3a12fb8160729008bdaa8026365675a11325da0
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5448
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-06 06:08:20 +02:00
Aaron Durbin 59674d25be chromeos: fix build breakage when !CHROMEOS_RAMOOPS
Needed types were being guarded by CONFIG_CHROMEOS_RAMOOPS.
Expose those unconditionally.

BUG=None
BRANCH=None
TEST=None

Change-Id: Ie858c746307ad3669eab5c35bf219e1a58da2382
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/188714
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/5453
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-05 00:28:26 +02:00
Alexandru Gagniuc eb3c9913dc x86/Makefile: Allow addition of link libraries for rom/ramstage
This is useful, for example, when using stage-independent code, as it
allows us to compile that code only once. It's also useful for vendor
code which needs wonky compiler definitions and include paths which
we'd rather not include in the other files.

Subsequent patches will make use of this when lib-izing AGESA.

Change-Id: Ifb0c5d353bf09d23864270b9eefb6b75fd86e6cb
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5425
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2014-04-04 18:58:38 +02:00
Alexandru Gagniuc 1d87dac4e4 hp/pavilion_m6_1035dx: Sanitize #includes
There were a number of things wrong with the includes. First, The
includes did not use paths to AGESA files, thus relying on the
compiler include paths to find the correct file. This made it unclear
where the file included was located, and whether it was local, under
vendorcode, or under a different directory. Instead, use full paths
for each non-local include.

Second, the local includes were mixed with the rest, making it unclear
which file is local and which one is not. Keep the local includes at
the top. This also prevents us from polluting the namespace of local
headers, with library definitions, and allows us to catch if we missed
an otherwise needed external header.

Thirdly, alphabetize the order of includes where possible.

Change-Id: I22c543291beabb83c16d912ea0a490be6ca4e03c
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5412
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-03 20:19:22 +02:00
Kyösti Mälkki cb3ba5fdbc lenovo/x60: Remove duplicate console_init()
For romstage, console_init() was called twice. The one in dock_connect()
should have done only UART programming and not touch CBMEM console and/or
USBDEBUG when those are enabled.

Second case where dock_connect() is called is in SMI handler.
If DEBUG_SMI is not enabled, console_init() does nothing in SMM.
If DEBUG_SMI is enabled, console_init() is already called every time when
enterining SMM.

Change-Id: Ib3a842442cb7a5be9d6b71682cd6f368930af886
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5433
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-04-03 10:04:19 +02:00
Edward O'Callaghan c814be4158 amd/agesa/s3_resume: Make compiler agnostic.
Clang does not like inline functions defined in C files with prototypes
in headers. Rather Clang expects inline function bodies to be in headers
if they are to be used out of scope. Since inline is purely advisory to
the compiler, drop its usage here.

Change-Id: I08a7a3d2cdf841ffbab10c017c75917768aac209
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5429
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2014-04-03 10:00:52 +02:00
Edward O'Callaghan a270586d4b superio/fintek/f71859: Avoid .c includes
Following the same reasoning as commit
d304331 superio/fintek/f81865f: Avoid .c includes
Clean up the early_serial #include directives in mainboard/romstage code.

Change-Id: I3577ca3f761fb699dc51141a02e1f853bf1f1a21
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5417
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-02 01:08:32 +02:00
Edward O'Callaghan b5a49ad9d7 superio/fintek/f71889: Avoid .c includes
Following the same reasoning as commit
d304331 superio/fintek/f81865f: Avoid .c includes
Clean up the early_serial #include directives in mainboard/romstage code.

Change-Id: Id8a1a2e8c87add636af1506598c2669d72dc3238
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5437
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-02 01:08:19 +02:00
Edward O'Callaghan 880e5248dc superio/fintek/f71872: Avoid .c includes
Following the same reasoning as commit
d304331 superio/fintek/f81865f: Avoid .c includes
Clean up the early_serial #include directives in mainboard/romstage code.

Change-Id: Ia021229154dc90b830a314f3adc2a0dd444bd68d
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5436
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-02 01:08:09 +02:00
Edward O'Callaghan ade70a0482 superio/fintek/f71863fg: Avoid .c includes
Following the same reasoning as commit
d304331 superio/fintek/f81865f: Avoid .c includes
Clean up the early_serial #include directives in mainboard/romstage code.

Change-Id: I863c16634873224c17e43100271e9b91419724d0
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5435
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-02 01:07:57 +02:00
Edward O'Callaghan fbdc3ef7d9 superio/fintek/f71805f: Avoid .c includes
Following the same reasoning as commit
d304331 superio/fintek/f81865f: Avoid .c includes
Clean up the early_serial #include directives in mainboard/romstage code.

Change-Id: Ibf743f7a5dd4a424a4513014fc9a896b87ecf3b1
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5434
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-02 01:07:27 +02:00
Aaron Durbin 905bfb05dc x86: use car_(get|set)_var accessors for apic timer
The timer_fsb variable was not correctly being accessed in the
presence of cache-as-ram. The cache-as-ram backing store could
be torn down but then udelay() could be called causing hangs from
accessing variables that have unknown values.

Instead change the timer_fsb variable to g_timer_fsb and obtain
the value through a local access method that does the correct things
to obtain the correct value.

Change-Id: Ia3e30808498cbe4a7f6f116c17a8cf1240a807a3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5411
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2014-04-01 14:31:36 +02:00
Kyösti Mälkki deb2cb27e9 Static CBMEM / CAR: Flag boards with BROKEN_CAR_MIGRATE
Use of CAR_GLOBAL is not safe after CAR is torn down, unless the
board properly implements EARLY_CBMEM_INIT.

Flag vulnerable boards that only do cbmem_recovery() in romstage on S3
resume and implementation with Intel FSP that invalidates cache before
we have a chance to copy the contents.

Change-Id: Iecd10dee9b73ab3f1f66826950fa0945675ff39f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5419
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-04-01 11:36:00 +02:00
Edward O'Callaghan d3043313a9 superio/fintek/f81865f: Avoid .c includes
We should not be #include .c files, instead link early_serial into
romstage and provide a prototype.

Change-Id: Ia9277169ce1592e1fc72f8849f0982741daec567
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5416
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-03-31 01:05:40 +02:00
Alexandru Gagniuc 01c44000be cubieboard: Enable the SD controller and mux SD pins
This step needs to be done before calling any MMC functionality.

Change-Id: I88763072c8a541ddba794e79fb55e82eb2f187a9
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4745
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-03-29 22:28:44 +01:00
Alexandru Gagniuc fccfee3bce mainboard/hp: Add initial support for Pavilion m6-1035dx
This was a pathetically easy port, where all the components are
already supported. This is basically a verbatim copy of amd/parmer.
The EC is an ENE KB932, which is a part that does surprisingly little
for an EC. This also means we need almost no code to get it working.
I've "select"ed the EC in Kconfig, which is the only difference from
parmer, although the keyboard worked fine without it.

I haven't coupled in the ACPI code from the EC yet, so battery level
is not readable from the OS. Hotkeys work except for brightness
control, and the CapsLock LED blinks at regular intervals instead of
following the CapsLock key.

Change-Id: Idfec6f848b99a52e73eac22d516f3550477ad822
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5409
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-28 20:59:57 +01:00
Paul Menzel 35a4901d3a mainboard/*/*/ec.c: Do not include `chromeos/chromeos.h`
It's not needed and causes build failures without CONFIG_CHROMEOS.

Change-Id: I7923717bfc5c84698044008e5f2441206041e0dd
Reported-by: Idwer Vollering <vidwer@gmail.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5398
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-03-28 19:28:31 +01:00
Edward O'Callaghan 024822f26d mainboard/jetway/nf81-t56n-lf: Enable ACPI S3 support in Kconfig
Switch on ACPI suspend/resume support which now works after many cycles.

Change-Id: I94a9bc9f23c2b4482d940018d542ab89e6c76f09
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5406
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-03-26 13:15:13 +01:00
Edward O'Callaghan 1547ef2362 mainboard/jetway/nf81-t56n-lf: Turn on PME in devicetree.cb
Change-Id: Ia58994d14ebf488a9200b02ec7af9c71ef4de9e6
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5401
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-24 07:10:55 +01:00
Aaron Durbin 3eb8eb7eba rmodules: use rmodtool to create rmodules
Start using the rmodtool for generating rmodules.
rmodule_link() has been changed to create 2 rules:
one for the passed in <name>, the other for creating
<name>.rmod which is an ELF file in the format of
an rmodule.

Since the header is not compiled and linked together
with an rmodule there needs to be a way of marking
which symbol is the entry point. __rmodule_entry is
the symbol used for knowing the entry point. There
was a little churn in SMM modules to ensure an
rmodule entry point symbol takes a single argument.

Change-Id: Ie452ed866f6596bf13f137f5b832faa39f48d26e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5379
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2014-03-20 23:55:55 +01:00
Edward O'Callaghan 8089f17806 mainboard/lenovo/x230 Fix usage of GNU field designator extension
In C99 we defined a syntax for this. GCC's old syntax was deprecated.

Change-Id: If8c53b5370be9101b9e5f2dfa88a6229f500a0f6
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5392
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-03-17 19:14:30 +01:00
Idwer Vollering 5809a7395d Make POST device configurable.
Change-Id: If92b50ab3888518228d2d3b76f5c50c4aef968dd
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/4561
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-03-16 21:42:49 +01:00
Edward O'Callaghan ed2bcaa731 mainboard/jetway/nf81-t56n-lf: Fix HWM base addr.
The target board has a different base addr. for its hardware
monitor (fans, temp, etc) from the Fintek Super I/O datasheet.

Change-Id: Ifc025cb92d0fc4e8f813091d00a6c87deae05863
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5383
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-13 20:25:44 +01:00
Edward O'Callaghan 236cf47513 mainboard/jetway/nf81-t56n-lf: Remove hard-coded IMC fan craft.
Fan controls in 0x400-0x4ff are not programmed here. Thus fan
control from amd/persimmon in the devicetree.cb does not apply
to this board.

Change-Id: I9156143476df0a7b44c7af90fa2107e8a8ba851e
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5381
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-13 20:25:22 +01:00
Chris Douglass b34739b4b0 drivers/spi: Add support for adesto SPI flash parts
Adds support for the following Adesto Technologies
SPI Flash parts.

AT25DF081
AT25DF321
AT25DF641

It has been tested on an Orion VPX7654 board populated
with an AT25DF321A part. The "08" and "64" densities have not
been tested.

These parts are the successors of the Atmel AT26DF line that
was spun out or purchased by Adesto.

In this patch, adesto.c is identical to winbond.c with part
entries for the Adesto parts. The datasheet for the AT25DF parts
includes a "100MHz" programming command in addition to the "85MHz"
command that is currently used but this patch does not add support
for that enhanced programming mode.

Change-Id: If82d075fd9000030480c412c645dcae2c8bb7439
Signed-off-by: Christopher Douglass <cdouglass.orion@gmail.com>
Reviewed-on: http://review.coreboot.org/5225
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-12 01:03:31 +01:00
Aaron Durbin 06ece7de93 chromeos: provide option to dynamically allocate ram oops buffer
Fixing the location of the ram oops buffer can lead to certain
kernel and boot loaders being confused when there is a ram
reservation low in the address space. Alternatively provide
a mechanism to allocate the ram oops buffer in cbmem. As cbmem
is usually high in the address space it avoids low reservation
confusion.

The patch uncondtionally provides a GOOG9999 ACPI device with
a single memory resource describing the memory region used for
the ramoops region.

BUG=None
BRANCH=baytrail,haswell
TEST=Built and booted with and w/o dynamic ram oops. With
     the corresponding kernel change things behave correctly.

Change-Id: Ide2bb4434768c9f9b90e125adae4324cb1d2d073
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5257
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-11 21:37:36 +01:00
Duncan Laurie e7e78d61a9 baytrail: Reserve memory between ASEG and 1MB and for ramoops
Low system tables are in this region, and it is probably safer
to keep ASEG reserved.

Also keep the region used by ramoops from being used by the OS
and from being cleared by developer mode boots.

Lots more work needed to make the ACPI tables fully functional.

BUG=chrome-os-partner:23505
BRANCH=rambi
TEST=boot on rambi and see that the kernel finds RSDP and uses ACPI

Change-Id: I4f7064d3cff14a3ecf15b194a1f20c1fa9d5e134
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175554
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4932
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-03-11 19:56:17 +01:00
Duncan Laurie 714b1e8b6c rambi: Enable USB boot with EHCI controller
This adds the EHCI driver back to libpayload and configures
the devicetree to route ports to EHCI.

This is hopefully just temporary until the issues with XHCI
can be worked out.

BUG=chrome-os-partner:23635
BRANCH=rambi
TEST=build and boot from USB on rambi

Change-Id: I0549661f5e5fd83477f4839a05e7e21175b24b64
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175513
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4931
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-11 19:55:58 +01:00
Duncan Laurie 3c9f17462a baytrail: Add EHCI initialization
This adds required steps to initialize the EHCI controller
on the baytrail platform.

BUG=chrome-os-partner:23635
BRANCH=rambi
TEST=build and boot from USB on rambi

Change-Id: I3a5487791e2305616036d4550e260a178c0e1c4d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175512
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4930
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-11 19:55:30 +01:00
Duncan Laurie f81a91a768 baytrail: Add XHCI initialization
This adds required steps to initialize the XHCI controller
on the baytrail platform.

Actually using XHCI is causing lots of bad behavior including
apparent memory corruption.

BUG=chrome-os-partner:23635
BRANCH=rambi
TEST=build and boot on rambi

Change-Id: Ic43e04f4b47e107ec3bb0c387a9fc72c3cae0271
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175511
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4929
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-11 19:55:12 +01:00
Aaron Durbin 97651c55a3 baytrail: add audio clock workaround for LPE
Apparently the LPE device needs a 25MHz clock. Provide
the work around to enable this clock.

BUG=chrome-os-partner:23791
BRANCH=None
TEST=Built and booted. Confirmed setting being applied.

Change-Id: Ibff5563436b3025eb8b61ffee3302bd2da872b39
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175493
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4928
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-11 19:54:58 +01:00
Aaron Durbin 65ad521f8a baytrail: add ccu iosf access functions
The clock control unit needs to be accessed to configure
some of the devices properly. Therefore. provide a way
to access the CCU.

BUG=chrome-os-partner:23791
BRANCH=None
TEST=Built.

Change-Id: I30ed06e6aef81ee99c6d7ab3cbe8f83818b8dee5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175492
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4927
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-11 19:54:04 +01:00
Aaron Durbin 46ab8cdc68 baytrail: HDA function disable workaround
Parts of the audio path are common between the HDA and LPE.
However, those parts are power-controlled by the D-state of
the HDA device. Therefore, one cannot put the HDA into D3Hot
because those audio paths will be shutdown.

BUG=chrome-os-partner:22871
BRANCH=None
TEST=Built and booted through depthcharge. Disabling HDA still
     causes a shutdown when performing warm reset, however I
     was able to verify the magic sequence was being performed.

Change-Id: I3b01356d85a4b7b902bd896b8eb9e7bc509fcc42
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175491
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4926
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-11 19:53:51 +01:00
Aaron Durbin 1eae3eed29 baytrail: allow function disable on TXE
Previously it was not known how to put the TXE pci device
into D3Hot. It's been disseminated that this is not a requirement
for disabling the TXE pci device in the function disable register.
Therefore, allow this by returning 0 from place_device_in_d3hot().

BUG=chrome-os-partner:22871
BRANCH=None
TEST=Temporarily set TXE to be disabled. Noted FUNC_DIS was being
     set accordingly.

Change-Id: Ibf537bf8ba718859591dc89bdf41e57c1ea9d836
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175490
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4925
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-11 19:53:17 +01:00
Duncan Laurie 223d4a4ff6 baytrail: Switch graphics init to use reg_script
This is an example consumer of the register script handler.

BUG=chrome-os-partner:23507
BRANCH=rambi
TEST=build and boot on rambi and see recovery screen

Change-Id: I4954a5defd0a345b179819b9f6bb15ea340a6715
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175214
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4924
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-11 19:52:06 +01:00
Aaron Durbin 4e6ad1bcaf rmodule: allow rmodule header structure to be used by userland
In order for userland to create rmodules the common code should be
shareable.  Therefore, convert the short u<width> name types to the
posix uint<width>_t types. Additionally, move the definition of the
header structure to a new rmodule-defs.h header file so that userland
can include that without pulling in the coreboot state.

Change-Id: I54acd3bfd8c207b9efd50a3b6d89efd5fcbfc1d9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5363
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-11 19:42:15 +01:00
WANG Siyuan 62a3f6f665 AMD Olive Hill: add IMC fan control
There are 3 steps to enable the IMC fan control:
1. Enable fan control related registers on Hudson using oem_fan_control().
2. Set EcStruct.
3. Enable thermal zone using enable_imc_thermal_zone().
I have tested on Olive Hill.

Change-Id: I1748e8c92fb72a82bac0506ecdf98304a5bd8239
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/4301
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-03-10 18:07:53 +01:00
WANG Siyuan d5813530fa AMD Parmer: add IMC fan control
There are 3 steps to enable the IMC fan control:
1. Enable fan control related registers on Hudson using oem_fan_control().
2. Set EcStruct.
3. Enable thermal zone using enable_imc_thermal_zone().
I have tested on Parmer.

Change-Id: Id11d5c5da30346c034d155a73749e7f4c9c980eb
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/4302
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-03-10 18:06:09 +01:00
Kyösti Mälkki 7841ece730 CBMEM console: Fix build for ARM
This preprocessor guard was used to disable CBMEM console from
romstage of ROMCC boards. It unintentionally disabled it for ARM
too as they do not have CACHE_AS_RAM selected.

Option EARLY_CBMEM_INIT implies CAR migration which is required
to have CBMEM console in romstage. This change should have been
done in commit f8bf5a10 already, but we missed it.

Change-Id: I03e95183be0e78bc7dd439d5fef5b10e54966dc3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5356
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-03-10 15:30:44 +01:00
Vladimir Serbinenko afc62a7631 intel/gma: Remove MCH register declarations.
i915_reg.h re-declares some of MCH registers as seen through MCHBAR mirror.
It's not currently used and we don't want any MCH registers in GFX.

Change-Id: I5fa4711fee60d64316696b7ed713013de8759b54
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5318
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-09 21:22:15 +01:00
Vladimir Serbinenko 47089f29f0 smbios: Supply tag type 2 (base board information)
Information really contained in it is mostly the same as in type 1 tag.
However Linux uses type 2 to match hardware. Duplicate the info.

Change-Id: I75e13d764464053ecab4a833fbb83836cedf26e6
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5322
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-09 21:21:46 +01:00
Edward O'Callaghan b66d53ac10 mainboard/jetway/nf81-t56n-lf: Turn PS/2 driver on by default.
This board has a working PS/2 port for a keyboard. Thus, it
makes for a good option to have on by default.

Change-Id: Ifcde0474d7be26152f1b5e19fe4906e87732b9a4
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5357
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-09 16:20:09 +01:00
Edward O'Callaghan bfa29dc021 mainboard/jetway/nf81-t56n-lf: Fix GPP missing CLK on PCI bridge.
The platform dependent mainboard.c was incorrectly disabling the
second clock signal feeding the GPP ports. This results in
spurious hangs by calling the set_pcie_dereset() SB CIMx callback
many times. This also stops coreboot from finding the second NIC
behind the pci 15.0 bridge.

Change-Id: I9f2370f6e05d1c5532fbca8203e32ab1ff15266a
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5355
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-03-09 13:38:49 +01:00
Kyösti Mälkki 8340666cb1 intel/jarrell: Apply ROMCC workaround
Taken from intel/xe7501devkit, maybe it had same symptoms once.

The call to ich5_watchdog_on() has side-effect of exploding the
requirements for ROMCC internal arrays at compile-time. The hard-coded
limit in question is MAX_RHS in util/romcc.c, the default of 127 comes
from the rhs field defined with 7 bits.

Before this patch intel/jarrell builds were using upto MAX_RHS=102, while
other ROMCC boards built even with MAX_RHS=10. This workaround brings
intel/jarrell to the same level.

Change-Id: I162d801f81d9196403d88636eb9cb291c950ded0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5348
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-09 13:09:48 +01:00
Kyösti Mälkki 233f5b3b0e ROMCC: Trigger internal compiler failure and apply the workaround
These boards first failed when attempting to change print_err() from
direct function call to console_tx_XX() to a code block in the form of

 do { if (y) console_tx_XX(x); } while(0)

Removing the label dummy_romcc_workaround_label added here will
trigger the following compiler error for the two boards:

  Internal compiler error: no edge to block->last->next

Change-Id: I997adfaf586d7fa2096401dd574b07ce676d0ac6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5349
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-08 19:24:22 +01:00
Patrick Georgi 946923b0fb qemu-i440fx: add a prototype for main()
This probably belongs elsewhere, but I haven't found a nice place yet.

Change-Id: I9ca52db33905cf4ee229d7ff44012105915271a8
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/4720
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-03-08 15:05:53 +01:00
Paul Menzel 1386d5ccb0 lib/dynamic_cbmem.c: Include `cbmem_console.h`
Broken with commit 1d7541fe (console: Fix includes).

Change-Id: If41f9e08df98d79b7bbf740b1a5634d0140207be
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5351
Tested-by: build bot (Jenkins)
2014-03-08 13:06:34 +01:00
Aaron Durbin c34713d33e x86: add MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING option
Boot speeds can be sped up by mirroring the payload into
main memory before doing the actual loading. Systems that
would benefit from this are typically Intel ones whose SPI
are memory mapped. Without the SPI being cached all accesses
to the payload in SPI while being loaded result in uncacheable
accesses. Instead take advantage of the on-board SPI controller
which has an internal cache and prefetcher by copying 64-byte
cachelines using 32-bit word copies.

Change-Id: I4aac856b1b5130fa2d68a6c45a96cfeead472a52
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5305
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-07 15:30:27 +01:00
Duncan Laurie 7274800ea3 Add a generic register script handler
This is based on the RCBA configuration setup from haswell.
It handles PCI, BARs, IO, MMIO, and baytrail-specific IOSF.
I did not extend it to handle MSR yet but that would be another
potential register type.

There are a number of approaches to this kind of thing, but in the
end they have a lot of switch statements and a mass of #defines.
I'm not particularly set on any of the details so comments welcome.

BUG=chrome-os-partner:23635
BRANCH=rambi
TEST=emerge-rambi chromeos-coreboot-rambi

Change-Id: Ib873936ecf20fc996a8feeb72b9d04ddb523211f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175206
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4923
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-04 16:31:14 +01:00
Kyösti Mälkki 0567c91b22 console: Use single driver entry for UARTs
UARTs now have unified prototypes and can use a single entry
in the list of drivers for ramstage.

Change-Id: I315daaf9a83cfa60f1a270146c729907a1d6d45b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5308
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04 15:40:34 +01:00
Kyösti Mälkki ab94bbf072 usbdebug: Move Kconfig under drivers/usb
This menu may become a bit more complicated with addition of
new USB hardware so move it out of console/.

Change-Id: Ieb330675b9227a3e53d093f7c2b5a65e3842dc82
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5307
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-04 15:38:12 +01:00
Kyösti Mälkki 9c479c9a3e SMM: Only have console with DEBUG_SMI
Existing code compiled serial communication and printk() for SMM
even when DEBUG_SMI was not selected.

Change-Id: Ic5e25cd7453cb2243f7ac592b093fba752a299f7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5142
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-03-04 15:36:27 +01:00
Kyösti Mälkki bea6bf07df uart8250: Move under drivers/uart
Change-Id: Ic65ffaaa092330ed68d891e4a09a8b86cdc04a3a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5236
Tested-by: build bot (Jenkins)
2014-03-04 15:34:27 +01:00
Kyösti Mälkki 2b95da01e6 uart8250mem: Unify calls with generic UART
NOTE: UART base for SMM continues to be broken, as it does not use
the address resource allocator has assigned.

Change-Id: I79f2ca8427a33a3c719adfe277c24dab79a33ef3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5235
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04 15:28:41 +01:00
Kyösti Mälkki 4770749edc uart8250io: Unify calls with generic UART
Change-Id: I6d56648e56f2177e1d5332497321e718df18300c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5234
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04 15:27:53 +01:00
Kyösti Mälkki 1d7541feeb console: Fix includes
Do not pull in console hw-specific prototypes everywhere
with console.h as those are not needed for higher levels.

Move prototypes for UARTs next to other consoles.

Change-Id: Icbc9cd3e5bdfdab85d7dccd7c3827bba35248fb8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5232
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04 15:26:08 +01:00
Kyösti Mälkki 7e75f20477 pl011 UART: Move under drivers/uart
Currently this is only a minimal stub to get console on qemu-armv7.

Change-Id: I3f20b7f944bc7d0e5ace9d22198d4c16a3839d2c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5162
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04 15:25:15 +01:00
Kyösti Mälkki 2cbcd2b710 ti/am335x: Fix baudrate calculation
UART input clock is platform dependent. Also account for possible
use of get_option() where baudrate is not compile-time constant.

The hardware reference on BeagleBone is from a 48 MHz oscillator input.
With pre-divisor of 16 we get same register values as in table 19-25.

Change-Id: I89aee27c958f8618ce79a968ae7520a867e7e8a2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5290
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04 15:24:50 +01:00
Kyösti Mälkki 65ba20e17b allwinner/a10: Fix baudrate calculation
UART input clock is platform dependent. Also account for possible
use of get_option() where baudrate is not compile-time constant.

Change-Id: Ie1c8789ef72430e43fc33bfa9ffb9f5346762439
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5289
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04 15:24:32 +01:00
Kyösti Mälkki c5332e30da samsung/exynos5: Fix baudrate calculation
Account for possible use of get_option() when baudrate is no longer
compile-time constant.

Change-Id: Ib45acd98e55c5892dbce9903830665aefeda5be0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5288
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04 15:24:10 +01:00
Kyösti Mälkki 919923def3 option: Add arch-agnostic get_option()
We should not have pc80/ includes in console/.

Change-Id: Id7da732b1ea094be01f45f9dbb49142f4e78f095
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5157
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04 15:23:10 +01:00
Kyösti Mälkki 3ee1668ab4 uart8250: Fix and unify baudrate divisor calculation
Divisor is a function of requested baudrate, platform-specific
reference clock and amount of oversampling done on the UART reference.
Calculate this parameter with divisor rounded to nearest integer.

When building without option_table or when there is no entry for
baud_rate, CONFIG_TTYS0_BAUD is used for default baudrate.

For OxPCIe use of 4 MHz for reference was arbitrary giving correct
divisor for 115200 but somewhat inaccurate for lower baudrates.
Actual hardware is 62500000 with 16 times oversampling.

FIXME: Field for baudrate in lb_tables is still incorrect.

Change-Id: I68539738469af780fadd3392263dd9b3d5964d2d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5229
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04 15:22:08 +01:00
Kyösti Mälkki c76b3d6cca uart: Drop HAVE_UART_MEMORY_MAPPED
This option is used to make uart8250mem option visible in menuconfig.
Showing it for these ARMs is incorrect.

Change-Id: I2c28e1c3781df41c09c365355a5105c9fe4945ed
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5259
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04 15:19:28 +01:00
Kyösti Mälkki a172ea5469 uart: Do not guard entire include file by config options
Do not guard the file by CONFIG_CONSOLE_SERIAL8250 or
CONFIG_CONSOLE_SERIAL8250MEM or CONFIG_CONSOLE_SERIAL.

Don't do indirect includes for <uart8250.h>.

The config-specific options are already properly guarded, and there
is no need to guard the register and bit definitions.

Change-Id: I7528b18cdc62bc5c22486f037e14002838a2176e
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4585
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04 15:18:27 +01:00
Edward O'Callaghan 93fa422dea jetway/nf81-t56n-lf: Minor corrections to devicetree.cb
The miniPCIe ports hanging off 15.0 are infact x1, as are the two
onboard NIC's on 6.0 and 15.0.

Change-Id: I6247838f6b5823369543e338975a4c5c6fd00d7c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5328
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-04 15:01:34 +01:00
Edward O'Callaghan ba88506812 jetway/nf81-t56n-lf: Fix PS/2 ACPI for KBC & Mouse.
Provide ACPI table node so that the PS/2 keyboard/mouse port works
in GNU/Linux.

Change-Id: If73b8d37a81bb9066cbcc650b518d25e243b84e7
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5327
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-04 15:00:19 +01:00
Vladimir Serbinenko 131573056f nehalem: Replace video init.
Old video init just replayed the sequence.
This one actually computes the values.

Change-Id: Ic1fe7a2e90dc2cc36ac0d8bcea5cfabc583f09a3
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5270
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-04 00:41:05 +01:00
Vladimir Serbinenko 1b12ef1ac3 drivers/intel/gma: Add EDID retrieving functions.
Change-Id: I64f2fcc5ad52d6a0188d02b28769001ada718c4f
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5278
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-03-04 00:40:50 +01:00
Vladimir Serbinenko 42c4a9df29 bd82x6x, ibexpeak, lynxpoint: Unify SPI.
SPI registers didnt change since ICH8. No need to have separate
files for them. Unify.

Change-Id: I4e2ac3221b419c007e135c9ee615fc3b84424cbc
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5254
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-04 00:00:57 +01:00
Vladimir Serbinenko 83ef74992a ibexpeak/ehci: Set .enable_resources properly.
Without this memory decoding isn't activated which, in turn,
makes SeaBIOS crash.

Change-Id: I3dcc721b500ab7468e1082157eeeed38044462d0
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5326
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-03-04 00:00:20 +01:00
Aaron Durbin 3f7ad7b216 coreboot: don't return struct lb_memory * from write_tables()
No one is interrogating the write_tables() return value. Therefore,
drop it.

Change-Id: I97e707f071942239c9a0fa0914af3679ee7a9c3c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5301
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-03-03 23:25:53 +01:00
Vladimir Serbinenko b013c279a9 nehalem: Remove SSKPD.
Not really used and conflicts with SSKPD from i915_regs.h

Change-Id: I1462457f656310df99e78aee8cbfe0206f6e2a1e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5268
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-03 23:14:26 +01:00
Vladimir Serbinenko db7d04d1b7 qemu: Support textmode gfx init.
Change-Id: I8b6b14b4fcf8df21d8bbf988d640b1efa013bd7f
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5283
Tested-by: build bot (Jenkins)
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-03-03 23:14:04 +01:00
Vladimir Serbinenko 160e9a0224 devices: Allow to configure textmode in native gfx init.
Usefull to select between text mode which offers best compatibility with
payloads and gfx mode which makes the best-looking screen.

Also right now we have an unfortunate situation when qemu is in gfx mode
while most real systems use text mode.

Change-Id: Ifad7ba197875edfdd06eb932afeb5800229ef055
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5282
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-03 23:13:17 +01:00
Edward O'Callaghan 4bab5824e1 lib/selfboot: s_srcaddr is uninitialized.
s_srcaddr is uninitialized in the BSS section, leading to a
garbage valued operand on the LHS of a '<' on line 383.

Change-Id: Ie4fec91b09c70fb1d91ad3918ac3f60653fa1d83
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5314
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-03-03 22:29:56 +01:00
Aaron Durbin 2d5cec6401 coreboot: remove unused get_lb_mem() function
The get_lb_mem() is no longer used. Therefore, remove it.

Change-Id: I2d8427c460cfbb2b7a9870dfd54f4a75738cfb88
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5304
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-03 21:47:55 +01:00
Aaron Durbin ceebc0503f selfboot: use bootmem infrastructure
Instead of packing and unpacking entries in lb_mem use
the bootmem infrastructure for performing sanity checks
during payload loading.

Change-Id: Ica2bee7ebb0f6bf9ded31deac8cb700aa387bc7a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5303
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-03 21:47:40 +01:00
Aaron Durbin 4904802efc coreboot: introduce notion of bootmem for memory map at boot
The write_coreboot_table() in coreboot_table.c was already using
struct memrange for managing and building up the entries that
eventually go into the lb_memory table. Abstract that concept
out to a bootmem memory map. The bootmem concept can then be
used as a basis for loading payloads, for example.

Change-Id: I7edbbca6bbd0568f658fde39ca93b126cab88367
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5302
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-03 21:47:27 +01:00
Vladimir Serbinenko c7db28c580 intel/nehalem: Fix soft reset detection.
Change-Id: I4575cddc35dc8309372beafec441d194bc145242
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5267
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-03-03 21:09:14 +01:00
Vladimir Serbinenko e1eef694ea intel/nehalem: Use non-powercycle reset.
Change-Id: Ibc2421a50e272a580461e4eacec6cfcd38654fe8
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5266
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-03-03 21:04:12 +01:00
Vladimir Serbinenko 9817a37416 nehalem/raminit: Don't touch clock generator in raminit.
Clock generator is mobo-specific. Don't touch it in raminit.

Change-Id: Ie114696b7fb13b8daee8dd1393d43bc609e149b3
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5265
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-03-03 20:55:26 +01:00
Aaron Durbin 7d1996cc4a coreboot: introduce arch_payload_run()
The selfboot() function relied on global variables
within the selfboot.c compilation unit. Now that the
bounce buffer is a part of struct payload use a new
architecture-specific arch_payload_run() function
for jumping to the payload. selfboot() can then be
removed.

Change-Id: Icec74942e94599542148561b3311ce5096ac5ea5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5300
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-03-03 19:50:32 +01:00
Aaron Durbin e58a24b1b5 selfboot: store bounce buffer in struct payload
In order to break the dependency on selfboot for jumping to
payload the bounce buffer location needs to be communicated.
Therefore, add the bounce buffer to struct payload.

Change-Id: I9d9396e5c5bfba7a63940227ee0bdce6cba39578
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5299
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-03-03 19:50:10 +01:00
Aaron Durbin 6086e63a79 coreboot: use struct payload for selfload()
In order to encapsulate more data for self loading use struct
payload as the type. That way modifications to what is needed
for payload loading does not introduce more global variables.

Change-Id: I5b8facd7881e397ca7de1c04cec747fc1dce2d5f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5298
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-03-03 19:49:57 +01:00
Aaron Durbin 1322d7f9d5 coreboot: move common code to payload_run() from selfboot()
The selfboot() routine was perfoming most of the common teardown
and stack checking infrastructure. Move that code into
payload_run() to prepare removal of the selfboot() function.

Change-Id: I29f2a5cfcc692f7a0fe2656cb1cda18158c49c6e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5297
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-03 19:49:40 +01:00
Aaron Durbin bdf913ab01 coreboot: unify infrastructure for loading payloads
A payload can be loaded either from a vboot region or from cbfs.
Provide a common place for choosing where the payload is loaded
from. Additionally, place the logic in the 'loaders' directory
similarly to the ramstage loader infrastructure.

Change-Id: I6b0034ea5ebd04a3d058151819ac77a126a6bfe2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5296
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-03-03 19:48:02 +01:00
Edward O'Callaghan 9cd96b4096 vendorcode/amd/agesa/f*: Improve gcccar.inc assembler compatibility.
A comparison with a two's complement in gcccar.inc has dubious
GAS/AT&T notation. Clang miss-parses 0x-1 as an invalid hexadecimal
number.

Change-Id: I88baa5c2513f062ff309df05916a3832b9bd9bb1
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5277
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-03-02 05:37:26 +01:00
Vladimir Serbinenko 5ca914bc64 lenovo/x60: Unify volume button handling with common code.
Change-Id: I45fe44a91f9f83a510b204e01dbaff9e8a9696ca
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5099
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-03-01 21:59:15 +01:00
Chris Douglass e92155fbe6 intel/sandybridge: add PCI IDs for 6-Series PCH
The PCI ids are taken from:
	Intel® 6 Series Chipset and
	Intel® C200 Series Chipset
	Specification Update – NDA
	October 2013
	CDI / IBP#: 440377

Change-Id: Ib8418173fd36fd4109b3c4ec0d5543ca8e39ffa6
Signed-off-by: Christopher Douglass <cdouglass.orion@gmail.com>
Reviewed-on: http://review.coreboot.org/5226
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-01 06:51:08 +01:00
Vladimir Serbinenko 770c71f3ec lenovo/x201: Move mainboard init to mainboard_init.
Rather than having it inside mainboard_enable.

Change-Id: Ie8bd25eb49b919b4e25c4628e3557fc66b2ba4d9
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4840
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-01 00:45:28 +01:00
Chris Douglass f0e025a386 drivers/spi: Sort SPI flash files
Change-Id: Id7e65065556ca7225969ca0afdb21eda24aeb967
Signed-off-by: Christopher Douglass <cdouglass.orion@gmail.com>
Reviewed-on: http://review.coreboot.org/5260
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-02-28 21:13:47 +01:00
Aaron Durbin 4a082c669c baytrail: use common code for iosf accessors
The same sequence is used regardless of the port
being read or written. Therefore, use the same
implementation for reading or writing to a port.

BUG=None
BRANCH=None
TEST=Built and booted through depthcharge. Dev and recovery
     screens still work. Nothing bizarre in console output.

Change-Id: I1a64b54b50472fa7d601e199653eb4a76accf910
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175441
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4922
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-02-27 06:35:44 +01:00
Aaron Durbin bc69ae9823 baytrail: add lpss iosf functions and regs
The low power subsystem devices have a lot of their
configuration done in the IOSF sideband message space.
Add support for these access methods.

BUG=chrome-os-partner:23790
BRANCH=None
TEST=Built and booted through depthcharge.

Change-Id: I0dd52b952a16ef1280c29301164db041ee87f636
Signed-off-by: Aaron Durbin <adurbin@chromum.org>
Reviewed-on: https://chromium-review.googlesource.com/175440
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4921
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-02-27 06:35:25 +01:00
Duncan Laurie 92fce495a7 baytrail: Fix EHCI function number and XHCI typo
BUG=chrome-os-partner:23635
BRANCH=rambi
TEST=successfully disable EHCI controller in devicetree.cb

Change-Id: I8a22e25a9f7c263d2a6debf0cd1606cb0f6f7645
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175403
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4920
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-02-27 06:35:01 +01:00
Aaron Durbin a8e9b63166 baytrail: increment boot count for elog
The elog boot counter in cmos was not being initialized
nor incremented. Start doing that in romstage. Since S3
resume is not detected yet the increment is unconditional.

BUG=None
BRANCH=None
TEST=Built and booted through depthcharge multiple times. Noted
     output such as 'Boot Count incremented to 4'.

Change-Id: Ic585d4ad4b3af086e0067e28fe0f35c02979bbd2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174717
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4919
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-02-27 06:34:41 +01:00
Aaron Durbin 6e77beec96 baytrail: add GNVS to cbmem and set acpi_slp_type
The ACPI code was previously complaining about not being able
to find the GNVS area: 'ACPI: Could not find CBMEM GNVS'. Fix
this by adding GNVS area early in start up. This is also the
appropriate place to set the acpi_slp_type variable to indicate
an S3 resume or not.

BUG=chrome-os-partner:22867
BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted through depthcharge. Noted cbmem has 'ACPI GNVS'
     entry.

Change-Id: Ifbca3dd390ebe573730ee204ca4c2f19626dd6b1
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174647
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4918
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-02-27 06:34:17 +01:00
Aaron Durbin 61cd57ba36 baytrail: fix uninitialized acpi structures
The callers of the following functions assume the storage
area provided by the pointers is initialized. That's not the
case as these were just place holders.
- void acpi_create_intel_hpet(acpi_hpet_t * hpet);
- void acpi_create_serialio_ssdt(acpi_header_t *ssdt);

To fix this properly initialize the hpet entry, and just remove
the serialio_ssdt function entirely.

BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted through depthcharge on rambi. Noted no more
     ACPI errors relating to invalid length.

Change-Id: If56ab033562ef2d755e9c9de42f507c95d291aba
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174716
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4917
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-27 06:34:05 +01:00
Duncan Laurie 0854c84735 baytrail: Add IOSF functions for USBPHY and USHPHY
These are needed for USB2 and USB3 PHY init sequences.

BUG=chrome-os-partner:23635
BRANCH=rambi
TEST=emerge-rambi chromeos-coreboot-rambi

Change-Id: Id284d882034e15eceeaa910b8b73bc0d8d895199
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175227
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4916
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-27 06:33:50 +01:00
Duncan Laurie 5d53554d41 rambi: Enable internal keyboard
The EC LPC init function needs to run to enable the internal keyboard.

I needed this to confirm that it is just USB keyboards that are causing
all sorts of issues.

BUG=chrome-os-partner:23635
BRANCH=rambi
TEST=boot to recovery screen and hit tab

Change-Id: Iea0fc66ba62ea7da71ef83c26e25ae32bef102bd
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175207
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4915
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-02-27 06:33:39 +01:00
Shawn Nematbakhsh a6151f4bfb rambi: Enable SATA port
Enable first SATA port in Rambi device tree.

BUG=chrome-os-partner:23643
TEST=TEST=Manual, in dev mode. Verify on rambi that SATA disk is
detected, and kernel is found + booted.

Change-Id: Ic0cb5f9ff17ca0f6cc7941f203b9338df200811d
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174916
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4914
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-02-27 06:33:26 +01:00
Shawn Nematbakhsh 1dbd0e224e baytrail: Add SATA driver
Add SATA driver for baytrail platform.

BUG=chrome-os-partner:23643
TEST=Manual, in dev mode. Verify on rambi that SATA disk is detected, and
kernel is found + booted.

Change-Id: I5c13e03203c8f26d233c7d10af8ff6812c460578
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174914
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4913
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-02-27 06:13:30 +01:00
Aaron Durbin 4477050e22 rambi: add all on-board devices
Add the on-board devices in the SoC to the device tree.
Also, disable the unused devices aside from TXE and HDA.
Those particular devices cause the system to shut down
when they are disabled.

BUG=chrome-os-partner:22871
BRANCH=None
TEST=Built and booted through depthcharge. Noted the calls to the
     southcluster disable function.

Change-Id: I482c1c9609833054aeb2948144af54b57d3df086
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174645
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4912
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-02-27 06:13:16 +01:00
Aaron Durbin d7bc23ac8e baytrail: add support for disabling south cluster pci devices
When the southcluster pci devices are listed in the devicetree add
the ability to perform the proper disabling sequence for turning
off devices. This only turns off the pci device interface as well
as put the device into D3Hot. It is not yet known how to put the TXE
device into D3Hot so it's currently not possible to disable that
device.

Also, expose the southcluster_enable_dev() function so that other
devices can call this if they require doing specific things before
disabling the device. The southcluster_enable_dev() is only called
on devices found in the devicetree and if they currently have no
ops associated with them.

BUG=chrome-os-partner:22871
BRANCH=None
TEST=Built and booted through depthcharge. Interrogated
     output to ensure devices were being properly disabled.

Change-Id: I537ddcb9379907af2fe012948542b6150a8bf7c5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174644
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4911
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-27 06:12:43 +01:00
Aaron Durbin 67633a558a baytrail: use MCRX in iosf access functions
While most registers accesses don't need the use of the MCRX
register (upper 24 bits of address) the MCRX register should
be protected. The reference code could be doing accesses to
registers that initialized the MCRX register. Thus, any access
after that should ensure the MCRX register is initialized
appropriately.

BUG=None
BRANCH=None
TEST=Verified assembly output. Also, built and booted through
     depthcharge.

Change-Id: I4d6cfbe6bb1666790c69778b8f2c8baeaf015264
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174643
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4909
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-27 06:12:25 +01:00
Vladimir Serbinenko cf6c9cc29c Kill ALT_CBFS_LOAD_PAYLOAD
Not used anymore.

Change-Id: Icf3a4a7f932776981048b805478582ad2b784182
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5132
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-02-25 20:03:49 +01:00
Vladimir Serbinenko 58fdb4fe15 lynxpoint: Kill alternative cbfs_load_payload.
With generic load using 32-bit accesses this is no longer has a
huge impact it previously did. It's also unnecessarily
component-speficific.

Change-Id: I7e8a74ea1ceaa225e1024f9eb43e7280773e2b5a
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5131
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-02-25 20:03:34 +01:00
Vladimir Serbinenko 4337020b95 Remove CACHE_ROM.
With the recent improvement 3d6ffe76f8,
speedup by CACHE_ROM is reduced a lot.
On the other hand this makes coreboot run out of MTRRs depending on
system configuration, hence screwing up I/O access and cache
coherency in worst cases.

CACHE_ROM requires the user to sanity check their boot output because
the feature is brittle. The working configuration is dependent on I/O
hole size, ram size, and chipset. Because of this the current
implementation can leave a system configured in an inconsistent state
leading to unexpected results such as poor performance and/or
inconsistent cache-coherency

Remove this as a buggy feature until we figure out how to do it properly
if necessary.

Change-Id: I858d78a907bf042fcc21fdf7a2bf899e9f6b591d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5146
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-25 00:57:35 +01:00
Paul Menzel 20f83d5656 intel/*/acpi: Increase range length of MCHBAR buffer to 32 kB
Linux kernel 2.6.31 reports the warning below on Intel Ivy Bridge (with
FSP).

	resource map sanity check conflict: 0xfed10000 0xfed17fff 0xfed10000 0xfed13fff pnp 00:01

Since Sandy Bridge the length of the MCHBAR is 32 kB and it is already
used that way in other places.

	$ more src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl
	[…]
	OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR, 0x8000)
	[…]

So instead of 16 kB specify that 32 kB are decoded in that memory
range for Intel Sandy Bridge, Ivy Bridge and Haswell.

(Linux kernel 3.10 does not warn about that.)

Change-Id: Ie7a9356d9051c807833df85e4a806e5a9498473f
Reported-by: Norwich in #coreboot on <irc.freenode.org>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5192
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Werner Zeh
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-02-24 21:58:08 +01:00
Duncan Laurie e3f75f8eca baytrail: Enable GFX device
- Ungate display in PUNIT
- Set GSM to 64MB since 32MB is not supported in <C0 stepping
- Initialize power management registers in GTT
- Execute VBIOS if found

BUG=chrome-os-partner:23507
BRANCH=rambi
TEST=build and boot to dev screen via HDMI on rambi

Change-Id: Idb032c7ea7f16b651b4c921e3429a652fe663a5d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174922
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4907
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-24 18:45:57 +01:00
Duncan Laurie e549e94d03 baytrail: IOSF write functions need to set data before control
The data needs to be available in the register before the control
bits are set to make the write happen.

BUG=chrome-os-partner:23507
BRANCH=rambi
TEST=successfully ungate power on PUNIT on rambi

Change-Id: I8fae60d5385ce9a401c1dec9cbb39b70d157a6c2
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174898
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4906
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-24 18:44:08 +01:00
Aaron Durbin 063c873588 rambi: add chromeos EC support
As rambi has the ChromeOS EC on it the EC needs to
be configured properly. Do this along with updating the
ChromeOS support for passing on write protect state, recovery
mode and developer mode.

BUG=chrome-os-partner:23387
BRANCH=None
TEST=Built and booted to depthcharge. EC software sync appears to
     work correctly. Additionaly, 'mainboard_ec_init' appears in
     the console output.

Change-Id: I40c5c9410b4acaba662c2b18b261dd4514a7410a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174714
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4905
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-24 18:43:43 +01:00
Aaron Durbin 3e0eea1f93 baytrail: initialize chromeos EC if present in romstage
The EC needs to be initialized early in romstage. Therefore
perform the call after console has been initialized in order to
view any messages that the code may spit out.

BUG=chrome-os-partner:23387
BRANCH=None
TEST=Built and booted with recovery mode and EC in RW. Noted that
     system reboots the EC.

Change-Id: I35aa3ea4aa3dbd9bd806b6498e227f45ceebd7a1
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174713
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4904
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-24 18:43:08 +01:00
Aaron Durbin 8fa6283b8d baytrail: use version 2 of efi wrapper
Version 2 of the efi wrapper wants the speed of the TSC
timer initialized in the parameter structure.

BUG=chrome-os-partner:22866
BRANCH=None
TEST=Built and booted through depthcharge. No errors spit out by
     wrapper.
CQ-DEPEND=CL:*147256

Change-Id: I9cd265ea6bde93be85fc6fbc905d83af57fc2773
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174712
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4903
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-24 18:42:52 +01:00
Aaron Durbin eb2eedf6f7 baytrail: remove gfx read_resources() work around
Before the special PUNIT settings the GFX pci device
had the same device id as the transaction router. This
required a special case in the transaction router's
driver to do the proper thing for read_resources().
However, that requirement is no longer needed as the
PUNIT special message is now being done. Therefore,
remove the work around.

BUG=None
BRANCH=None
TEST=Built and looked at resource allocation logs to confirm
     work around is no longer needed.

Change-Id: I90b155cb5560ca3291f146c2f586456e5529f6b2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174652
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4902
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-24 18:42:05 +01:00
Aaron Durbin 315bb30cd7 baytrail: get rid of global microcode_ptr
A global microcode_ptr was added when doing the MP
development work. However, this is unnecessary as the
pattrs structure already contains the pointer. Use
that instead.

BUG=chrome-os-partner:22862
BRANCH=None
TEST=Built and booted. Microcode still being loaded correctly.

Change-Id: I0abba66fc7741699411d14bd3e1bb28cf1618028
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174552
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4901
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-24 18:41:35 +01:00
Aaron Durbin 049e9bd2dc baytrail: add microcode version 319
Update microcode version to 319.

BUG=None
BRANCH=None
TEST=Built and booted. Noted 319 being used.

Change-Id: I008f90a1c6b542d979e34da22e9f375224c0ffeb
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174551
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4900
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-24 18:41:16 +01:00
Vladimir Serbinenko 8b22feb1cf jetway/nf81-t56n-lf: Use proper category.
"Mini-ITX" was a pure inventional name for category called "mini".

Change-Id: I6450fd27c1a7679f252ce7f46f409b7dc459c50d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5286
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-02-24 14:57:29 +01:00
Kyösti Mälkki d47c08affd TI am335x: Apply Kconfig use conventions
Change-Id: Ic3c26fd7b1dd8a6731abc9a63b9ca17e084074b2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5291
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-02-24 14:57:22 +01:00
Edward O'Callaghan d777d86ab2 CAR_GLOBAL: enforce compiler to check if _start != _end
There are some fun rules C compilers can use to optimize their code.
One of them is the assumption that two symbols point to two different
addresses.
In this case this wasn't true, resulting in unintended code execution
(and later, a crash) with a clang build.

Change-Id: I1496b22e1d1869ed0610e321b6ec6a83252e9d8b
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/4719
Tested-by: build bot (Jenkins)
2014-02-24 13:54:02 +01:00
Vladimir Serbinenko fb6d25faa0 device: Do not show "framebuffer graphics resolution" with native init.
No native init uses this.
Real hardware ones use mode specified in EDID.
Qemu one uses CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_[XY]RES.

Change-Id: I0845fec10b9811e2be44b5be30b9dc4f1c9719a6
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5281
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-22 09:07:53 +01:00
Vladimir Serbinenko 1a37b265a4 lib/edid: Don't set vbe_valid in decode_edid.
Decoding EDID doesn't yet mean that gfx mode is used.

Change-Id: Icedd36f26877754f34dd59233cce72271d7f0b19
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5269
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-02-21 08:19:48 +01:00
Kyösti Mälkki ea6736a2d0 usbdebug: Unify console API
Struct dbgp_pipe would not be suitable for use with xHCI.
Just use an index, it is easy to setup in Kconfig if our
future debug setup has separate pipes for console
output and debugging/traceings.

Change-Id: Icbbd28f03113b208016f80217ab801d598d443a8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5227
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-20 23:29:12 +01:00
Vladimir Serbinenko 902626c23c nehalem: Make SPD address map into parameter.
It's mobo dependent.

Change-Id: I7a9ba0fb7374a61178e9282acd8f10098435f1fd
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5253
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-02-20 23:18:10 +01:00
Vladimir Serbinenko 2ab8ec7cfb nehalem/raminit: Fix typo of NUM_CHANNELS instead of NUM_SLOTS.
Change-Id: I0fbfa8cb39881782bec3af5e43ff3c63dd2e4919
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5276
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-20 20:54:50 +01:00
Vladimir Serbinenko 2bebc80166 ibexpeak/thermal: set temperature target in early init.
Properly determine temperature target and set it in early
init rather than hardcoding it in late init.

Change-Id: Ie763f205890674a9dd1d9c5974caaccdd67cea14
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5264
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-20 14:04:19 +01:00
Vladimir Serbinenko 10b3974811 intel/model_2065x: Fix APICID generation.
APIC IDs always step by 4 on 2065x independently of number of threads.

Change-Id: I5abd4005c8ce1740bb0862d952af66236b609aa8
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5262
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-20 14:03:56 +01:00
Kyösti Mälkki e7f7d990df SMM: Fixes for DEBUG_SMI
Get the required UART includes directly.
The ne2k part is old copy-paste leftover.

Change-Id: Ifd9253abb5a50b515887459faf06b63f907eeda9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5258
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-20 12:56:56 +01:00
Vladimir Serbinenko b7d8788880 ibexpeak/lpc: Fix PCIIDs.
Add PCIID from Easynote LM85. Remove unrelated IDs inherited from
BD82x6x.

Change-Id: I03b6e0b2e08a4a6014aa1ef1f8d9a3a567f03ad9
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5263
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-02-19 23:24:08 +01:00
Patrick Georgi d01ed75066 printk: support and use %hh prefix
clang complains otherwise.

Change-Id: I2ac98d7147ecd3d7064f17f8c9d214d44baedf97
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/4717
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-02-19 20:57:58 +01:00
Patrick Georgi 327a86603c x86: only build disassembly with gcc
The assembler options are specific to the gnu toolchain.

Change-Id: I8424767ef186ef2d4c18bfbcae1f54e0da2e4f47
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/4715
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-02-19 20:56:56 +01:00
Patrick Georgi 938ef9fb8d x86 bootblock: improve clang compatibility
Its linker doesn't like "." arithmetics, so use .org,
while its assembler doesn't like data32 prefixes.

Change-Id: I3f5bbb350493d6510b8013df15d44c44c5db63c7
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/4714
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-02-19 20:56:19 +01:00
Duncan Laurie 0d0b3c5467 lynxpoint: Finalize chipset before playload if not CONFIG_CHROMEOS
The Chrome OS environment sends an SMI to finalize the chipset/board
at the end of the "depthcharge" payload, but there is no facility to
send this command if not using the full ChromeOS firmware stack.

This commit adds a callback before booting the payload that will
issue this SMI which will lock down the chipset and route USB devices
to the XHCI controller.

Change-Id: I2db9c44d61ebf8fa28a8a2b260a63d4aa4d75842
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/5181
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-18 18:22:51 +01:00
Kyösti Mälkki 970ad70763 console: Add drivers/uart
Also move UART related Kconfig options from top-level file.

Change-Id: I4e407977cff6f6506f991600c98d6d264676d3f8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5230
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-17 20:45:27 +01:00
Shawn Nematbakhsh 7040d7dfad rambi: Set VBOOT_RAMSTAGE_INDEX to point to ramstage image
The ramstage image is the third image in the partition (after ECRW hash
and depthcharge image).

TEST=Manual. Boot rambi, verify that ramstage image is correctly found:
"RW ramstage image at 0xffb1dc70, 0x0000f391 bytes"
BUG=None.

Change-Id: I628db3daf0b109106c51693960487a0c83b4e9f4
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174540
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4899
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-02-17 18:55:59 +01:00
Aaron Durbin ae5d83ef84 baytrail: add support to run reference code blob
The reference code blob is needed to bootstrap
certain pieces of hardware in bay trail. Provide
the ability to run reference code by loading
the reference code as an rmodule.

Note that support for vboot verification and S3
resume is omitted from this commit.

BUG=chrome-os-partner:22866
BRANCH=None
TEST=Built and booted with refcode loading.

Change-Id: I30334db441a57f4d87b4de6fca0a9a48e1c05c05
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174426
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4898
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-17 18:55:29 +01:00
Aaron Durbin e18d68fbac baytrail: add south cluster fixed resources
The PCU (platform controller unit) contains the
resources and IP blocks that used to reside in the
south bridge. Bay Trail has since renamed it south
cluster. There are quite a few fixed MMIO and I/O
resources. If these aren't added the resource allocator
will freely assign these addresses which causes conflicts
and other subtle bugs.

BUG=chrome-os-partner:23544
BUG=chrome-os-partner:23545
BRANCH=None
TEST=Built and booted through depthcharge. Verified
     resource allocation not weird. And no more depthcharge
     crashes.

Change-Id: I697fbda4538c03fded293bcb63a5823b1ed150ec
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174421
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4893
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-17 18:50:17 +01:00
Vladimir Serbinenko 6c3413ab5f lenovo/x201: Fix wrong declaration in devicetree.cb
Change-Id: I90c6ff14ab819368ccc874008a7fb1410a543984
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5255
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-17 10:24:58 +01:00
Aaron Durbin ce7ecf9cc7 baytrail: enable monotonic timer
Enabling the monotonic timer allows for collecting
boot stage times as well as each device initialization
time.

BUG=chrome-os-partner:23166
BRANCH=None
TEST=Built and booted. Noted timings in console output.

Change-Id: I5fdc703ea21710fd26de352f367c6fc0c767ab6a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174422
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4894
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-17 10:23:20 +01:00
Idwer Vollering 73a1018ce3 src/drivers/spi: introduce AMIC support
Add support for the AMIC A25L032 flash chip.

Change-Id: Ie8d441a923c6fbd18c16440b4571321652d934d5
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/5252
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-02-17 10:21:48 +01:00
Kyösti Mälkki a4c7b7a46b vortex86ex: Drop baudrate programming for 10 UARTs
This is responsibility of end-user application. When coreboot does
it, it is only for the purpose of debug console.

Change-Id: Idbbf9528c60b9b819b7bea9dfe84078a3f055bc9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5251
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Andrew Wu <arw@dmp.com.tw>
2014-02-17 09:14:55 +01:00
Kyösti Mälkki 591031f4de sandy/ivy: Fix mrc.cache file in CBFS
The file was not recreated when configuration changed. One would
hit this bug when turning CHROMEOS on/off.

Also do not create mrc.cache with CHROMEOS at all.

Change-Id: I5b0ecde66589396b24967ce289bf65e20bb08825
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5211
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-17 06:13:31 +01:00
Vladimir Serbinenko d262a71957 ibexpeak/azalia: Remove C4-register extended init.
This sequence was derived from BD82X6X and on ibexpeak it inadvertently
disables interrupts. In older kernels it wasn't a problem but in new kernel
it makes codec probe fail.

Change-Id: I40184ae8c4cfe758869af1a1565b88f0a238150e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5074
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-02-17 00:58:45 +01:00
Vladimir Serbinenko 56ffa7268c ibexpeak/sata: Add PCI ID from Easynote LM.
Change-Id: I979a40ad3692cd474920f3ee5c6b10c41f75bfdb
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5256
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-02-17 00:58:21 +01:00
Aaron Durbin 7837be6cbb baytrail: SMM support
Initialize SMM on all CPUs by relocating the SMM region
and setting SMRR on all the cores. Additionally SMI
is enabled in the south cluster.

BUG=chrome-os-partner:22862
BRANCH=None
TEST=Built and booted rambi. Tested with DEBUG_SMI and noted
     power button turns off board while in firmware.

Change-Id: I92e3460572feeb67d4a3d4d26af5f0ecaf7d3dd5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173983
Reviewed-on: http://review.coreboot.org/4892
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-16 20:57:14 +01:00
Aaron Durbin 6a360048a1 haswell: backup the default SMM region on resume
Haswell CPUs need to use the default SMM region for
relocating to the desired SMM location. Back up that
memory on resume instead of reserving the default
region. This makes the haswell support more forgiving
to software which expects PC-compatible memory layouts.

Change-Id: I9ae74f1f14fe07ba9a0027260d6e65faa6ea2aed
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5217
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-16 20:42:41 +01:00
Aaron Durbin b4b9eb399e x86: provide infrastructure to backup default SMM region
Certain CPUs require the default SMM region to be backed up
on resume after a suspend. The reason is that in order to
relocate the SMM region the default SMM region has to be used.
As coreboot is unaware of how that memory is used it needs to
be backed up. Therefore provide a common method for doing this.

Change-Id: I65fe1317dc0b2203cb29118564fdba995770ffea
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5216
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-16 20:42:07 +01:00
Kyösti Mälkki af5ca44784 intel/jarrell: Fix missing include
To unconditionally get cmos_read().

Change-Id: I0af0e85c8a1f42113bd32b51c4e29e86b3c28112
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5228
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-02-16 20:39:43 +01:00
Aaron Durbin 302cbd6c2e baytrail: bring up APs
Bring up the APs using x86 MP infrastructure.

BUG=chrome-os-partner:22862
BRANCH=None
TEST=Built and booted rambi. Noted all cores are brought up.

Change-Id: I9231eff5494444e8eb17ecdc5a0af72a2e5208b5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173704
Reviewed-on: http://review.coreboot.org/4889
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-02-16 20:39:06 +01:00
Aaron Durbin 70400284b9 rambi: add BSP lapic device
There's some baked in assumptions internal to coreboot
that the BSP's cpu device exists in the device tree. Therefore
provide one in the device tree.

BUG=chrome-os-partner:22862
BRANCH=None
TEST=Compiled and booted with other changes.

Change-Id: I22ba10964760ee8efbc5bbd5d4ce65daf31b3839
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173702
Reviewed-on: http://review.coreboot.org/4887
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-02-16 20:38:40 +01:00
Shawn Nematbakhsh 9956b72d56 baytrail: Modify GPIO pull-up specification method
Minor style changes to the way GPIO pull-ups are specified in
board-specific GPIO maps. Intent is to allow calls to GPIO_FUNC macro
from such maps.

BUG=chrome-os-partner:22863
TEST=Manual. Build + boot on bayleybay.

Change-Id: I80134b65d22d3ad8a049837dccc0985e321645da
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173748
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: David James <davidjames@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4886
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-02-16 20:38:23 +01:00
Aaron Durbin 6c52ba7779 rambi: disable internal pullups on ram_id[2:0]
The ram_id[2:0] signals have stuffing options for pull up/down
with values of 10K. However, the default pulldown values for these
pads are 20K. Therefore, one can't read a high value because of
the high voltage threshold is 0.65 * Vref. Therefore the high
signals are marginal at best.

Fix this issue by disabling the internal pull for the pads connected
to ram_id[2:0].

BUG=chrome-os-partner:23350
BRANCH=None
TEST=Built and checked that ram_id[2:0] is properly read now.

Change-Id: Ib414d5798b472574337d1b71b87a4cf92f40c762
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173211
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
Reviewed-on: http://review.coreboot.org/4885
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-02-16 20:37:55 +01:00
Aaron Durbin f3f409bf55 baytrail: correct MMC pci location
The original documentation was incorrect. Fix the pci
device for the MMC port to reflect reality.

MMC is at 00:17.0 with a device id of 0x0f50.

BUG=None
BRANCH=None
TEST=Built.

Change-Id: Ic18665b7dda5f386e72d1a5255e4e57d5b631eb0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172772
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4884
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-02-16 20:37:22 +01:00
Aaron Durbin 9d9d7f0429 baytrail: fix tsc rate
Despite some references to a fixed bclk in some of the
docs the bclk is variable per sku. Therefore, perform
the calculation according to the BSEL_CR_OVERCLOCK_CONTROL
msr which provides the bclk for the cpu cores in Bay Trail.

BUG=chrome-os-partner:23166
BRANCH=None
TEST=Built and booted B3. correctly says: clocks_per_usec: 2133

Change-Id: I55da45d42e7672fdb3b821c8aed7340a6f73dd08
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172771
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4883
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-02-16 20:37:03 +01:00
Kyösti Mälkki 6f6a249a75 usbdebug: Remove EHCI_DEBUG_OFFSET
Read this variable from PCI configuration capabilities list instead.

Change-Id: I0cfe981833873397c32cd3aa2af307f35f01784b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5176
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-16 20:10:54 +01:00
Edward O'Callaghan 6e56de3d20 Jetway NF81-T56N-LF [2/2]: actually implement mainboard support.
Step 2: change the Persimmon code to adapt it to the new board's hardware.

The NF81-T56N-LF is a IPC form factor embedded board:
- AMD Fusion G-T56N (1.65 GHz dual core) APU
  - 2x SO-DIMM sockets for DDR3 800-1066 SDRAM (Fixed at 1.5V)
  - VGA and LVDS (via Analogix ANX3110)
- AMD A55E (Hudson-E1) southbridge
  - 6x USB 2.0/1.1 ports
  - 5x SATA3 6Gb/s, 1x mSATA socket
  - 6-Channel HD Audio (via VIA VT1705)
  - PCI and ISA (via ITE IT8888)??
  - NEC uPD78F0532 microcontroller on I2C ("SEMA")??
- 2x RJ45 GbE (via Realtek RTL8111E x2)
- Fintek F71869AD Super I/O
  - PS/2 KB/MS port
  - RS232 header (via Unisonic UTC 75232 RS232 driver/receiver)
  - GPIO header
  - CIR header
- 1x MXIC MX25L1606E (SO8, soldered) 16 Mbit SPI flash (BIOS)

Note: MX25L1606E is 16Mbit, 8bits in a byte, so 2MB. Jetway *lies*
claiming the SPI flash is 16MB. They also use red pen over the chip
so you wont see this deceit.

Change-Id: I03ccc58bc782e800aeef0d19679ce060277b0c04
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/4801
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-16 04:51:47 +01:00
Edward O'Callaghan 4726a87c9a Jetway NF81-T56N-LF [1/2]: create board by forking AMD Persimmon
Step 1: copy all files unmodified from Persimmon.  This makes it much
easier later to see how the two boards actually and deliberately differ
when porting bugfixes from one to the other.

Change-Id: I23e223049ed1c69e320e6b31efe4266bfeb97207
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/4800
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-16 04:51:31 +01:00
Vladimir Serbinenko 80865c9619 lenovo/x60: Change to common EDID framework.
Currently lenovo/x60 gfx init provides vbe_mode_info_valid in
incompatible way. Use EDID framework as do other inits.

Change-Id: I887abd5a09064f26f473a2bf9caa2eb33e269c07
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5238
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-16 02:01:47 +01:00
Vladimir Serbinenko 7b54ca228e lenovo/x60: Fix EDID byte-swapping.
Change-Id: I75305ff7c5a8ba6142ef460e813acc014d9992bb
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5249
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-02-16 00:58:33 +01:00
Alexandru Gagniuc ffa839d310 console/uart8250*: Remove inclusion of mc146818rtc.h
The RTC functionality provided by the include is specific to x86, but
is not used in these files.

Change-Id: I82d0dfdb6e8b67bc81291a7a5d63ced91e095772
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4586
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-02-15 22:56:18 +01:00
Aaron Durbin 0f333071ef coreboot: infrastructure for different ramstage loaders
There are 2 methods currently available in coreboot to load
ramstage from romstage: cbfs and vboot. The vboot path had
to be explicitly enabled and code needed to be added to
each chipset to support both. Additionally, many of the paths
were duplicated between the two. An additional complication
is the presence of having a relocatable ramstage which creates
another path with duplication.

To rectify this situation provide a common API through the
use of a callback to load the ramstage. The rest of the
existing logic to handle all the various cases is put in
a common place.

Change-Id: I5268ce70686cc0d121161a775c3a86ea38a4d8ae
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5087
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-02-15 18:39:29 +01:00
Aaron Durbin e9aaa71fb1 x86: provide stage_exit() like arm
The arm architectures have a stage_exit() function
which takes a void * pointer as an entry point. Provide
the same API for x86. This can make the booting paths
less architecture-specific.

Change-Id: I4ecfbf32f38f2e3817381b63e1f97e92654c5f97
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5086
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-02-15 18:03:15 +01:00
Alexandru Gagniuc 09af15e09e google/rambi: Do not select CHROMEOS in Kconfig
CHROMEOS is the meant to be selected by the user. The correct variable
for a mainboard to select is MAINBOARD_HAS_CHROMEOS. This will then
default to a CHROMEOS build, but when the mainboard selects CHROMEOS,
the user can no longer disable CHROMEOS.

Change-Id: I78fb15a0a9fef733e2de064d6c09cf774b7bce78
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5218
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2014-02-14 15:17:11 +01:00
Edward O'Callaghan b5fc67ab02 superio/fintek: Document Fintek F71869AD code.
Change-Id: I156077bf5571764d0e4bc044be80c8ab94556de4
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5178
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-02-13 17:14:20 +01:00
Alexandru Gagniuc 6d51f5dfe9 cpu/allwinner/a10: Add minimal ramstage driver
Change-Id: I857755976b17b0e492c086162f395a77933eeed8
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4698
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-13 17:03:58 +01:00
Aaron Durbin 3ccb3ce415 baytrail: print dram configuration
After running the MRC blob print out some information
on the training: MRC version, number channels, DDR3
type, and DRAM frequency.

Example output:
MRC v0.90
2 channels of DDR3 @ 1066MHz

Apparently there are two dunit IOSF ports -- 1 for each
channel. However, certain registers really on live in
channel 0. Thus, there was some changes to dunit support
in the iosf area.

BUG=chrome-os-partner:22875
BRANCH=None
TEST=Built and booted bayleybay in different configs.

Change-Id: Ib306432b55f9222b4eb3d14b2467bc0e7617e24f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172770
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4882
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-13 16:55:56 +01:00
Aaron Durbin 1ce0b3022c baytrail: allow downstream use of SSE instructions
If a payload is compiled to use SSE instructions it will
fault with an undefined opcode because SSE instructions weren't
enabled. Therefore enable SSE instructions at runtime.

BUG=chrome-os-partner:22991
BRANCH=None
TEST=Built and booted with SSE enabled payload. No exceptions seen.

Change-Id: I919c1ad319c6ce8befec5b4b1fd8c6343d51ccc1
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172642
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4881
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-13 16:55:45 +01:00
Aaron Durbin dc249f690a baytrail: add vboot ramstage verification
Add suport for verifying the ramstage with vboot
during romstage execution. Along with this support
select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM to
cache the relocated ramstage 1MiB below the
top end of the TSEG region.

BUG=chrome-os-partner:23249
BRANCH=None
TEST=Built and booted with CONFIG_VBOOT_VERIFY_FIRMWARE=y
     selected.

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I355f62469bdcca62b0a4468100effab0342dc8fc
Reviewed-on: https://chromium-review.googlesource.com/172712
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4880
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-13 16:55:33 +01:00
Oskar Enoksson 42283e7994 Eliminate some ASL warnings
The ASL compiler warned about "Control Method should be made Serialized
(due to creation of named objects within)". This commit eliminates the
warnings by changing those NonSerialized into Serialized.

Change-Id: I639e769cf7a9428c34268e0c555a30c7dee1e04c
Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
Reviewed-on: http://review.coreboot.org/5189
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-02-13 01:04:02 +01:00
Alexandru Gagniuc 76e25b66ae google boards: Do not hardcode location of spd.bin
spd.bin can reside anywhere in CBFS, and we only use CBFS APIs to
access and read it. As such, there is no need to hardcode it, and it
can collide with mrc.bin or mrc.cache on some boards. Do not use a
specific position for spd.bin, but instead let cbfstool find the
optimal placement.

Change-Id: I496094d3c0de708813494095b7ac4be8addb4112
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5210
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-12 23:37:24 +01:00
Shawn Nematbakhsh 82e7d956ef baytrail: gpio: add configs for PU/PD functional pins
Pull-ups and pull-downs can be active on functional pins. Add configs
for these options so they can be specified on board GPIO maps.

TEST=Manual on bayleybay. Verify that platform boots to payload load.
BUG=chrome-os-partner:22863

Change-Id: Ie4f77d8ce812f086cc8fe5a6bfcac59669f56f92
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172766
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5209
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-12 23:36:10 +01:00
Duncan Laurie b3b008a9b6 falco: Add ACPI code to describe the I2C touchpad device
If the SerialIO devices are put into ACPI mode then it is possible
to use ACPI to instantiate the touchpad in the kernel without
needing to have a platform level driver to do the binding.

This is the "new way" of describing on-board I2C devices and the
upstream kernel is starting to add ACPI IDs to drivers so they can
be used in this fashion.  For the Cypress touchpad use a generic
ACPI ID of "CYPA0000" to describe it.

In order to support the proper scoping of the touchpad device under
the appropriate I2C controller device the mainboard.asl file needs
to be included after pch.asl so the I2C device exists.

Change-Id: I81e053d27be478f3a19b6f9b13cd2b4fabcb88c0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/5194
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-02-12 23:31:45 +01:00
Duncan Laurie 6c03160d48 lynxpoint: Do not put SerialIO devices into D3Hot in ACPI mode
Remove the bit of code that was putting the SerialIO devices into
D3Hot state when they are switched from PCI to ACPI mode.  Instead,
add the appropriate ACPI Methods to allow the kernel to control the
power state of the device.

The problem seems to be that if the device is put in D3Hot state
before it is switched from PCI to ACPI mode then it does not properly
export its PCI configuration space and cannot be woken back up.

Adding the ACPI Methods for _PS0/_PS3 allows the kernel to transition
the device into D0 state only when it is necessary to communicate with
the device, then put it back into D3Hot state.

Change-Id: I2384ba10bf47750d1c1a35216169ddeee26881df
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/5193
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-02-12 23:31:19 +01:00
Kyösti Mälkki 2161c1d792 PCI: Add capability list parser to romstage
These are almost one-to-one copies from pci_device.c. However,
devicetree has not been enumerated yet and we have no console.

Change-Id: Ic80c781626521d03adde05bdb1916acce31290ea
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5196
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-12 22:01:00 +01:00
Kyösti Mälkki 2c78726897 PCI: Drop includes under cpu
The files affected do not make any PCI configuration calls.
If they did, the more correct includes would be pci_ops.h,
pci_defs.h and pci_ids.h.

Change-Id: I3e7f009371be6ea50318eaabf0c15500cb3f1210
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5200
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-02-12 21:57:11 +01:00
Kyösti Mälkki 318066fbc1 PCI: Guard pci.h with CONFIG_PCI
Adding PCI functions for romstage in pci.h breaks ARMv7 build without
this. Also fix two related includes to use pci_def.h instead.

Change-Id: I5291eaf6ddf5a584f50af29cf791d2ca4d9caa71
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5199
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-12 21:56:30 +01:00
Kyösti Mälkki 8cde852ecf usbdebug: Split to USB host/device
Top-level interface to console over USB mut not require low-level
details of ECHI debug port internals.

Change-Id: If3ca3b1f479e3f20976cd4abd8f5e682a58d5650
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5197
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-12 21:55:56 +01:00
Oskar Enoksson 411bf97c22 winbond/w83627hf/acpi: Fix some ASL warnings
There were ASL compiler warnings about "Size mismatch". This commit
eliminates the warnings by changing the ASL declarations of those
fields.

Change-Id: If851ed4892ef6c96acbff861abd7001ab67d9d66
Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
Reviewed-on: http://review.coreboot.org/5190
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-02-12 21:30:33 +01:00
Oskar Enoksson adc0a6352d hp/dl145_g1: Add missing copyright notes
Missing copyright notes added.

Change-Id: I55b320a169b1125017c63b7a2384078465e7ce6e
Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
Reviewed-on: http://review.coreboot.org/5188
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-02-12 00:35:11 +01:00
Oskar Enoksson 3298eb2123 hp/dl145_g1: Fix some commented out code
Some out-commented code contained variables which changed name.
This commit fixes the "problem".

Change-Id: I8d9168c9f4b2cb6810b3e4dfeff2155f3c08357d
Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
Reviewed-on: http://review.coreboot.org/5187
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-02-12 00:33:57 +01:00
Oskar Enoksson 592d5277cc hp/dl145_g1: Add HAVE_HARD_RESET
This platform has a hard reset button

Change-Id: Ic4d2f9382b6770654eea8842a37ad38cf12de459
Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
Reviewed-on: http://review.coreboot.org/5097
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-02-11 23:57:05 +01:00
Oskar Enoksson aaedecaea4 hp/dl145_g1: Adding FID/VID and Powernow ACPI
Add cool-n-quiet functionality which allows the OS to dynamic
alter CPU voltage and frequency change in order to save power
e.g. when the CPU load is low.

Change-Id: I4c895a56bcf571d4276af192aeef87d120143063
Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
Reviewed-on: http://review.coreboot.org/5186
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
2014-02-11 23:56:28 +01:00
Aaron Durbin d907a3402e amd/cimx: fix sb(8|9)00 NULL type redefine
It is inappropriate for chipset code to be redefining
types -- especially NULL to a non-pointer type. There's
only one non-straight forward change. A condition
being checked was '!ptr_type == NULL' (0 as int). That
check is actually 'ptr_type != NULL'.

Change-Id: Iab5733e5a573baba6fec94e0c955ba4fad72c836
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5088
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-02-11 22:23:15 +01:00
Aaron Durbin 6ecdb68562 baytrail: add reset support
Bay Trail has the following types of resets it supports:
 - Soft reset (INIT# to cpu) - write 0x1 to I/O 0x92
 - Soft reset (INIT# to cpu)- write 0x4 to I/0 0xcf9
 - Cold reset (S0->S5->S0) - write 0xe to I/0 0xcf9
 - Warm reset (PMC_PLTRST# assertion) - write 0x6 to I/O 0xcf9
 - Global reset (S0->S5->S0 with TXE reset) - write 0x6 or 0xe to
   0xcf9 but with ETR[20] set.

While these are documented this support currently provides support
for 2nd soft reset as well as cold and warm reset.

BUG=chrome-os-partner:23249
BRANCH=None
TEST=Built and booted.

Change-Id: I9746e7c8aed0ffc29e7afa137798e38c5da9c888
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172710
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4878
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-02-11 22:22:25 +01:00
Shawn Nematbakhsh f92271db84 rambi: Add platform GPIO configuration tables
Configure GPIOs according to function on board.

TEST=compile only.
BUG=chrome-os-partner:22863

Change-Id: Ic38eeb64149606f2d7a19cc7a0144cc7e24807b8
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172657
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4875
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-02-11 22:21:38 +01:00
Shawn Nematbakhsh 8561460d68 rambi: Add ncore GPIO config tables
gpncore config tables were previously missing -- add them.

Also, make the baytrail GPIO/PAD LUTs easier to read.

TEST=Manual. Build + boot on bayleybay.
BUG=chrome-os-partner:22865

Change-Id: I49a1b23c7ad4fb5f4c86618e8c78ea9a1a42f79d
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172510
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4874
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-02-11 22:21:20 +01:00
Aaron Durbin 1f5eb1f78e rambi: add per-sku SPD support
There are currently 4 SKUs:
0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
0b001 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz
0b011 - 2GiB total - 2 x 1GiB Hynix  H5TC2G63FFR-PBA 1600MHz

Add each of the 4 spds to the build, and use the proper
parameters to MRC to use the in-memory SPD information.

BUG=chrome-os-partner:22865
BRANCH=None
TEST=Built. Noted 1024 bytes of SPD content.

Change-Id: Ife96650f9b0032b6bd0d1bdd63b8970e29868365
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172280
Reviewed-on: http://review.coreboot.org/4872
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-02-11 22:20:28 +01:00
Aaron Durbin 5f8ad56358 baytrail: move early init to before mainboard
It's helpful to have a lot of the early init happen
before the handoff to mainboard. One example of this
need is having the BARs programmed so that the mainboard
can read board-specific gpios.

BUG=chrome-os-partner:22865
BRANCH=None
TEST=Built. Booted and saw console outout in bayleybay
     mainboard.

Signed-off-by; Aaron Durbin <adurbin@chromium.org>

Change-Id: I030d7b4f9061ad7501049e8e204ea12255061fbe
Reviewed-on: https://chromium-review.googlesource.com/172290
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4871
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-11 22:19:48 +01:00
Shawn Nematbakhsh 3b036f7107 baytrail: Add functions to peek at GPIO input values
- Add functions to peek at GPIO input pad values (need to be used from
  romstage for board ram_id GPIOs)
- Modify UART GPIOs to use existing fn-assignment function

TEST=Manual. Add debug print and verify that GPIO functions return input
values. Also, verify UART still functions in romstage.
BUG=chrome-os-partner:22865

Change-Id: Ib2e57631c127a592cfa20ab6e2184822424e9d77
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172189
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4870
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-11 22:19:32 +01:00
Aaron Durbin bb3ee83711 baytrail: set max frequency early in romstage
Set the BSP to operate at max frequency early in romstage.
The call to punit_init() is when the frequency actually ramps as
that makes the punit actually start working.

BUG=chrome-os-partner:22857
BRANCH=None
TEST=Built and booted. Noted operating frequency status is max.

Change-Id: Icfd9e5c7682aa21fc740bd687607ca6a66597d5e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172131
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4869
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-11 22:19:14 +01:00
Aaron Durbin 08a4613219 baytrail: adjust cache policy during romstage
The caching policy for romstage was previously using a 32KiB
of cache-as-ram for both the MRC wrapper and the romstage stack/data.
It also used a 32KiB code cache region. The BWG's limitations for
the code and data region before memory is up was wrong. It consists
of a 16-way set associative 1MiB cache. As long as enough addresses
are not read there isn't a risk of evicting the data/stack.

Now create a 64KiB cache-as-ram region split evenly between romstage
and the MRC wrapper. Additionally cache the memory just below
4GiB in CBFS size. This will cover any code and read-only data needed.

BUG=chrome-os-partner:22858
BRANCH=None
TEST=Built and booted quickly with corresponding changes to MRC warpper.
CQ-DEPEND=CL:*146175

Change-Id: I021cecb886a9c0622005edc389136d22905d4520
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172150
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4868
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-11 22:18:59 +01:00
Aaron Durbin 3f5a1ffb83 baytrail: add punit access functions
Like the bunit and dunit, add the punit accessor functions.

BUG=chrome-os-partner:23085
BRANCH=None
TEST=Built.

Change-Id: Ifd7184dfca8c0491c107bc1c562ea1ded444e372
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/171931
Reviewed-on: http://review.coreboot.org/4867
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-02-11 22:18:48 +01:00
Shawn Nematbakhsh 0b132c3ae3 baytrail: make default GPIO configs closer to power-on defaults
- Set config0 defaults for hysteresis disable, pad bypass, etc.
- Set config1 power-on defaults.
- Set pad_val for input as default.

BUG=chrome-os-partner:22863
TEST=Manual. Enable GPIO_DEBUG and verify pad registers are set
according to expectation. Also verify bayleybay still boots to payload
loading.

Change-Id: I0f1c9e4d4f39c5c56d7e14a82eb4825612e19420
Reviewed-on: https://chromium-review.googlesource.com/171903
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4866
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-11 22:18:33 +01:00
Kyösti Mälkki 5a5c886b8d SMP: Add arch-agnostic boot_cpu()
We should not have x86 specific includes in lib/.

Change-Id: I18fa9c8017d65c166ffd465038d71f35b30d6f3d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5156
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-11 21:55:30 +01:00
Kyösti Mälkki 972d5cf040 Move hexdump32() to lib/hexdump.
Needs printk and is not a console core function.

Change-Id: Id90a363eca133af4469663c1e8b504baa70471e0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5155
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-11 21:54:34 +01:00
Peter Stuge 4d77ed9d99 Kconfig: Move vendorcode menu up from the bottom to above Chipset menu
Change-Id: Ic97a497a634533f44d94df297ca6e35d94c34565
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/5160
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-11 21:37:29 +01:00
Oskar Enoksson 2516f2e467 hp/dl145_g1: Adding ACPI support
Basic ACPI support for this old platform. Created by copying and
tweaking similar motherboard ACPI implementations in coreboot.
Works reasonably well under Linux, providing HPET-timers
and more under linux (tested under OpenSUSE 12.2 kernel 3.4.63-2.44).
Not tested under Windows.

Change-Id: I69431be962a0d272db398ecf4ac9f0249de8ebab
Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
Reviewed-on: http://review.coreboot.org/5185
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-02-11 01:21:36 +01:00
Kyösti Mälkki cb141bce35 usbdebug: Split PCI EHCI part
There are EHCI compatible host controllers on ARM without PCI bus
architecture. Currently we have not come across one with the debug
capability though.

Change-Id: I8775c9814f6fdf8754f97265118a7186369d721d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5175
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-10 19:34:20 +01:00
Kyösti Mälkki 48e899d2d5 usbdebug: Fix data toggle on receive
USB device end toggles data PID when we ACK'd the zero-length data
packet. As USB host we need to toggle data PID too or the next data
received would get discarded.

Change-Id: I3203bc874c7ded9244c7548a666d7041a0fbb379
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4775
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-10 19:33:45 +01:00
Kyösti Mälkki 089b88c165 usbdebug: Remove duplicate port claim
This claim is useless when done before EHCI controller reset. Code in
usbdebug_init_() already sets this properly after reset, see use of
DBGP_OWNER.

Change-Id: Ic17493fe4edbbbed6ebcbef35a264fbf188f1fba
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4709
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-10 19:33:25 +01:00
Kyösti Mälkki 0108bf5157 usbdebug: Improve receive speed
Read from USB endpoint_in 8 bytes at a time, the maximum what
EHCI debug port capability has to offer.

Change-Id: I3d012d758a24b24f894e587b301f620933331407
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4700
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-10 19:33:04 +01:00
Vladimir Serbinenko b33384a03c device_util: Make device in dev_find_slot_pnp u16.
LDN is 8-bit but coreboot squeezes unrelated info: VLDN in this field.
Increase to 16-bit to handle this.

Change-Id: I97af1b32dcfaed84980fa3aa4c317dfab6fad6d8
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5165
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-02-09 23:33:08 +01:00
Aaron Durbin ca4f4b8c9e mtrr: only add prefetchable resources as WRCOMB for VGA devices
Be more conservative and only add VGA devices' prefetchable
resources as write-combining in the address space. Previously
all prefetchable memory was added as a write-combining memory
type. Some hardware incorrectly advertises its BAR as
prefetchable when it shouldn't be.

A new memranges_add_resources_filter() function is added
to provide additional filtering on device and resource.

Change-Id: I3fc55b90d8c5b694c5aa9e2f34db1b4ef845ce10
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5169
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Tested-by: build bot (Jenkins)
2014-02-09 22:08:53 +01:00
Vladimir Serbinenko 400c05cf25 device_util: Add dev_find_slot_pnp.
Change-Id: I5223c54c8ddbc60a176e4d718730e99decc772a3
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5112
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-02-07 09:06:05 +01:00
Kyösti Mälkki 732cee31a6 ARMv7: Remove static CBMEM allocation
The calculations for static allocation are no longer valid.

Change-Id: I6740cdcec789abddf78485a0edaf24882ef8c2a5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4569
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-02-06 11:22:14 +01:00
Kyösti Mälkki c79dfdb991 console: Drop IO and Oxford (PCI) UARTs on armv7
Change-Id: Ia410b61c4babdfa3c984539527a9739462d3ad80
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5141
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-02-06 11:18:40 +01:00
Kyösti Mälkki 9a3acf6900 console: Drop extra uart_init()
This call is already in console_init().

Change-Id: Ie0cb3595af514e37efac5ac5d474f52ba551bf22
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5140
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-06 11:17:41 +01:00
Kyösti Mälkki e2f4c2a72f uart8250: Drop includes in superio
Change-Id: If723896cc31da75dbb3a63d5dc959764e96fded1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5139
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-06 11:17:24 +01:00
Kyösti Mälkki d0281f15eb uart8250: Drop unused declarations
Change-Id: Ie915ef9dbc45604bd5ca1b610acb12af634fdebe
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5138
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-06 11:17:05 +01:00
Kyösti Mälkki 2113099e49 uart8250: Drop xmodem support
Unused and hard-coded to use uart8250 on IO.

Change-Id: I3f84c50039a450a2ae97a5fd2af89992f8567e6c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5137
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-06 11:16:37 +01:00
Kyösti Mälkki 03731d776c QEMU debugcon: Move under drivers/emulation/qemu
Also prepare this console for use in romstage.

Change-Id: I26a4d4b5db1e44a261396a21bb0f0574d72aa86d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5136
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
2014-02-06 11:16:26 +01:00
Kyösti Mälkki 207379db12 ne2k: Move under drivers/net
Change-Id: I978b6009c09c31be4429f57be40ef82f438f7574
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5135
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-06 11:14:50 +01:00
Kyösti Mälkki 5148642c56 spkmodem: Move under drivers/pc80
Change-Id: I46eb17ab19cea8759b3e4822019285cbe907e83a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5134
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-02-06 11:14:24 +01:00
Kyösti Mälkki e2227a23a7 usbdebug: Move under drivers/usb
Also relocate and split header files, there is some interest
for EHCI debug support without PCI.

Change-Id: Ibe91730eb72dfe0634fb38bdd184043495e2fb08
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5129
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-06 11:13:57 +01:00
Kyösti Mälkki 9db1c4e51a usbdebug: Drop obsolete code
Change-Id: I918ca1d0d0d7bcb7e16d41a12830a0357f15b8ed
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5130
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-02-06 11:13:31 +01:00
Vladimir Serbinenko 30fe6120ca MTRR: Mark all prefetchable resources as WRCOMB.
Change-Id: I2ecfd9733b65b6160bc2232d22db7b16692a847f
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5149
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-06 00:55:13 +01:00
Vladimir Serbinenko 7a4fa0a32c lib/memrange: Skip 0-sized resources.
Change-Id: I44194153817b8e6b641e407fc4a9e0fd5bc3f318
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5152
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-06 00:55:06 +01:00
Aaron Durbin 5b9e3b6051 mtrr: retry fitting w/o WRCOMB if usage exceeds BIOS allocation
If the MTRR usage exceeds the BIOS allocation for MTRR usage
re-try without the WRCOMB type.

Change-Id: Ie70ce84994428ff6700c36310264c3c44d9ed128
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5151
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Tested-by: build bot (Jenkins)
2014-02-06 00:09:09 +01:00
Aaron Durbin ed9307db13 memranges: add memranges_update_tag() functionality
The memranges_update_tag() function replaces all instances
that are tagged with old_tag and update to new_tag. This
can be helpful in the MTRR code by adjusting the address
space if certain memory types cause the MTRR usage to
become too large.

Change-Id: Ie5c405204de2fdd9fd1dd5d6190b223925d6d318
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5150
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-02-06 00:08:59 +01:00
Vladimir Serbinenko 3d6ffe76f8 load_payload: Use 32-bit accesses to speed up decompression.
Flash prefers 32-bit sequential access. On some platforms ROM is
not cached due to i.a. MTRR shortage. Moreover ROM caching is not
currently enabled by default. With this patch payload decompression
is sped up by theoretical factor of 4.

Test on X201, with caching disabled:

Before:
  90:load payload                  4,470,841 (24,505)
  99:selfboot jump                 6,073,812 (1,602,971)

After:
  90:load payload                  4,530,979 (17,728)
  99:selfboot jump                 5,103,408 (572,429)

Change-Id: Id17e61316dbbf73f4a837bf173f88bf26c01c62b
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5144
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2014-02-05 23:04:53 +01:00
Vladimir Serbinenko 79c712cb9e lenovo/x201: Enable flash prefetching.
Speeds up coreboot and especially payload load.

Before:
  90:load payload                  4,530,979 (17,728)
  99:selfboot jump                 5,103,408 (572,429)

After:
  90:load payload                  4,390,051 (14,849)
  99:selfboot jump                 4,505,966 (115,915)

Change-Id: I45c3042594cda16ab3adde6472e00ec1b2d2a688
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5145
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-05 20:11:35 +01:00
Aaron Durbin c625d0983c mainboard/google: add initial rambi mainboard support
BUG=chrome-os-partner:23121
BRANCH=None
TEST=None

Change-Id: I283415be326e2d92e1e1bf7866954f17a7266edb
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/171940
Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
Reviewed-on: http://review.coreboot.org/4865
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-05 05:24:26 +01:00
Aaron Durbin 189aa3e2ae baytrail: initialize punit
The punit is responsible for a number of things. Without
performing the sequence included it won't change processor
frequency when requested and apparently there are some bizarre
hangs introduced if this sequence isn't included either. Lastly,
this needs to come after microcode has been loaded. As that is
done in bootblock the ordering is correct.

One other side effect is that this fixes the graphics devices'
device id. Before it was showing up as the same device id of the
SoC transaction router.

BUG=chrome-os-partner:22880
BUG=chrome-os-partner:23085
BUG=chrome-os-partner:22876
BRANCH=None
TEST=Built and booted.

Change-Id: Ib7be1d4b365e9a45647c778ee5f91de497c55bf1
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/171862
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4864
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-02-05 05:24:20 +01:00
Aaron Durbin c0270aa6d0 baytrail: load microcode in bootblock
Start loading microcode in the bootblock. This way
no caching has been set up and cache-as-ram mode
will be running in a validated configruation (with ucode
patch).

BUG=chrome-os-partner:22858
BRANCH=None
TEST=Built and booted. Confirmed microcode is loaded.

Change-Id: I6fd1d8e55bcc9d799b11d9faed771ac50dc120a2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/171861
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4863
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-02-05 05:24:13 +01:00
Aaron Durbin fd039f7f4d baytrail: disable tco timer
The TCO timer always starts ticking out of reset.
However, depending on microcode loading and punit
initialization the TCO timing out has a different
impact on the sytem. Without loading microcode
or initializing the punit the tco times out and
nothing happens. However, when microcode is loaded
a timeout will reset the system. Lastly, if the
punit is initialized but the microcode isn't loaded
the TCO timeout will shut down the system.

To fix all the weird symptoms disable the TCO.

BUG=chrome-os-partner:22858
BRANCH=None
TEST=Built and booted with microcode loading. Reset doesn't
     occur.

Change-Id: I49cd62f510726a96bf734ae728a352c671d1561e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/171860
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4862
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-02-05 05:24:03 +01:00
Aaron Durbin a64ef62ca4 baytrail: program PUNIT memory-mapped base address
Apparently there was another BAR living at 0x5c in the LPC
bridge that mapped the PUNIT registers. EDS 2.0 released
and this register is now documented.

BUG=chrome-os-partner:23085
BRANCH=None
TEST=Built and booted.

Change-Id: I5892c2a14923b57826060e92b4335cb1952ea057
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/171612
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4861
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-02-05 05:23:54 +01:00
Aaron Durbin 51ca694a97 baytrail: add 316 microcode
The 316 microcode is the newest version. Include that in the build.

BUG=chrome-os-partner:22858
BRANCH=None
TEST=Built and partially booted with microcode loading. Noted 316
     loaded.

Change-Id: Iba01dd58688737ae38bc58a84014ee9526540db1
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/171611
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4860
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-02-05 05:23:46 +01:00
Aaron Durbin 3f00d29800 baytrail: additional iosf changes
Allow for one to write an individual byte of a 32-bit register
when sending a read/write through the IOSF messaging system.
Add PUNIT registers and fields for early sequencing.

BUG=chrome-os-partner:23085
BRANCH=None
TEST=Built and partially booted with changes that use PUNIT
     registers and individual byte en fields.

Change-Id: I929fb5c51d805c55c478cab884e3572254987fc7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/171710
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4859
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-02-05 05:23:35 +01:00
Aaron Durbin 833ff353b7 baytrail: import and use updated mrc_wrapper.h
The mrc_wrapper.h was changed to protect against ABI differences
between the two sets of compilers and flags used. This requires
a prope shim for the console output funciton.

BUG=chrome-os-partner:23048
BRANCH=None
TEST=Built and booted successfully.

Change-Id: I976e692e66dcfc0eacadae6173abfd9b81e31137
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/171580
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4858
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-02-05 05:23:27 +01:00
Vadim Bendebury c04e171467 baytrail: Rearrange config options alphanumerically
This is a no-op change for easier maintenance.

BUG=none
TEST=manual
    . baitrail coreboot still builds and runs

Change-Id: I0c0bd78c6f361e8f81979f19cce148e7f51865ee
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/171002
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4857
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-02-05 05:23:18 +01:00
Aaron Durbin 794bddf97c baytrail: start collecting timestamps
This commit always selects COLLECT_TIMESTAMPS and starts
tracking TSC values from the early stages of bootblock.
The initial timestamp value is saved in mm0 and mm1 while
in bootlbock. This approach works because romcc is not configured
to use mmx registers for its compilation.

Additionally, the romstage api with the mainboard was changed to
always pass around a pointer to a romstage_params structure as the
timestamps are saved in there until ram is up.

BUG=chrome-os-partner:22873
BRANCH=None
TEST=Built and booted with added code to print out timestamps at
     end of ramstage. Everything looks legit.

Change-Id: Iba8d5fff1654afa6471088c46a357474ba533236
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170950
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4856
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-02-05 05:23:08 +01:00
Vladimir Serbinenko f592c08b68 pcengines/alix2c: Add ALIX.2C as a clone of ALIX.2D.
According to vendor (Pascal Dornier) they're the same from coreboot
perspective.

Change-Id: I43aeb77f21c251b3d9c5c2dcfa01d4d1de0bc87b
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5114
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-04 17:55:06 +01:00
Kyösti Mälkki fbdbcb713f AMD cimx/sb800: Set SPI frequency and prefetch
Broken with/since commit d1cb0eec.

Original intention was to set the frequency for 'Fast Read' command
in bits 15..14, and enable 'Fast Read' command.

Modified register contains SPI frequency for 'Normal Read' command
in bits 13..12. Default for this is 11b for 16.5 MHz. Existing code
unintentionally clears these bits, increasing SPI frequency to 66MHz
for 'Normal Read' command.

This is above specifications for many common SPI flash components
and also makes flashrom older than 0.9.7-r1750 to operate unreliably
on read/write/erase for these platforms.

Change-Id: I30109e2a0410c0bb0bdc968ea71787396b32e761
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5089
Tested-by: build bot (Jenkins)
Reviewed-by: Kevin O'Connor <kevin@koconnor.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-02-04 01:43:31 +01:00
Oskar Enoksson d9b5d897d7 cpu/amd/model_fxx: Add coolnquiet for two new (old) AMD K8 models
The added CPU's are OSA248CEP5AU and a OSP280 processors.
The OSP280 VID/FID numbers have been found by experimentation
and extrapolation/guesses from similar models. It has been
verified to work fine under Linux (OpenSuse 12.2, kernel
3.4.63-2.44) with four different test-processors.
Windows is untested.

Change-Id: I3afa1cba5f55c8a78917b3636382af7706a80fee
Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
Reviewed-on: http://review.coreboot.org/5095
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-02-03 22:24:17 +01:00
Shawn Nematbakhsh ebe3b3cfe2 baytrail: Add GPIO initial configuration infrastructure.
During ramstage, call mainboard_get_gpios to get initial GPIO configuration
from the mainboard code, then initialize GPIOs as requested.

BUG=chrome-os-partner:22863
TEST=Manual. Using bayleybay GPIO table, set UART GPIOs to 'function 1',
and verify UART still works after GPIO configuration. Also, verify
legacy GPIO config is functional by toggling test pin.

Change-Id: Ic58d8ddd15c4dc48a751a83f6d26c7809c1efc42
Reviewed-on: https://chromium-review.googlesource.com/170306
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4855
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-03 16:31:05 +01:00
Vladimir Serbinenko c8f54a1109 lenovo/x230: Enable msata port.
Port 2 is used by msata. Enable it.

Change-Id: Ib75227f64c9d77f6cfca1902a78d63b5cdd23d76
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4789
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-02-03 03:45:14 +01:00
Ronald G. Minnich a8a133ded3 Add section header parsing and use it in the mk-payload step
This completes the improvements to the ELF file parsing code.  We can
now parse section headers too, across all 4 combinations of word size
and endianness. I had hoped to completely remove the use of htonl
until I found it in cbfs_image.c. That's a battle for another day.

There's now a handy macro to create magic numbers in host byte order.
I'm using it for all the PAYLOAD_SEGMENT_* constants and maybe
we can use it for the others too, but this is sensitive code and
I'd rather change one thing at a time.

To maximize the ease of use for users, elf parsing is accomplished with
just one function:

int
elf_headers(const struct buffer *pinput,
	    Elf64_Ehdr *ehdr,
	    Elf64_Phdr **pphdr,
	    Elf64_Shdr **pshdr)

which requires the ehdr and pphdr pointers to be non-NULL, but allows
the pshdr to be NULL. If pshdr is NULL, the code will not try to read
in section headers.

To satisfy our powerful scripts, I had to remove the ^M from an unrelated
microcode file.

BUG=None
TEST=Build a peppy image (known to boot) with old and new versions and verify they are bit-for-bit the same. This was also fully tested across all chromebooks for building and booting and running chromeos.
BRANCH=None

Change-Id: I54dad887d922428b6175fdb6a9cdfadd8a6bb889
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/181272
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: http://review.coreboot.org/5098
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-02 20:18:55 +01:00
Paul Menzel 25fc8d181f drivers/i2c/at24rf08c/lenovo_serials.c: Remove trailing whitespace
The trailing whitespace breaks the Git commit hook
`util/lint/lint-stable-003-wihitespace`. So remove it.

Change-Id: I70e4ac71529884a9a4fabf2aa9a4ea6e0323b9d4
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5092
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-02-02 12:26:08 +01:00
Rudolf Marek 566b4f008f AGESA f15tn: Fix GPP ports resume
The AGESA resumes the GPP ports in the romstage using FchInitResetGpp(),
which does FchGppPortInitS3Phase() for S3 resume. The PreInitGppLink()
looks into CMOS to figure out what ports to just force to Gen1 or
Gen2 PCIe. Then boot continues and in the ramstage the rest of GPP
init is executed. There is a problem that nobody sets properly the
PortDetected flags in the S3 path. As the consequence FchGppDynamicPowerSaving()
thinks the GPP port is not enabled and shut downs it.

The best fix would be also to remove the CMOS dependency which
might be some left over, because AGESA does not use CMOS much for
anything else. There could be also some way how to pass the GPP state
structure from romstage to ramstage possibly via hudson/resume.c
but I don't know how to do that. Similar problem is that the "late"
stage of init again "forgets" the PortDetected state.

This fix fixes the resume issue on Asus F2A85-M. With this patch applied
both GPP ports (used as PCIe x1 and internal ethernet) are working again
after resume.

Change-Id: Idaf609043abb09441c6790504d66d23e0637588f
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/4671
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-01 21:44:31 +01:00
Vladimir Serbinenko d69757bd4e lenovo/x201: Skip AT24RF08 detection.
AT24RF08 was inherited from RE of original BIOS. As we don't really care
if the chip in question is really AT24RF08 or a generic replacement,
we can skip this check.

Change-Id: I862dd66b2332314beb835f215f1c1cd838aa07b9
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4769
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-02-01 20:17:59 +01:00
Vladimir Serbinenko 707b35bcdd pcengines/alix6: Make clone declaration in line with other clones.
Change-Id: I4e56f6b37314bff569728b732b4115fb940f70dd
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4756
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-01 20:17:52 +01:00
WANG Siyuan 55f9a731b8 AMD hudson and yangtze: add IMC fan control support
imc_reg_init: init fan control related registers.
enable_imc_thermal_zone: AGESA does not enable thermal zone. We enable
it here.

Change-Id: I93c729982d78b6d2c7c20bcb1a3e27a7dd0eba91
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/4300
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-02-01 19:07:19 +01:00
Vladimir Serbinenko 62adc4c610 lenovo: Handle EEPROM/RFID chip.
EEPROM/RFID chip present in thinkpad should be locked in a way to avoid
any potential RFID access.

Read serial number, UUID and P/N from EEPROM.

This info is stored on AT24RF08 chip acessible through SMBUS.

Change-Id: Ia3e766d90a094f63c8c854cd37e165221ccd8acd
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4774
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-02-01 18:48:16 +01:00
Vladimir Serbinenko 5f20dbfbe3 ibexpeak: add smbus_write_byte
Change-Id: I045f1cff794d3c965c502fff98dd2442af2143bd
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4839
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-02-01 18:43:11 +01:00
Vladimir Serbinenko e57718f522 bd82x6x: Add smbus_write_byte
Change-Id: Iaab076cc014a1ee463866c243636f4f71798ddc4
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4838
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-02-01 18:41:24 +01:00
Vladimir Serbinenko dec919890e smbus: Add guards to avoid calling NULL.
Many of SMBus functions are unavailable on many controllers.
While calling unavailable function is bad, it shouldn't lead
to spectacular crash.

Change-Id: I7912f3bbbb438603893223a586dcedf57e8a7e28
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4837
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-02-01 18:38:32 +01:00
Vladimir Serbinenko 5ef4220693 cpu/intel/model_2065x: Add model 20652
Found in some X201t.
Tested on X201t.

Change-Id: I3fc4c3f5b1abf9fe61746ab8f401d1b6ee67f3ea
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5090
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-01 16:41:11 +01:00
Aaron Durbin 452d31ad75 baytrail: introduce pattrs
The pattrs structure is intended for the supporting coreboot
code to reference instead of going back to the source of
the values (msrs, cpuid, etc). It essentially serves as a global
structure for collecting attributes about the platform/processor.

Additionally, the implementation provides a point during boot to
hoook work before device enumeration/initialization by providing
a init() function to soc_intel_baytrail_ops that is called before
device work in the boot state machine.

BUG=chrome-os-partner:22862
BUG=chrome-os-partner:22863
BRANCH=None
TEST=Built and booted. Noted pattrs output.

Change-Id: I073da8aca29635146fb0d4a2625b2b7564fd8414
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170403
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4854
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-01-31 20:42:37 +01:00
Aaron Durbin 4c53df4730 baytrail: add dunit access and registers
The dunit on baytrail is the dram unit. Provide a means
to access the configuration registers there using the
proper IOSF mechanisms.

BUG=chrome-os-partner:22875
BRANCH=none
TEST=Built and booted. Able to read dram registers.

Change-Id: I4d5c019720a7883fe93f3e1860bcd57ce2ea6542
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170490
Reviewed-on: http://review.coreboot.org/4853
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-01-31 20:42:28 +01:00
Aaron Durbin 191570ded8 baytrail: set host memory map
Prior to this commit the coreboot resource allocator
was not using proper addresses. That's not surprising there
wasn't any code to initialize the resources properly. This
commit initializes the memory map accoring to the BUNIT
registers.

BUG=chrome-os-partner:22860
BUG=chrome-os-partner:22862
BRANCH=None
TEST=Built and booted. Noted output for resource assignments
     is sane.

Change-Id: Ice8d067d8b993736de5c5b273a0f642fa034a024
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170429
Reviewed-on: http://review.coreboot.org/4852
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-01-31 20:42:16 +01:00
Aaron Durbin fda56a6bfd baytrail: add common pci_operations
The coreboot device modeling for pci devices wants
a pci_operations structure for all devices. This structure
just sets the subsystem vendor and device id. Add a common
one that all the other pci drivers can use for Bay Trail.

BUG=chrome-os-partner:22860
BRANCH=None
TEST=Built and booted while utilizing this new structure.

Change-Id: I39949cbdb83b3acb93fe4034eb4278d45369e321
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170428
Reviewed-on: http://review.coreboot.org/4851
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-01-31 20:42:08 +01:00
Aaron Durbin ecf9086389 baytrail: initialize graphics before MRC
The graphics device needs to have its resource contraints
initialized before running the reference code. Right now just
use a 256MiB aperture, 32MiB of stolen memory data, and 2MiB
GTT memory.

BUG=chrome-os-partner:22869
BRANCH=None
TEST=Built and booted. Noted amount of stolen memory matches
     configuration as well as BAR size within the graphics
     device.

Change-Id: I328bf858f288363187cf705d6340947393b5ff10
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170427
Reviewed-on: http://review.coreboot.org/4850
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-01-31 20:41:57 +01:00
Aaron Durbin ba170b4775 baytrail: cache ROM space early in bootblock
Take advantage of the cache early in bootblock. The
intent is to speed up cbfs walking when trying to locate
romstage.

BUG=chrome-os-partner:22857
BRANCH=None
TEST=Built and booted.

Change-Id: If03210103c9782390230915db3b4a9759d172dce
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170426
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4849
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-01-31 20:41:42 +01:00
Aaron Durbin 81d3a2277c baytrail: update microcode to version 313
B2 and B3 steppings are now bumped to version 313.

BUG=chrome-os-partner:22858
BRANCH=None
TEST=Built.

Change-Id: I09ae5110b66c725e959e95fc15bc85ccf371495d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170425
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4848
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-01-31 20:41:29 +01:00
Aaron Durbin 9a7d7bcea5 baytrail: add initial support
The initial Bay Trail code is intended to support
the mobile and desktop version of Bay Trail. This support
can train memory and execute through ramstage. However,
the resource allocation is not curently handled correctly.
The MRC cache parameters are successfully saved and reused
after the initial cold boot.

BUG=chrome-os-partner:22292
BRANCH=None
TEST=Built and booted on a reference board through ramstage.

Change-Id: I238ede326802aad272c6cca39d7ad4f161d813f5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/168387
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4847
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-31 16:36:59 +01:00
Aaron Durbin ba6b07e888 cpu/intel: allow non-packaged scoped turbo setting
In the past the turbo disable setting (bit 38) of the
IA32_MISC_ENABLES msr has been package scoped. That means
knocking the turbo disable bit down enabled turbo for the
entire package. Sadly, that's no longer true on all Intel
processors. Therefore, allow non-packaged scoped turbo
setting by introducing the CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
Kconfig option. It defaults to false which was the original
assumption.

BUG=chrome-os-partner:25014
BRANCH=baytrail
TEST=Built and ran both ways successfully.

Change-Id: I71a31e76ff47878023081fc47da643187517b597
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182405
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/5047
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-30 06:10:26 +01:00
Aaron Durbin cd3f8ad235 x86: Add SMM helper functions to MP infrastructure
In order for the cpu code to start SMM relocation 2 new
functions are added to be shared:
- void smm_initiate_relocation_parallel()
- void smm_initiate_relocation()
The both initiate an SMI on the currently running cpu.
The 2 variants allow for parallel relocation or serialized
relocation.

BUG=chrome-os-partner:22862
BRANCH=None
TEST=Built and booted rambi using these functions.

Change-Id: I325777bac27e9a0efc3f54f7223c38310604c5a2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173982
Reviewed-on: http://review.coreboot.org/4891
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-01-30 06:05:38 +01:00
Aaron Durbin d0520406ed x86: add SMM save state for 0x0100 revision
The Bay Trail SMM save state revision is 0x0100.
Add support for this save state area using the
type named em64t100_smm_state_save_area_t.

BUG=chrome-os-partner:22862
BRANCH=None
TEST=Built and booted using this structure with forthcoming CLs.

Change-Id: Iddd9498ab9fffcd865dae062526bda2ffcdccbce
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173981
Reviewed-on: http://review.coreboot.org/4890
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-01-30 06:05:25 +01:00
Aaron Durbin e0785c0331 x86: parallel MP initialization
Provide a common entry point for bringing up the APs
in parallel. This work is based off of the Haswell one
which can be moved over to this in the future. The APs
are brought up and have the BSP's MTRRs duplicated in
their own MTRRs. Additionally, Microcode is loaded before
enabling caching. However, the current microcode loading
support assumes Intel's mechanism.

The infrastructure provides a notion of a flight plan
for the BSP and APs. This allows for flexibility in the
order of operations for a given architecture/chip without
providing any specific policy. Therefore, the chipset
caller can provide the order that is required.

BUG=chrome-os-partner:22862
BRANCH=None
TEST=Built and booted on rambi with baytrail specific patches.

Change-Id: I0539047a1b24c13ef278695737cdba3b9344c820
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173703
Reviewed-on: http://review.coreboot.org/4888
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-01-30 06:05:02 +01:00
Aaron Durbin 75e297428f coreboot: config to cache ramstage outside CBMEM
Haswell was the original chipset to store the cache
in another area besides CBMEM. However, it was specific
to the implementation. Instead, provide a generic way
to obtain the location of the ramstage cache. This option
is selected using the CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
Kconfig option.

BUG=chrome-os-partner:23249
BRANCH=None
TEST=Built and booted with baytrail support. Also built for
     falco successfully.

Change-Id: I70d0940f7a8f73640c92a75fd22588c2c234241b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172602
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4876
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-30 06:04:02 +01:00
Aaron Durbin 6ac3405fdf x86: include optional reference code blob in cbfs
In order to incorporate external blobs into
CBFS besides MRC have a notion of a reference code
blob. By selecting HAVE_REFCODE_BLOB and providing
the file name the refcode blob will be added to
cbfs as a stage file.

BUG=chrome-os-partner:22866
BRANCH=None
TEST=Using this option and other patches able to build,
     boot, and run blob code.

Change-Id: I472604d77f4cb48f286b5a76b25d8b5bfb0c7780
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174423
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4895
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-30 05:49:47 +01:00
Aaron Durbin 2f6402c7a6 chromeec: allow override of i8042 interrupt
Some boards need to override which IRQ the i8042 keyboard
controller has its interrupt on instead of the default
IRQ#1. The SIO_EC_PS2K_IRQ macro provides the mainboard
an ability to override the interrupt location.

BUG=chrome-os-partner:23965
BRANCH=None
TEST=Built and booted rambi using this option. New IRQ is correctly
     picked up by kernel allowing keyboard support.

Change-Id: Ic2b222018dfc3aa30e24a31009e832ae0fb7e9cf
Reviewed-on: https://chromium-review.googlesource.com/177222
Tested-by: Bernie Thompson <bhthompson@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4978
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-01-30 05:36:33 +01:00
Duncan Laurie 58867b1002 chrome ec: Fix ASL to use IO() instead of FixedIO()
FixedIO seems like a nice short version of IO but in reality
it is limited to 10-bit ISA addresses and so should not really
be used in most situations.

Change all the references to use IO() directly instead.

BUG=chromium:311294
BRANCH=none
TEST=emerge-samus chromeos-coreboot-samus and check for iasl
warnings using updated iasl compiler revision 20130117.
Boot the imge and ensure that EC regions are still exported
in /proc/ioports.

Change-Id: I54de65892bed9e43dbba916990cf2b70c370843c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174810
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4910
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-01-30 05:36:13 +01:00
Aaron Durbin 3a499c3a42 chromeos: provide option to identify reference code blob
Certain platforms need to have reference code
packaged and verified through vboot. Therefore,
add this option.

BUG=chrome-os-partner:22867
BRANCH=None
TEST=Built.

Change-Id: Iea4b96bcf334289edbc872a253614bb1bebe196a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180025
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/5022
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-01-30 05:26:38 +01:00
Duncan Laurie 16e899ba94 cbmem: Export ACPI GNVS cbmem pointer in coreboot table
This will make it possible for payloads to find the ACPI
NVS region which is needed to get base addresses for devices
that are in ACPI mode.

BUG=chrome-os-partner:24380
BRANCH=none
TEST=build and boot rambi with emmc in ACPI mode

Change-Id: Ia67b66ee8bd45ab8270444bbb2802080d31d14eb
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179849
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5015
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-01-30 05:26:14 +01:00
Aaron Durbin d37705c3b0 vboot: provide empty vboot_verify_firmware()
In the case of CONFIG_VBOOT_VERIFY_FIRMWARE not being
selected allow for calling vboot_verify_firmware()
with an empty implementation. This allows for one not to
clutter the source with ifdefs.

BUG=chrome-os-partner:23249
BRANCH=None
TEST=Built with a !CONFIG_VBOOT_VERIFY_FIRMWARE and non-guarded
     call to vboot_verify_firmware().

Change-Id: I72af717ede3c5d1db2a1f8e586fefcca82b191d5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172711
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4879
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-30 04:13:00 +01:00
Duncan Laurie d4322565ed VBOOT: Set virtual recovery switch based on EC Software Sync
The Virtual Recovery switch flag needs to be set in coreboot since
it is passed through directly to VBOOT layer by depthcharge.

Rather than add a new config option we can assume that devices with
EC Software Sync also have a virtual recovery switch and set the
flag appropriately.

BUG=chrome-os-partner:25250
BRANCH=all
TEST=build and boot on rambi, successfully enter developer mode

Change-Id: Id067eacbc48bc25a86887bce8395fa3a9b85e9f2
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183672
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5061
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-30 03:25:09 +01:00
Edward O'Callaghan 5760e197b3 AGESA boards: Clean up definition of BIOS_SIZE in platform_cfg
Clean up vendor code from hard coded #define if-def chain with a
pre-processor shift and subtract.

Change-Id: Ibce34ab576d7db8586a6ec8f9b2460268e0e1878
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/4811
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-01-29 20:06:57 +01:00
Aaron Durbin 029aaf627c x86: add common definitions for control registers
The access to control registers were scattered about.
Provide a single header file to provide the correct
access function and definitions.

BUG=chrome-os-partner:22991
BRANCH=None
TEST=Built and booted using this infrastructure. Also objdump'd the
     assembly to ensure consistency (objdump -d -r -S | grep xmm).

Change-Id: Iff7a043e4e5ba930a6a77f968f1fcc14784214e9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172641
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4873
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-28 23:12:27 +01:00
Aaron Durbin f545abfd22 rmodule: consolidate rmodule stage loading
There are 3 places rmodule stages are loaded in the
existing code: cbfs and 2 in vboot_wrapper. Much of the
code is the same except for a few different cbmem entry
ids. Instead provide a common implementation in the
rmodule library itself.

A structure named rmod_stage_load is introduced to manage
the inputs and outputs from the new API.

BUG=chrome-os-partner:22866
BRANCH=None
TEST=Built and booted successfully.

Change-Id: I146055005557e04164e95de4aae8a2bde8713131
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174425
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4897
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-28 22:29:42 +01:00
Aaron Durbin 16000c883e spi: Add support for Winbod W25Q64DW
The W25Q64DW spi part is programatically equivalent
to the other W25Q64 parts except it operates at 1.8V.
Just add a new entry with the appropriate ID.

BUG=chrome-os-partner:22292
BRANCH=None
TEST=SPI controller can program the part.

Change-Id: I65b0261223a9fefcb07477a43b6a3edb8228dd03
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170011
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/5077
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-28 22:24:06 +01:00
Aaron Durbin bf18b17cf3 cbmem: add reference code ids
In order to identify the ram used in cbmem for
reference code blobs add common ids to be consumed
by downstream users.

BUG=chrome-os-partner:22866
BRANCH=None
TEST=Built and booted with ref code support. Noted reference
     code entries in cbmem.

Change-Id: Iae3f0c2c1ffdb2eb0e82a52ee459d25db44c1904
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174424
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4896
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-01-28 19:54:57 +01:00
Aaron Durbin 3674ccfa3e x86/mtrr: don't assume size of ROM cached during CAR mode
Romstage and ramstage can use 2 different values for the
amount of ROM to cache just under 4GiB in the address
space. Don't assume a cpu's romstage caching policy
for the ROM.

Change-Id: I689fdf4d1f78e9556b0bc258e05c7b9bb99c48e1
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4846
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-01-28 19:54:49 +01:00
Aaron Durbin e6767674af intel: fix microcode compilation failure in bootblock
When not building with CONFIG_SSE there are not enough
registers for ROMCC to use for spilling. The previous
changes to this file had too many local variables that
needed to be tracked -- thus causing romcc compilation
issues.

Change-Id: I3dd4b48be707f41ce273285e98ebd397c32a6a25
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4845
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-28 19:54:29 +01:00
Vladimir Serbinenko ffa81bf29d bachmann/ot200: Fix cmos.layout.
In current cmos.layout baud_rate overlaps with hardcoded reboot byte.
Fix the layout and provide the default for upgrade.

Change-Id: I979b8743c4aab6f17b3acf61b92a74a333203379
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4804
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2014-01-28 14:04:36 +01:00
Aaron Durbin 790e3adc70 chromeos: include stddef to fix compilation error
As some of the standard definitions were shuffled around
chromeos started failing to build. Correct this.

Change-Id: I9927441ccb2d646e8b3395e6e9f8e8166de74ab0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4844
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-28 05:55:33 +01:00
Aaron Durbin a86e81d472 x86: include header to define types in use
The tsc header is using u32 w/o including the file
with defines it.

Change-Id: I9fcad882d25e93b4c0032b32abd2432b0169a068
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4843
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-28 05:55:20 +01:00
Vladimir Serbinenko e660651824 coreboot_table: don't add CMOS checksum twice.
Checksum is already in cmos_layout.bin. No need to add it twice

Change-Id: I6d12f35fd8ff12eee9a17365bbfab38845c09574
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4829
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-27 07:06:02 +01:00
Vladimir Serbinenko a60a3020d9 siemens/sitemp-g1p1: Add missing boot_option option.
Unlike other additions this doesn't require versionning first since
the bootblock reads it anyway from this hardcoded offset.

Change-Id: I3e3f65602bb1b92b91097692ee13e6948a748061
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4832
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-01-27 04:20:30 +01:00
Vladimir Serbinenko 3572f5c6f0 sitemp-g1p1: Migrate to new cmos.default approach
Current code just prints warning, defaults match the behaviour of
current code when checksum is incorrect and look sane.

Change-Id: Icda0d3cb3517fc15e6a0ee787b00276d2d435776
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4827
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-27 04:05:43 +01:00
Edward O'Callaghan 962b6c0a5e superio/fintek: Add initial support for Fintek F71869AD.
Change-Id: I41f1ee20517dd179a4dee914ab7f6332739e326e
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/4784
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-27 00:13:14 +01:00
Alexandru Gagniuc 28684171f0 google/stout: Provide cmos.default
Change-Id: Ief0d08e0cd3dc469d700acf8567435894651171e
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4822
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-01-26 22:59:41 +01:00
Alexandru Gagniuc ded4e1266d google/butterfly: Provide cmos.default
Change-Id: I0ec0d80f6c6682a0d3656a0c0743d166b1bc85c2
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4820
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-01-26 22:15:53 +01:00
Denis 'GNUtoo' Carikli 0bf998e34f lenovo/t60: Add CMOS defaults.
The code for handling the invalid CMOS space in mainboard.c
is now useless and so it was removed.

Change-Id: I86ec6a7f73e32948adff9087d4af5372a49a46a5
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3520
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-01-26 21:06:07 +01:00
Vladimir Serbinenko 63e35f207c pc80/keyboard: Ignore interface test failure.
On Asus A8N-E this test fails but if failure is ignored keyboard works.

Change-Id: Ifeeff2f41537b35bc90a679f956fea830b94292c
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4816
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-26 17:39:42 +01:00
Vladimir Serbinenko e0553b436b asus/a8n-e: Implement basic ACPI.
Change-Id: I3c8fa1fbec2175787666697f2239abb70020019e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4819
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-26 16:58:28 +01:00
Vladimir Serbinenko 8540a8b80f asus/a8n-e: Add IRQ for onboard audio.
Now onboard audio works.

Change-Id: I1a598390c980287744689011b40210cec0145c6a
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4818
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-26 16:30:35 +01:00
Vladimir Serbinenko 1bddb02f05 asus/a8n-e: Fix GPIO resources.
Allocator can't currently handle both PnP and PCI resources together.
Only 2 resources in PnP are not fixed. So fix them.

Change-Id: Iad695d1d991d110b726ec429fff87c616af5ac8b
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4815
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-26 16:30:23 +01:00
Vladimir Serbinenko bb6956ad13 asus/a8n-e: supply cmos.default
Change-Id: Ib54cda60c9d8c57885c2b62f978222e01c1c3347
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4814
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-26 16:30:06 +01:00
Paul Menzel 4fe9813adb src/cpu: Fix spelling of MTTR to MTRR
Change-Id: Ia4718ac31a5b2bd12f8cda5e107aa878d74d2a03
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/4805
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-26 15:59:46 +01:00
Alexandru Gagniuc b92f5e884d nb/sandybridge: Move MRC cache above mrc.bin
This small change greatly reduces CBFS fragmentation. There is now a
small gap of only 728 bytes between mrc.bin and mrc.cache, with the
64 KiB alignment maintained for mrc.cache -- assuming systemagent-r6
is used. The gap was just under 64 KiB before.

With this change, it is easier to accommodate fallback and normal
boot stages without having to manually place the stages in the highly
fragmented CBFS.

Change-Id: Ia2340c1928ed6e232949e053d1943c2f5737f741
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4763
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-01-24 19:54:33 +01:00
Vladimir Serbinenko b66b0438c0 asrock/e350m1/board_info.txt: Specify ROM socket and Flashrom support.
Based on info by Kevin O'Connor.

Change-Id: I21d447fec976e0ee967ba64b0f506c97c22917a3
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4765
Tested-by: build bot (Jenkins)
Reviewed-by: Kevin O'Connor <kevin@koconnor.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-24 07:43:54 +01:00
Vladimir Serbinenko 487984e7f3 asus/a8n-e/board_info.txt: Set ROM Protocol.
Change-Id: I65f2faee672d4d7dea50b67cf6426f503034b380
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4760
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-24 07:43:42 +01:00
Vladimir Serbinenko 9c70adf26d intel/microcode: Remove leftover MICROCODE_INCLUDE_PATH.
Not used anymore since microcode was moved.

Change-Id: Id666c80cb20e90e3664c4dcfcc0c41a4aeb4864c
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4788
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-23 20:51:49 +01:00
Vladimir Serbinenko f3c7a9cf9d sandy/ivy SPI: Support hardware sequencing and use with multiple chips
When 2 chips are present to get to the second one you have to use hardware
sequencing. Also use it as the fallback if chip is unknown.

Based on code in flashrom by Stefan Tauner and Carl-Daniel Hailfinger
distributed under compatible license.

Tested on Lenovo X230 which has EN25QH64 (8M) + N25Q032..3E (4M)

Change-Id: I56f3cf0406b5f09fa327ed052c8e8b1df1d8a11f
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4613
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-23 20:42:31 +01:00
Vladimir Serbinenko e23bd0e3c4 SPI: Add API for programmer-specific flashing.
Change-Id: I7a2f5b9ae74458b5ed6271b1c27842c61546dcd2
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4712
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-23 20:42:08 +01:00
Andrew Wu e33d6cac96 keyboard.c: fix coding style with indent
Change-Id: Ie8efa9fb9bdc65bf8015eec197f44c432e87d907
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3986
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-23 20:41:44 +01:00
Andrew Wu a4ae3107ca dmp/vortex86ex: Initialize I2C controller base address/IRQ
Change-Id: Iefd6852f2300f703ebed8b52aee627107a024f85
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/4570
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-23 20:40:53 +01:00
Vladimir Serbinenko 77c70a06e1 lenovo/x230: Enable wacom USB port
Based on lsusb -t info from David Schissler.

Change-Id: I061881f531b11dc6f5f7719269cf9f3c9b0b99e1
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4786
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-23 20:38:36 +01:00
Vladimir Serbinenko 2657e84109 Multiboot: remove multiboot tables generation.
GRUB2-as-payload doesn't use them. Libpayload can live with just coreboot tables
if loaded as payload. memtest86+ can use them but is buggy with them. Solaris
needs a huge boot archive not supported by coreboot and too big to fit in
flash (dozens of megabytes). All-in-all looks like no users are left for this.

Change-Id: Id92f73be5a397db80f5b0132ee57c37ee6eeb563
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4628
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-01-23 20:37:48 +01:00
Vladimir Serbinenko b2939f7486 lenovo/x230: Add missing copyright line.
Change-Id: I5ecd25e23cebf83d4ae9300307aaac527e05c377
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4778
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-23 20:33:27 +01:00
Vladimir Serbinenko 4c8b1ee14a X201: Enable expresscard hotplug.
Change-Id: Ieefc2ad775c16de9aa974b2602d55ee047c9f568
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4643
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-23 20:32:41 +01:00
Vladimir Serbinenko 786c0f5fca nehalem: Fix SMRAM register address
Change-Id: If6646853039d15d6ba0fcf2b9b9b0658004be6e6
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4787
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-23 20:29:52 +01:00
Vladimir Serbinenko 969f8617e9 lenovo/x201: Reinit CBMEM only on S3 resume.
Change-Id: I0643cdab10cda3f19ab56223f5fa77376a8046ac
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4782
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-23 19:57:09 +01:00
Vladimir Serbinenko bca985557e X201: Move early nehalem S3 magic to right place.
This MCH magic needs to be done before GPIO.

Now S3 (Suspend-to-RAM) works on X201.

Change-Id: I319e57af52ff01083bfbffbcd883ac5f453320a1
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4632
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-23 19:56:52 +01:00
Vladimir Serbinenko f7a42de725 nehalem: Restore frequency ratio registers on S3 resume
Previously registers 274/265 and 6dc/6e8 were recomputed
which lead to a slightly different values. On
S3 resume it needs to be a perfect match.

Change-Id: I14f42c7659dde5f327979831fcb1f84ea0c78dee
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4634
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-23 19:56:31 +01:00
Vladimir Serbinenko f62669c966 nehalem: Small cleanup to raminit RE bindings
Change-Id: Ifd3f172a1c8a108909d1a7dae94f926b2778c2b1
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4633
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-23 19:55:57 +01:00
Vladimir Serbinenko 1cd937b48c Ibexpeak: add missing thermal init.
Without it ME doesn't always start correctly and no temperature is reported,
no fan management and so on.

Change-Id: Iff71f3afbc35a1453a20d182890ae2d196c556bd
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4636
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-23 19:49:39 +01:00
Vladimir Serbinenko 82926e1d16 nehalem: Move mrc.cache to 0xfffe0000.
On nehalem there is no MRC.bin. To avoid excessively fragment the CBFS,
put MRC.bin as high as possible.

Change-Id: Ia3f7aef5a1e62a42c9fa9ea0f6eec2b29eb6722d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4708
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-23 19:41:53 +01:00
Vladimir Serbinenko cc16ffc7cb X201: Add missing LPC registers
Without them PMH7 is inaccessible from running system.

Change-Id: Ib5a524325040e253a9d914906f90263fc208c313
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4655
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-23 19:40:37 +01:00
Vladimir Serbinenko 24356dd5c1 X201: Add missing CPU counter.
Change-Id: If9f10ef40193fc84ab1849429b5af678ffe831b2
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4624
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-23 19:40:07 +01:00
Vladimir Serbinenko bd89699516 nehalem: Simplify acpi.c by using __SIMPLE_DEVICE__
Change-Id: I93351a2716cd58c2006400cecca1390b1704e94b
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4603
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-23 19:39:45 +01:00
Vladimir Serbinenko 517406aac7 X201: Add azalia verb.
Adds missing sound codec configuration.

Change-Id: I3a7097ab0a7c85524f2400471323f5d2d15569ed
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4641
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-23 19:39:15 +01:00
Alexandru Gagniuc 0dbea2322a board_info.txt: Add ROM information for google butterfly
Change-Id: I7d973ef41c4f2973e71015ec292ae88faaeb5840
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4766
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-01-23 04:06:04 +01:00
Vladimir Serbinenko 4737b0c2cc lenovo/x230/dsdt.asl: Change space to tab.
Change-Id: I9e6d39a5a08fe9fd27daeca0e8393ff019b722d4
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4779
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-01-23 03:51:19 +01:00
Vladimir Serbinenko 52884ad161 board_info.txt: Classify almost all remaining boards.
Based on info from commit messages (most devel/eval boards are mentioned
as such in commit message) and information from vendor sites (mostly based
on form factor).

Classification for siemens/sitemp_g1p1 is based on info by Nico Huber.

For Google boards based on info from ML posted by Aaron Durbin.

Remaining unclassified board is:
google/pit

For which very little info is available publically.

Change-Id: I12dfff4c629811a48cfc77be27bdc5081530b8f6
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4759
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-01-22 22:05:39 +01:00
Kyösti Mälkki d1443aa60b CBMEM: Rename cbmem_reinit()
This function does not really initialize anything, but only
checks for the TOC.

Change-Id: I9d100d1823a0b630f5d1175e42a6a15f45266de4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4669
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-22 21:38:57 +01:00
Kyösti Mälkki 6f1d26e258 lenovo/x230: Fix CBMEM
Fix build. Changes to static CBMEM functions were written before
this board was in tree.

Change-Id: I6b20d0c2815337edc330d384a409f1f939727c2b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4781
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-01-22 21:32:00 +01:00
Kyösti Mälkki fa8cedae2a AMD K8/fam10: Fix CBMEM on S3 resume
Change to use cbmem_recovery() to wipe CBMEM region and reset
ACPI wakeup if CBMEM TOC was not found.

Change-Id: Ic362253eaa00bd442d4cc0514632f9096e20bfa6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4673
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-22 20:55:55 +01:00
Kyösti Mälkki 47770c0769 AMD AGESA: Fix CBMEM on S3 resume
Change to use cbmem_recovery() to wipe CBMEM region and reset
ACPI wakeup if CBMEM TOC was not found.

Change-Id: I6648570d76b5c137f50addcc5bce9c126d179c65
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4672
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-22 20:55:20 +01:00
Kyösti Mälkki 2d8520b275 CBMEM: Replace cbmem_initialize() with cbmem_recovery()
The replacement function confirms CBMEM TOC is wiped clean on power
cycles and resets. It also introduces compatibility interface to ease
up transition to DYNAMIC_CBMEM.

Change-Id: Ic5445c5bff4aff22a43821f3064f2df458b9f250
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4668
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2014-01-22 20:54:57 +01:00
Kyösti Mälkki 97e1b11f41 lenovo/x201: Really do EARLY_CBMEM_INIT
The board was missing cbmem_initialize() call in romstage. Selecting
EARLY_CBMEM_INIT implies this is done in romstage.

Change-Id: I9ec93f89fe4cbb9e729532be36db601b6e62bca6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4667
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-01-22 20:53:48 +01:00
Kyösti Mälkki 886a543d60 roda/rk9: Add EARLY_CBMEM_INIT
Change-Id: I450f78cce7172fd2dee66dc81b4f33e07c1aff09
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4664
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-22 20:53:20 +01:00
Kyösti Mälkki a7c9611712 intel/i945 boards: Add EARLY_CBMEM_INIT
Inspired by commits ac6ea04b and 4560ca50 that enabled this feature
for lenovo/x60 and lenovo/t60 with i945 chipset.

Change-Id: Ia04f58b8c3769b5734708c6a338bb80c13c5aeba
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3994
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-01-22 20:53:00 +01:00
Vladimir Serbinenko 66fd775168 emulation/qemu-armv7: Fix wrong stack parameters.
Now it boots up to message "Could not find payload".

Change-Id: I07ddca7046492f7e0dec15a8ea00c2870b09ee67
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4754
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-22 19:38:12 +01:00
Vladimir Serbinenko e7e9502d46 Lenovo X230: new port
probably a problem in MRC:
- EHCI output failure after sysagent
- no S3
- no MRC cache
- MRC needs watchdog
- less MTRR could be used by some memory map optimisations

Not tested:
- dock (probably doesn't work)
- msata (probably works)
- wwan (probably works)
- mini displayport (probably works)

Blobs:
MRC
VGA Oprom

Change-Id: I5bdb9372971f48e048848d57b6c924b79782dbde
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4679
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-22 16:44:57 +01:00
Patrick Georgi df29f1ba6f CAR_GLOBAL: Define section details once
Improve clang compatibility by dropping an opaque hack

The section attribute was only ever meant for specifying
section names, not their properties - otherwise they would
have provided section(name,attribute,class) instead of only
section(name).

The hack to add attribute and class to the name, and commenting
out the "real" definitions inserted by the compiler (see the
terminating "#"), is refused by clang developers.

This is a cleaner implementation in that the section is first
declared with its properties, then used later-on, expecting that
later conflicting declarations are ignored.

It can still break in two ways:
1. The assembler or linker could complain about a section declared
in two different ways.
2. The assembler could just use the latest declaration, not the first,
to determine the section's properties.

I won't sort these out unless they actually happen.


Change-Id: I4640b0fc397b301102dde6dc3ea1a078ce9edf1c
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/4716
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-21 19:05:25 +01:00
Vladimir Serbinenko 9609823ed8 sandybridge/igd: Add brightness register descriptions
Needed for brightness control for Lenovo X230

Change-Id: Ib6d127d2e050671dd402c31af06ff4726f65156c
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4618
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2014-01-21 16:33:46 +01:00
Alexandru Gagniuc 74230c32ce google/butterfly: Remove unused cmos.layout options
Do not expose options that are unsupported by the board. I tried for
a couple of days to see why hyperthreading wasn't working. It's not
supported by the CPU. The same applies to the baud_rate option. It
makes no sense to expose it to userspace via nvramtool.

Change-Id: I89b91820616d92fb4db20bf77f4b7f48a70353d5
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4697
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-20 13:47:00 +01:00
Vladimir Serbinenko 484a5bfffe X201: Fix SMI bindings.
Doesn't have a visible effect currently but it's better if those
bindings are correct.

Change-Id: I0f1a468e59429b14db139cc48e1e68c0e1841300
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4645
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-20 11:44:55 +01:00
Vladimir Serbinenko 51634d25bc google/falco/board_info.txt: Declare as a laptop.
Change-Id: I42c77d03b6a5f8ef88f1276de543bb3fc55467af
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4755
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-20 03:21:02 +01:00
Vladimir Serbinenko 14813b3241 board_info.txt: Add mentions of thin client names.
Based on info from old page

Change-Id: Ibd07b5904569e510de249e4216875438a855ff57
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4746
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-19 20:00:06 +01:00
Vladimir Serbinenko 39268299c0 linutop: Add Linutop-1 as a clone of artecgroup/dbe61
Change-Id: I69e99e2a1bf9b890281caaf0633f91850d923241
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4747
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-19 19:10:31 +01:00
Vladimir Serbinenko 047c10c0f8 boardstatus: Add new category "sbc".
Change-Id: I8a7bf265ebb30dd5997f93729a0329e74f463a23
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4739
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-01-19 03:20:08 +01:00
Vladimir Serbinenko 14a703045d boardstatus: Add category "emulation".
Change-Id: If9d26b9e4cb1895452316c9cf2e8c75a01cfd7c2
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4738
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-01-19 03:17:18 +01:00
Vladimir Serbinenko 13cd4907f2 board_info.txt: Remove some needless name overrides.
Overrides were to have names in line with wiki but names derived from the
tree are better in some cases.

Change-Id: Ic805ba9a3b9c7f926dc9ef27f8673f2c18e9af34
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4737
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-01-19 03:09:49 +01:00
Vladimir Serbinenko 2e71e55d33 board_info.txt: Change iei/kino's link to web.archive.org.
Original link is dead.

Change-Id: I56e975ee411f7290c12aad501f490ccc5dedaf05
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4736
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-19 03:09:25 +01:00
Vladimir Serbinenko 1af25246a9 board_info.txt: declare chromebooks as laptops.
Change-Id: I4a3ed7e9b6aaec8aba8ffc47eafdbcca31e4c700
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4734
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-01-19 02:57:16 +01:00
Vladimir Serbinenko 9514f5a901 board_info.txt: Categorize various boards
Info supplied by: idwer

Change-Id: I3086e8118a721ded33c578c6c82e20642ef9d776
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4733
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-01-19 02:47:06 +01:00
Vladimir Serbinenko 0fc8ed6318 boardstatus: Remove some needless name overrides.
Overrides were to have names in line with wiki but names derived from the
tree are better in some cases.

Change-Id: Iff3c27db1a4936b03f976c82d872589e41df0c90
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4735
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-19 02:46:54 +01:00
Vladimir Serbinenko 2eaf3b4e3a boardstatus: Handle clones.
Change-Id: I7bfe19eb800729713a549dc0396765a9785e11b1
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4732
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-19 02:18:33 +01:00
Vladimir Serbinenko acca285973 board-status: Add board_info.txt manually for irregular wiki entries
Based on info from wiki.

Change-Id: Iebd799abe48550c4df55632b8177d845df7d9a7d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4706
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-19 02:00:35 +01:00
Vladimir Serbinenko 4333071e23 board-status: Add board_info.txt extracted from wiki.
board_info.txt is a file to be used by board-status to add
some useful info to the generated table like flash chip type.
This series is autogenerated from wiki page Supported_Motherboards.

Change-Id: Ie2bda900713ef4883134477163320936c84c34f5
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4701
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-19 01:35:03 +01:00
Vladimir Serbinenko af771885a5 jetway/j7f4k1g2e and jetway/j7f4k1g5d: Add as clones of jetway/j7f2.
Change-Id: I16e027b78dc65538d8f0cd6f5e57bbdfc10b7169
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4729
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-01-19 00:40:32 +01:00
Vladimir Serbinenko 2cb9685860 jetway/j7f24: Rename to jetway/j7f2.
Original actually meant j7f[24] which without square brackets
became confusing.  There is no such board as j7f24.

This is a prerequisite to adding j7f4* as cloned boards

Change-Id: Ia7708b13ac4141ef788183c7817fce1366919936
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4728
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-01-19 00:18:05 +01:00
Vladimir Serbinenko fb07108894 via/epia-mii and via/epia-ml: Add as clones of epia-m.
Change-Id: I4f297e7a7332acc6ceda6a99981599e3a372b696
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4727
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-01-19 00:05:57 +01:00
Vladimir Serbinenko f16d9c6bcc iei/rocky-512: Add it as an explicit clone of juki-511p.
Change-Id: I87e2768de6728658a87729998648514824d79fd6
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4726
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-01-18 23:56:37 +01:00
Vladimir Serbinenko e66548d010 A8N-SLI: Add it explicitly as a clone of A8N-E
Change-Id: Ieab7d46177eb92393914f8cb055675df00a9a375
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4723
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-18 23:56:29 +01:00
Alexandru Gagniuc 07d881a02d cpu/intel: Remove dummy terminators from microcode blobs
Now that CBFS microcode no longer requires a NULL termination, remove the
dummy terminators from all microcode blobs. This also enables microcode
blobs from different CPU models to be linked in the same
cpu_microcode_blob.bin without the terminators getting in the way.

Change-Id: I25a6454780fd5d56ae7660b0733ac4f8c4d90096
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4506
Tested-by: build bot (Jenkins)
2014-01-16 05:35:28 +01:00
Alexandru Gagniuc 2c38f50b4a cpu/intel: Make all Intel CPUs load microcode from CBFS
The sequence to inject microcode updates is virtually the same for all
Intel CPUs. The same function is used to inject the update in both CBFS
and hardcoded cases, and in both of these cases, the microcode resides in
the ROM. This should be a safe change across the board.

The function which loaded compiled-in microcode is also removed here in
order to prevent it from being used in the future.

The dummy terminators from microcode need to be removed if this change is
to work when generating microcode from several microcode_blob.c files, as
is the case for older socketed CPUs. Removal of dummy terminators is done
in a subsequent patch.

Change-Id: I2cc8220cc4cd4a87aa7fc750e6c60ccdfa9986e9
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4495
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-01-16 05:34:25 +01:00
Vladimir Serbinenko b4c39902ed butterfly: fix compilation with !CHROMEOS
One of arguments to cbfs_get_file_content was missing.

Change-Id: Icb4ef26f18d63c133bc32f1c62a524edee0621ea
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4696
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-16 04:34:30 +01:00
Idwer Vollering c18e52122d AMD Hudson: show POST codes on a PCI device
Show POST codes on a PCI device: implement hudson_pci_port80().
Remove the comments that use pci_locate_device():
using the code found in the comment seems to break booting.

This shares much code with sb600/sb700/sb800,
however the deduplication work needs to be discusses somewhere else
than in this review board.

Tested on an Asus F2A85-M.
The contribution is (C) by Rudolf Marek.

Change-Id: I54fb1dcb0614452c775ed70d867ab44ff263a61a
Author: Rudolf Marek <r.marek@assembler.cz>
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/4559
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-01-15 22:27:21 +01:00
Paul Menzel be8d23a3b5 cpu/amd/model_fxx/powernow_acpi.c: Comment out set but unused variable `Start_vid`
When adding support for PSS object generation for AMD pre Family Fh CPUs
(199c694f) the function `pstates_algorithm` was copied and adapted, but
`Start_vid` is not needed anymore as a static table is used. I’d remove
the variable, but Ron Minnich requested to leave it there for
documentation purposes. So just comment it out.

Change-Id: I3002951d168cade6461941c16d78373c47792e13
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/4036
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-01-15 22:20:20 +01:00
Vladimir Serbinenko 01d06dc67b ROMSIZE: Add option for 12M chips.
On X230 2 real chips (8 + 4) are merged into one virtual 12M chip.

Change-Id: I49c251b1777fc9edccebc4a204b9c4a087bf2a8e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4688
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-01-15 16:35:53 +01:00
Kyösti Mälkki 78938481eb Intel (sandy/ivy): Avoid calling cbmem_initialize() twice
Delay the copying of MRC cache data from CAR to CBMEM until after
sdram_initialize() returns and cbmem_initialize() completes.
Calling cbmem_initialize() twice would complicate the decision logic
of when CBMEM area needs to be wiped clean.

Change-Id: Ic59e94cb2436293efc47b52f7418f5dbf76c714a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4666
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-15 15:33:54 +01:00
Kyösti Mälkki 1e5cacc8f8 google/stout: Add EARLY_CBMEM_INIT
Required for MRC cache and for HAVE_ACPI_RESUME to work.

Change-Id: I7d48b167bd581d7c14ca50bd46e74be0133cecfb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4665
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-15 15:31:15 +01:00
Kyösti Mälkki cb08e169cf CBMEM intel: Define get_top_of_ram() once per chipset
Only have one definition of get_top_of_ram() function and compile
it using __SIMPLE_DEVICE__ for both romstage and ramstage.

Implemented like this on intel/northbridge/gm45 already.
This also adds get_top_of_ram() to i945 ramstage.

Change-Id: Ia82cf6e47a4c929223ea3d8f233d606e6f5bf2f1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3993
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-15 15:29:52 +01:00
Kyösti Mälkki bbf013c38f nehalem/sandy/ivy/haswell: Enable WRPROT cache for all of flash
CBFS could start from below 4MB, and should be cacheable for the
purpose of early microcode update and CBFS search for romstage file.

Change-Id: Ia2a1c6e5fdcc3201fafc8cf5c841cebbbf0b30c9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4626
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-15 15:27:33 +01:00
Kyösti Mälkki 107f72e674 Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR
This change allows Kconfig options ROM_SIZE and CBFS_SIZE to be
set with values that are not power of 2. The region programmed
as WB cacheable will include all of ROM_SIZE.

Side-effects to consider:

Memory region below flash may be tagged WRPROT cacheable. As an
example, with ROM_SIZE of 12 MB, CACHE_ROM_SIZE would be 16 MB.
Since this can overlap CAR, we add an explicit test and fail
on compile should this happen. To work around this problem, one
needs to use CACHE_ROM_SIZE_OVERRIDE in the mainboard Kconfig and
define a smaller region for WB cache.

With this change flash regions outside CBFS are also tagged WRPROT
cacheable. This covers IFD and ME and sections ChromeOS may use.

Change-Id: I5e577900ff7e91606bef6d80033caaed721ce4bf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4625
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-01-15 15:26:48 +01:00
Vladimir Serbinenko 5e73be2a7a sandybridge: Allow skipping mrc.cache
On X230 MRC fails if cache is passed to it. Until better solution is found
do not create mrc.cache

Change-Id: I7e70ebe3c4879e7ab33a9c95a0c9e40408ff5ca4
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4680
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-15 14:56:01 +01:00
Alexandru Gagniuc 1b4cbafe1d cpu/allwinner/a10: Clarify positioning of boot stages
This fixes a number of potential issues, such as generating a build
failure if the bootblock is too large, and making sure romstage and
ramstage cannot overlap in memory.

Change-Id: I4ca9ad097b145445316bcd962e007731b08a7fda
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4687
Tested-by: build bot (Jenkins)
2014-01-14 14:15:25 +01:00
Alexandru Gagniuc 93b600ded7 cubieboard: Setup CPU clock in romstage and load ramstage
This completes the romstage for the cubieboard.

Change-Id: If3272d8a9e414f782892bc41b34b5e2dece5d7e1
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4686
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-14 14:15:12 +01:00
Alexandru Gagniuc 601b5b5302 cpu/allwinner/a10: Add helper to configure CPU clock
Change-Id: I5a3bb3220aeefdd6822a7dbecf210ff77095dad6
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4685
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-14 14:14:58 +01:00
Alexandru Gagniuc 594ef81326 lib: Add log2 ceiling function
Change-Id: Ifb41050e729a0ce314e4d4918e46f82bc7e16bed
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4684
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-14 14:14:46 +01:00
Alexandru Gagniuc 3dd0e72d3b lib/hexdump: Take const void * and size_t as arguments
Representing a memory location as an unsigned long is specific to
32-bit architectures. It also doesn't make sense to represent a length
assumed to be positive as a signed integer. With this change, it is no
longer necessary to cast a pointer to unsigned long when passing it to
hexdump.

Change-Id: I641777d940ceac6f37c363051f1e9c1b3ec3ed95
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4575
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-14 08:07:44 +01:00
Alexandru Gagniuc 8e053afa86 cubieboard: Configure system voltages from devicetree
Change-Id: I93bac9bf94f5bafcd3ff0c3d5763b31d3ee9959b
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4640
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-13 06:25:01 +01:00
Alexandru Gagniuc abe9b81e83 xpowers/axp209: Add helper to set voltages from devicetree config
Change-Id: I3ffe225b78f88c3c2d3a15292c43009e69413afb
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4638
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-13 06:24:54 +01:00
Alexandru Gagniuc af4bd599ca lib: Make log2() available in romstage on ARM, not just x86
On x86, log2() is defined as an inline function in arch/io.h. This is
a remnant of ROMCC, and forced us to not include clog2.c in romstage.
As a result, romstage on ARM has no log2().
Use the inline log2 only with ROMCC, but otherwise, use the one in
clog2.c.

Change-Id: Ifef2aa0a7b5a1db071a66f2eec0be421b8b2a56d
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4681
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-13 04:03:06 +01:00
Alexandru Gagniuc 910ce01757 cpu/allwinner/a10: Provide utility to make a bootable image
Up until now, we relied on mksunxiboot to prepend the header which
makes coreboot.rom bootable on Allwinner SoCs. If that tool was not
present, the build silently failed.

Integrate this tool into our util/ package, so that we do not have to
rely on mksunxiboot being in PATH.
Our version of mksunxiboot also eliminates some limitations of the
original tool, so we no longer have to use 'dd' to limit the file
size.

Change-Id: Id5a4b1e2a3cb00cd1d6c70e6cbc3cfd8587e8a24
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4656
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-13 04:03:00 +01:00
Alexandru Gagniuc d7b07af621 cpu/allwinner/a10: Clean up include order in Makefile.inc
Alphabetize the sources for each stage (bootblock, rom, ram), and
include twi.c in both romstage and ramstage.

Change-Id: I5526f5a66f6600560005731a3ee536eb858f4ff0
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4639
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-13 04:02:48 +01:00
Alexandru Gagniuc 4d3a89d72a xpowers/axp209: Allow voltages to be sepecified in devicetree.cb
This allows system voltages to be specified uniformly, rather than
hardcoding them for each board. This will be used by cubieboard in an
upcoming patch.

Change-Id: I9dc2d3281d076c359c3fad13688649f7d36c0001
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4637
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-13 04:02:12 +01:00
Alexandru Gagniuc 428eeff923 drivers: Add support for X-Powers AXP209 PMU
Change-Id: I1de0e656a38527b172af1d0b5bcd97acbfc03bf0
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4591
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-13 04:01:48 +01:00
Vladimir Serbinenko 066dcec2fe drivers/spi/eon: Add EN25Q64
chip found in X230 if not using hardware sequencing.

Change-Id: I6ded10d35bfdbbe3d54c4170dd7846c7833f5ff7
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4616
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12 18:07:02 +01:00
Vladimir Serbinenko 09b65e6391 X60: Enable WWAN by default.
Change-Id: I8e51a8fc03c1d7dbbdc11b121b3ea3ec18f65a5a
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4670
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12 18:06:38 +01:00
Vladimir Serbinenko ea9181c76a acpi/ec: Add missing delays
Without these delays on fast systems like X230 the port is read before it's
updated.

Change-Id: I3e01fc348cc5170cec108a05095ba301055ed6b0
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4617
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12 18:06:06 +01:00
Vladimir Serbinenko c2ee6801e8 sandybridge: Use calls rather than asm to call to MRC.
Using asm as it's done currently is unsafe because caller-saved registers
are not declared as clobbered.

Using real call is nicer.

regparm((1)) ensures that argument is passed in %eax as expected.

Change-Id: I7449182582eaa53d4e473bc834b472edd8ee0d30
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4675
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12 18:04:38 +01:00
Vladimir Serbinenko f3c3dae580 ec/lenovo/h8: Add backlight control.
Change-Id: I773793bf53d91ae787bd0d0ae7bd882243196d56
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4678
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12 18:04:27 +01:00
Vladimir Serbinenko eada34faaa ec/lenovo/h8: Make trackpoint enable a CMOS option.
To be consistent with touchpad counterpart.

Change-Id: I72d09b41b964f80a81fbf409ef69dd368834a3e2
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4654
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12 18:04:15 +01:00
Vladimir Serbinenko 1eda31c0a7 ec/lenovo/h8: Remove trackpoint_enable from device tree.
Change-Id: I6652e0ad4e0179950f775bbd0200484907bfc976
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4653
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12 18:04:06 +01:00
Vladimir Serbinenko 8e7e5254e4 ec/lenovo/h8: make wlan config a CMOS option
To stay in line with wwan and bluetooth.

Change-Id: Iafe2dc97fc2aec5c2ad1834659b796a6b079c1bc
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4652
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12 18:03:56 +01:00
Vladimir Serbinenko add3f7fda2 ec/lenovo/h8: Allow control of low-battery beep.
Change-Id: I2f422e83f2afcf0cc3f3ecbace01a8f4f39e87d4
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4663
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12 18:03:46 +01:00
Vladimir Serbinenko 9a3b9c42d3 ec/lenovo/h8: Allow user to disable powermanagement beeps.
They're pretty annoying.

Change-Id: I44d26dc168927a9cedfd6ecc4c9a51a3a7b362c7
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4662
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12 18:03:33 +01:00
Vladimir Serbinenko 6d6298dddc ibexpeak / bd82x6x: Make SATA mode user-visible option.
Ability to choose compatibility mode is interesting for testing payloads and
OS for compatibility with older systems.

As per comments
"ide_legacy_combined # TODO: Does nothing since
		      generations, remove from sb code?"
The "combined" mode was removed. It wasn't used by any mobo and the code for
it is almost identical to IDE one other than few bits relating to interrupt
handling and ISA mode.

Change-Id: I407a8fac753b513812a86bef5abcf39c6d81472e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4658
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12 18:03:23 +01:00
Vladimir Serbinenko 2dd601efaf ibexpeak: Fix timings for IDE mode.
Change-Id: I3c89bb633c32a2c2db349cb4fcbe1ed1c8deb5af
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4657
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12 18:03:13 +01:00
Vladimir Serbinenko 11a7c84f85 ec/lenovo/h8: Implement sticky Fn option.
Useful for accessibility.

Sticky modifier (sticky Fn) is a behaviour of modifier key when
you don't have to hold it pressed to achieve the result. E.g.
with normal Fn brightness up is:
<Press Fn> <Press Home> <Despress Home> <Depress Fn>
With sticky Fn you can do:
<Press Fn> <Depress Fn> <Press Home> <Despress Home>

Change-Id: I4da5adcea02428d936023891de08684cae77c44e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4661
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12 17:42:28 +01:00
Vladimir Serbinenko fc7090b249 ec/lenovo/h8: Add an option to swap ctrl and fn.
Tested on my X201 and X230.

Change-Id: I3c7ec65681157d15c6e87eea64779a08e03ae5a8
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4660
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12 17:42:11 +01:00
Vladimir Serbinenko 1287416822 CBFS: use cbfs_get_file_content whenever possible rather than cbfs_get_file
Number one reason to use cbfs_get_file was to get file length.
With previous patch no more need for this.

Change-Id: I330dda914d800c991757c5967b11963276ba9e00
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4674
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2014-01-12 17:41:58 +01:00
Vladimir Serbinenko 0af61b6c82 lib/cbfs_core.c: Supply size of file as well in cbfs_get_file_content
Change-Id: I5b93e5321e470f19ad22ca2cfdb1ebf3b340b252
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4659
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2014-01-12 17:41:02 +01:00
Vladimir Serbinenko e4ac9c043a ec/lenovo/h8: Remove wlan_enable and wwan_enable from device tree.
wwan_enable was never used.
wlan_enable isn't something for device tree but for CMOS config if at all.

Change-Id: I765d9d6f0b73b7dc5a57c0c630a53b4b7a0b48cb
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4651
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-12 12:07:36 +01:00
Paul Menzel cd47740844 arch/x86/acpi/globutil.asl: Make control method `S2BF` serialized
This changes eliminates a warning from the ASL compiler.

Change-Id: I502cca731b6b4cd3e17c57fc191f1eed10a5a1fe
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/4093
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-01-12 03:44:55 +01:00
Patrick Georgi 5d1ada0f64 intel/fsp: Fix microcode including
IS_ENABLED() requires the full define (incl. CONFIG_ prefix)
but isn't needed here.

Change-Id: I91d504367c75ce3fcecc6fa2499afaa0896595d3
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/4646
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-11 09:46:47 +01:00
Vladimir Serbinenko 54124d3e56 Remove sprintf
Remove sprintf as if you can't easily use snprintf then you probably
have buffer overflow.

Change-Id: Ic4570e099a52d743aca938a2bfadb95981adc503
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4280
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-10 18:08:31 +01:00
Vladimir Serbinenko a37383db80 Replace all occurences of sprintf with snprintf
THis reduces risks of bufer overflows.

Change-Id: I77f80e76efec16ac0a0af83d76430a8126a7602d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4279
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-10 18:08:16 +01:00
Vladimir Serbinenko 4b5012a4a2 console/vsprintf: Implement snprintf
snprintf is a safe variant of sprintf. To avoid buffer overflows
we shouldn't use sprintf at all. But for now let's start by
implementing snprintf in first place.

Change-Id: Ic17d94b8cd91b72f66b84b0589a06b8abef5e5c9
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4278
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2014-01-10 14:13:23 +01:00
Vladimir Serbinenko 697c1ed1ff X201: set default USB debug controller to 2.
The other port is not easily accessible.

Change-Id: I6ea31346a375debcd5fc1c27e4078e3a436715e3
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4635
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-01-09 17:50:37 +01:00
Vladimir Serbinenko 6a7aeb3b35 bd82x6x/ibexpeak: Make DRAM reset gate GPIO configurable
DRAM reset gate GPIO is different on different mobos move it to hidden config
with 60 (current value) as default.

Set it to 10 for Lenovo X201.

Change-Id: I4f3b6876d7c33d4966315091b63a76a9a0064c16
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4622
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-01-09 17:16:12 +01:00
Alexandru Gagniuc ffd4a610ba cpu/allwinner/a10: Import raminit code from uboot
The memory initialization code is a work in progress for uboot, so we
only import the bits needed to get RAM up and running. Any refactoring
is cosmetic, and any functional refactoring should be done in separate
patches, and preferably, in coordination with the sunxi team.
Since it's not yet determined if we should initialize memory during
the bootblock or romstage, we don't add raminit to the build just yet.

Change-Id: I2ec1821942c6970150a02fa3806a257da649e1c9
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4597
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-01-09 06:37:25 +01:00
Alexandru Gagniuc cce6c1c92a cpu/allwinner/a10: Add low-level helpers for DRAM clock control
PLL5 is special in that it controls the DRAM clock, and requires a
fine-grained low-level control which will be needed by raminit code.
This change also brings functionality which will be needed by
raminit.

Change-Id: I25ecc91aa2154e504ceebb9003a5e5728d47f4a3
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4593
Tested-by: build bot (Jenkins)
2014-01-09 06:37:13 +01:00
Alexandru Gagniuc 5d8b0a9fb3 cubieboard: Initialize memory in bootblock
Even though the Allwinner A10 is limited to a 24KiB bootblock, the
memory initialization takes only about 3KiB and leaves enough room for
an MMC or NAND driver, so init the memory early on. The advantage is
that we can eliminate complicated logistics of where to cache CBFS and
where to load the ramstage in SRAM.

Change-Id: Id549552ed509434e831db60deaef28e04d62417f
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4630
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-01-09 01:12:56 +01:00
Alexandru Gagniuc 391622ae30 cubieboard: Keep AHB clock within specs
The CPU was clocked at 384MHz in the bootblock, but the AHB bus has a
maximum rated frequency of 250MHz. Its clock needs to be divided to
keep it within spec. Overclocking the AHB bus hung the CPU when
memory was accessed.

Change-Id: I7cb9cdd1f126b3d5b0446fc68af79b54946bc2d3
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4629
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-01-09 01:06:00 +01:00
Alexandru Gagniuc 30c20e92a2 cubieboard: Turn on green LED during bootblock
Change-Id: I807060bde374e4a42abe306cecf838ab157c9515
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4600
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-01-09 01:05:39 +01:00
Alexandru Gagniuc 919e499a36 cpu/allwinner/a10: Add functions for driving GPIO pins
Change-Id: I9473a6e574c3af02d154a7e30245f0dc0b238300
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4599
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-01-09 01:05:29 +01:00
Alexandru Gagniuc 6ed574a661 cpu/allwinner/a10: Add definitions for in/output GPIO functions
Change-Id: I2b857d3b4c01e39c62e54f753e400e6049f1dbc9
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4598
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-01-09 01:04:07 +01:00
Alexandru Gagniuc a94bed0116 cpu/allwinner/a10: Add function for reading chip revision
Change-Id: Iafbd253235db3914b9382fdb41de2622ef83c6d8
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4596
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-01-09 01:03:01 +01:00
Alexandru Gagniuc bd09dbe330 cpu/allwinner/a10: Implement udelay using timer 0
Change-Id: I4825f0d57696cd28751c59ae133b7e3315fb78e5
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4595
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-01-09 01:02:47 +01:00
Alexandru Gagniuc b70a140bd0 cpu/allwinner/a10: Add definition for gating GPIO S clock
This bit is not documented in the datasheet, but is used in the
upcoming RAM init code.

Change-Id: I697ec222496236ac7690460ee62313ab8b1a2f0b
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4592
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-01-09 01:02:05 +01:00
Alexandru Gagniuc 5c4bde70ae cpu/allwinner/a10: Add basic TWI (I²C) driver
Change-Id: I11b10301199e5ff1a45d9b7d2958cc7b6667a29c
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4588
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-01-08 23:03:46 +01:00
Alexandru Gagniuc bc30b2b225 cpu/allwinner/a10: Refactor API for gating clocks to peripherals
Rather than having to track which bit in which register should be
cleared or set to gate or ungate the clock to a certain peripheral,
provide a simplified enum which encodes the register and bit. This
change comes with a function which decodes the enum and gates/ungates
the clock.

This also removes the register-dependent bitmasks for APB0 and APB1
gating registers.

Change-Id: Ib3ca16e54eb37eadc3ceb88f4ccc497829ac34bc
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4571
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-01-08 23:03:34 +01:00
Alexandru Gagniuc 8226dbbf1d cpu/allwinner/a10: Refactor and document pinmux API
Include a function to multiplex more than one pin at a time. This
is useful for peripherals that have the same function number for
all their pins.
Since we now have two functions for muxing pins, also document
them.

Change-Id: I53997cc3a2586e3cf749cd672f69fb427659c67f
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4565
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-01-08 23:03:19 +01:00
Alexandru Gagniuc be32f51aa1 cpu/allwinner/a10: Clarify the usage of SRAM during bootblock
We have 32KiB of usable SRAM right when we boot. The first 24KiB can
be loaded with our bootblock, while the other 8KiB can be used as
stack during the bootblock stage.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Change-Id: I48d3a37869031c3c1dbc1fab71204d473d64deeb
Reviewed-on: http://review.coreboot.org/4563
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-01-08 23:02:49 +01:00
Alexandru Gagniuc 14964dd372 mainboard: Add preliminary support for A10-based Cubieboard
Add a minimal infrastructure which initializes the system clocks
and serial console.

Change-Id: I768ede6ccf8674ffe9fecd8925cec89768209cab
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4553
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-01-08 22:54:22 +01:00
Alexandru Gagniuc f64111b486 cpu: Add initial support for Allwinner A10 SoC
Add minimal support needed to get a bootblock capable of initialising
a serial console.

Change-Id: I50dd85544549baf9c5ea0aa3b4296972136c02a4
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4549
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-01-08 22:54:08 +01:00
Kyösti Mälkki 4dba06a827 CBMEM: Fix allocation for static CBMEM
CBMEM console buffer size is adjustable in menuconfig, but this would
not correctly adjust the overall allocation made for CBMEM.

HIGH_MEMORY_SIZE is aligned to 64kB and definitions are moved down in
the header file as HIGH_MEMORY_SIZE is not used with DYNAMIC_CBMEM.

Try to continue boot even if CBMEM cannot be created. This error would
only occur during development of new ports anyways and more log output
is better.

Change-Id: I4ee2df601b12ab6532ffcae8897775ecaa2fc05f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4621
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2014-01-06 17:34:44 +01:00
Kyösti Mälkki 5b353002a9 CBMEM: Drop cbmem_base_check()
This function was for logging only, but we have both base and size
already logged elsewhere.

Change-Id: Ie6ac71fc859b8fd42fcf851c316a5f888f828dc2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4620
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-06 17:33:51 +01:00
Kyösti Mälkki cb28f3f8ed CBMEM ACPI: Move resume handler
Handler is ACPI/x86 specific so move details out of cbmem code.

With static CBMEM initialisation, ramstage will need to test for
S3 wakeup condition so publish also acpi_is_wakeup().

Change-Id: If591535448cdd24a54262b534c1a828fc13da759
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4619
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-06 17:33:10 +01:00
Kyösti Mälkki 8526c3a403 usbdebug: Fix hidden menuconfig options
Options for selecting the USB port and controller for usbdebug
were unintentionally hidden with commit 8232bc2c on AGESA platforms
using cimx/sb700 or cimx/sb800.

Change-Id: Ibacc81a580519fe7fa86f08374046625327340b4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4607
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-06 17:31:53 +01:00
Vladimir Serbinenko e51210dbae MRC cache: determine flash size on runtime
It should be possible to put coreboot compiled for smaller chip by
putting it at the end of bigger chip. We already have chip size in
flash->size. Use it.

Tested on Lenovo X230.

Change-Id: If8ff03ed72671a9f2745ed4e759a04e83aa7cc37
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4612
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-01-06 10:06:21 +01:00
Vladimir Serbinenko 00ea28ecf9 nehalem: Simplify smi.c by using __SIMPLE_DEVICE__
Change-Id: Ib5bac45ee7aa5492c10fa97cd75b828b6192250d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4604
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-01-06 10:01:39 +01:00
Vladimir Serbinenko 98dda06e7a cpu/cpu.h: Allow compiling with __SIMPLE_DEVICE__
Change-Id: I14a2ac47198be6359b4f10b38f1cf86c9917d67e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4602
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-01-06 09:47:01 +01:00
Vladimir Serbinenko 503e4fef17 X201: Fix native video init
Due to recent restructuring X201 native video init has disappeared from
config options. Put it back and fix compilation with it.

Change-Id: I6d9ba5da196c093abd2df89a6fe5efefece1fb3c
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4606
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-01-04 12:20:47 +01:00
Paul Menzel fd3451d72d device/Kconfig: Add third person singular s to lacks
Change-Id: I74be0dbbf8d99f58ac28bfac281ccd27d1500078
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/4608
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-01-04 00:04:35 +01:00
Dave Frodin 812d624fd0 asrock/imb-a180: Configure the 6 COM ports and the keyboard
Change-Id: I66d0715f3be201f8068acd7097e2be49185bee00
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/4574
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-03 18:47:48 +01:00
Dave Frodin 6c6acd79a0 superio: Uncomment the w83627uhg UART clock source initialization
The asrock/imb-a180 mainboard is the first mainboard to use this
w83627uhg/nct6627UD sio. The default h/w clock setting is 0. Adding
the SIO in the mainboard Kconfig made the builder complain that the
set_uart_clock_source() wasn't being used. So the calls to that function
were uncommented.

Change-Id: Iedba035237c5c0fa230b02ff4799bb8c1b7bbd4a
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/4573
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-01-03 18:47:22 +01:00
Dave Frodin 892d129220 Add the gizmosphere/gizmo mainboard
Gizmo is a AMD-Family14 based board. More information can
be found at www.gizmosphere.org

Change-Id: I5cfd161b4f408be1f65cf332b083ed7c79a99cfd
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/4536
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-01-03 18:46:37 +01:00
Kyösti Mälkki ea8d4607ce AMD K8 (rev F): Move rev F0/F1 workaround to header
Place this in header so it works also when raminit_f.c and
raminit_f_dqs.c are not #included in romstage.c build.

The workaround remains to be disabled for all boards.

Change-Id: Iff0271ceb21ee1e28a1a31d6bbdb97e29d76461e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4568
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-30 07:20:38 +01:00
Kyösti Mälkki 5c62375222 AMD K8 (rev F): Move MEM_TRAIN_SEQ check to northbridge
Do it just to remove MEM_TRAIN_SEQ test under mainboard/ to see all
K8 rev F boards do the same things here.

Change-Id: If75035a4ef8882c2618d434d83ba59c408593d86
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4567
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-30 07:19:10 +01:00
Kyösti Mälkki 7d3045b517 AMD K8: Define MEM_TRAIN_SEQ only with K8_REV_F_SUPPORT
Change-Id: I601efbff03d0f0f59557b33be8d6928ede310b62
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4558
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-30 07:17:16 +01:00
Kyösti Mälkki b316585eaf AMD K8 (pre-F): Clean platforms without K8_REV_F_SUPPORT
Change-Id: Ie109f58bd8ce54754b8d0b00118e75ace8717df0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4566
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-30 07:15:27 +01:00
Kyösti Mälkki 0946190e15 AMD K8 (rev-F): Always have RAMINIT_SYSINFO
K8 Rev F raminit code cannot be built without RAMINIT_SYSINFO,
so have the option enabled together with K8_REV_F_SUPPORT.
Also move the option under AMD K8.

Change-Id: I91fa0b4ae7e3e54fbcb4a4f91eb043956cd0fb60
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4582
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-29 19:45:50 +01:00
Kyösti Mälkki 239c3d32f0 AMD fam10: Drop RAMINIT_SYSINFO
AMD fam10 raminit cannot be built without RAMINIT_SYSINFO, this
is not a true option but copy-paste remainder from AMD K8.

Change-Id: Id8edc112f3bacebd1732304ac9ee6e77cc6263b7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4581
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-29 19:45:41 +01:00
Kyösti Mälkki 1709453bad via/epia-m700: Drop RAMINIT_SYSINFO
Option is for AMD K8 only.

Change-Id: Ic55288b3cae2c9bf4f347037e7bf5d9bfcf16689
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4580
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-29 19:45:29 +01:00
Kyösti Mälkki 2e77461051 AMD K8: Socket implies K8_REV_F_SUPPORT
K8_REV_F_SUPPORT is already set by all affected sockets, (AM2, F, S1G1).

Change-Id: If42a4178263d90a4e195fae0c78943ac9eda1ad6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4557
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-29 00:04:02 +01:00
Paul Menzel 475e1b9095 via: Write »access« without »m« at end
The comment was copied around so fix all occurrences using the following
command.

	$ git grep -l accessm | xargs sed -i 's/accessm/access/g'

Change-Id: I46e117c126c0f851cd5e95cf9e42a77ca5f80996
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/4577
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-27 19:49:46 +01:00
Kyösti Mälkki ba6c2663ed AMD AGESA: Drop MEM_TRAIN_SEQ
This config was for AMD K8 only.

Change-Id: Ic1ce60041fef6ddee2dae0e3559fb78f088740af
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4556
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-26 23:24:06 +01:00
Kyösti Mälkki 6c57f64e58 AMD fam10: Drop MEM_TRAIN_SEQ
This config was for AMD K8 only.

Change-Id: I76276405b676d1dd4d5dbf8c5b94194a670ccb25
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4555
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-26 23:23:30 +01:00
Kyösti Mälkki 142b52cd32 AMD boards (non-AGESA): Cleanup post_cache_as_ram.c includes
Change-Id: Ib3a69e3364418426438f88ba14e5cf744e2414fa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4524
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-26 23:22:17 +01:00
Kyösti Mälkki 88a67f0cc9 AMD boards (non-AGESA): Cleanup earlymtrr.c includes
Change-Id: I5f4bf9dbaf3470dc83d3e980bb6cab10801e15c1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4523
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-12-26 23:19:11 +01:00
Kyösti Mälkki 1c434ff2d6 vortex86ex: Cleanup earlymtrr.c include
No MTRRs on this platform.

Change-Id: Iaef57c8013ae9d40f3b063aae284b3faeeaa43dd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4572
Tested-by: build bot (Jenkins)
Reviewed-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-12-26 23:18:28 +01:00
Vladimir Serbinenko b32816e9a5 Remove PCI_ROM_RUN option
The main purpose of option rom is to supply int* handlers.
But supplying those is outside of coreboot scope and if someone needs those
they should run SeaBIOS anyway which runs the option roms wonderfully.

Running VGA oprom is kept because they're needed to init graphics.

This patch still keeps the options to include the option roms to make them
available to SeaBIOS.

Change-Id: I646334cf88094d3bf8f527779a68a07e0b4b93ec
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4545
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Kevin O'Connor <kevin@koconnor.net>
2013-12-24 14:40:49 +01:00
Kyösti Mälkki 50ecb9c111 usbdebug: Add option to disable console for romstage
If there is trouble setting up usbdebug, it may be useful to delay
usbdebug init to run in ramstage.

Change-Id: I31de5a06d3f9ce19f71c422cce0c8cb0fd50f396
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4488
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-12-23 10:35:39 +01:00
Idwer Vollering d26da9c8f0 Coding style: punctuation cleanup [1/2].
Clean up superfluous line terminators.

Change-Id: If837b4f1b3e7702cbb09ba12f53ed788a8f31386
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/4562
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2013-12-23 02:12:51 +01:00
Alexandru Gagniuc c6c8cb7f79 Fix linking microcode with more than one microcode file
When assembling microcode , the rule to link individual object files into
one larger file only passed the first dependency to the linker. As a results
only microcode from one object file would actually get linked. This is fixed
 by replacing $^ with $+ inside the make rule.

Change-Id: I65c0565f2e03777af23e530c08d1241804ca19b1
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4500
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-22 19:26:31 +01:00
Andrew Wu fea5b50feb vortex86ex: Change PCI S/B resource reservation functions for more I/O devices.
Originally, Vortex86EX PCI S/B internal resource reservation functions can
only support one big legacy I/O device space (0-0xfff).

Change function signature to support other non-legacy I/O device space in
the future.

Change-Id: I22f5c877ed441d59f29801d925ee40b24fb796ce
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3976
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-22 14:57:09 +01:00
Duncan Laurie 9d1d740968 lynxpoint: XHCI: Don't put device in D3 in _PS0 Method
The end of the _PS0 method that is supposed to transition the
XHCI device to D0 state is instead putting it in D3 state.

This triggers a PME_B0 GPE which causes a Notify to the XHCI
ACPI Device in the kernel and that increments the wakeup counter
and causes aborted suspends.

Instead if we just leave the device in D0 where it should be
after executing this function then the PME_B0 is not generated
and the kernel does not see a wakeup on XHCI.

Similarly I changed the _PS3 method to always put the device in
D3 at the end of the method, rather than depending on the state
to be D3 at the start.

Before this change the kernel would see the following sequence
when trying to suspend when the XHCI controller is in D3cold:

kernel: ACPI: Execute Method [\_SB_.PCI0.XHCI._PS0] (Node ffff88017802bf28)
kernel:   evmisc-0169 [07] ev_queue_notify_reques: Dispatching Notify on [XHCI] (Device) Value 0x02 (Device Wake) Node ffff88017802bc30
kernel:   evmisc-0169 [07] ev_queue_notify_reques: Dispatching Notify on [EHCI] (Device) Value 0x02 (Device Wake) Node ffff88017802b8e8
kernel:   evmisc-0169 [07] ev_queue_notify_reques: Dispatching Notify on [HDEF] (Device) Value 0x02 (Device Wake) Node ffff88017802b1b8
kernel: xhci_hcd 0000:00:14.0: power state changed by ACPI to D0
kernel: xhci_hcd 0000:00:14.0: PME# disabled
kernel: xhci_hcd 0000:00:14.0: enabling bus mastering
kernel: xhci_hcd 0000:00:14.0: setting latency timer to 64
kernel: PM: Wakeup pending, aborting suspend
kernel: last active wakeup source: 0000:00:14.0

Now it does not get a notification (due to PME_B0) when going to D0
on the way into suspend.  XHCI goes from D3cold to D0 (in order to
be able to read mmio) and then back to D3hot before suspend.

kernel: ACPI: Execute Method [\_SB_.PCI0.XHCI._PS0] (Node ffff88017802bf28)
kernel: xhci_hcd 0000:00:14.0: power state changed by ACPI to D0
kernel: xhci_hcd 0000:00:14.0: PME# disabled
kernel: xhci_hcd 0000:00:14.0: enabling bus mastering
kernel: xhci_hcd 0000:00:14.0: setting latency timer to 64
kernel: ACPI: Execute Method [\_SB_.PCI0.XHCI._S3D] (Node ffff88017802c000)
kernel: xhci_hcd 0000:00:14.0: PME# enabled
kernel: xhci_hcd 0000:00:14.0: System wakeup enabled by ACPI
kernel: ACPI: Execute Method [\_SB_.PCI0.XHCI._PS3] (Node ffff88017802bf50)
kernel: xhci_hcd 0000:00:14.0: power state changed by ACPI to D3hot

Change-Id: Id5cd28eede2b27d97640047feb17349ae4ab79b7
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65236
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4448
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 23:55:02 +01:00
Duncan Laurie 0bf1dea8d8 lynxpoint: Fix an issue clearing port change status bits
The coreboot and ACPI code that clears USB3 PORTSC change status
bits was not properly preserving the state of the PED (port enabled
or disabled) status bit, and it could write 0 back to this field
which would disable the port.

Additionally add back the code that resets disconnected USB3 ports
on the way into suspend (as stated in the BWG) but take care to
clear the PME status bit so we don't immediately wake.

suspend/resume with USB3 devices

1) suspend with no devices, plug in while suspended, then resume
and verify that the devices are detected
2) suspend with USB3 devices inserted, then suspend and resume
and verify that the devices are detected
3) suspend with USB3 devices inserted, then remove the devices
while suspended, resume and ensure they can be detected again
when inserted after resume

Change-Id: Ic7e8d375dfe645cf0dc1f041c3a3d09d0ead1a51
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65733
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4473
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 23:54:59 +01:00
Duncan Laurie 568ce5ce13 lynxpoint: XHCI: Advertise D3 as lowest wake state
The recommended value in docs is D2, but lynxpoint XHCI does not even
support D2 state which causes the kernel to think this device cannot
be used as a wake source:

kernel: xhci_hcd 0000:00:14.0: System wakeup enabled by ACPI
kernel: ACPI: Device does not support D2
kernel: xhci_hcd 0000:00:14.0: System wakeup disabled by ACPI

Additionally this means the kernel will never put the device into D3
state by itself.  There is SMI code that will put the device into D3
before suspend so advertising D3 here should be correct.

With this change the kernel will put the controller into D3 on suspend
and back to D0 on resume, including executing the ACPI methods
for _PS0/_PS3 that contain chipset specific workarounds.

In addition add a _PSC method to directly return the D state from the
device registers.  With ALL USB devices removed the XHCI controller
goes into D3 state and the kernel can have a hard time determining
the state of the device at boot.

A kernel compiled with CONFIG_ACPI_DEBUG=y and module parameters
acpi.debug_layer=0x7f acpi.debug_level=0x2f can be used to see
what ACPI methods are executed:

kernel: xhci_hcd 0000:00:14.0: System wakeup enabled by ACPI
kernel: ACPI: Execute Method [\_SB_.PCI0.XHCI._PS3] (Node ffff8801000a7f50)
kernel: ACPI: Preparing to enter system sleep state S3
...
kernel: ACPI: Waking up from system sleep state S3
kernel: ACPI: Execute Method [\_SB_.PCI0.XHCI._PS0] (Node ffff8801000a7f28)
kernel: xhci_hcd 0000:00:14.0: power state changed by ACPI to D0

Change-Id: Ic64040eb4dd1947a1e2f0ee253a64be683e0ec70
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>

meld with s3d

Change-Id: Ic6789720c4efe661dcb03a4afce8d88115854472
Reviewed-on: https://gerrit.chromium.org/gerrit/63916
Tested-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4409
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 23:54:55 +01:00
Duncan Laurie 0dcb577652 lynxpoint: Fix issues with XHCI init
- Put the device into D0 and not D3 so memory bar is available
and the subsequent commands actually do something useful
- Remove set of 818Ch[7:0]=FFh (gone in ref code)
- Fix reg 0x40/0x44 mixup

Verify that expected bits are set:
localhost ~ # pci_read32 0 0x14 0 0x10
0xe0500004
localhost ~ # mmio_read32 0xe0508144
0x000003ff
localhost ~ # mmio_read32 0xe050816c
0x000f0038

Change-Id: I388398e8c7d11e538ca18dab55d8bbd9b88f17df
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63801
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4408
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 23:54:51 +01:00
Duncan Laurie 911cedff97 lynxpoint: Route all USB ports to XHCI in finalize step
This commit adds a new Kconfig option for the LynxPoint
southbridge that will have coreboot route all of the USB
ports to the XHCI controller in the finalize step (i.e.
after the bootloader) and disable the EHCI controller(s).

Additionally when doing this the XHCI USB3 ports need
to be put into an expected state on resume in order to make
the kernel state machine happy.

Part of this could also be done in depthcharge but there
are also some resume-time steps required so it makes sense
to keep it all together in coreboot.

This can theoretically save ~100mW at runtime.

Verify that the EHCI controller is not found in Linux and
that booting from USB still works.

Change-Id: I3ddfecc0ab12a4302e6034ea8d13ccd8ea2a655d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63802
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4407
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 23:54:46 +01:00
Duncan Laurie 1f529083fc lynxpoint: Move USB SMI sleep code to separate USB files
Move this to the existing USB source files so they can share some
helper functions and keep the main smihandler code cleaner.

The XHCI sleep prepare code now implements the actual sleep
preparation steps from the ref code instead of the docs.

Change-Id: Ic90adbdaba947a6b53824e548c785b4fb3990ab5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63800
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4406
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 23:54:42 +01:00
David Hendricks c81187f231 pit: disable LCD FETs before doing any graphics init
This ensures that the LCD FETs are off before we do graphics init.

FIXME: The location of the code is sub-optimal and should probably be
done in romstage, but there are __PRE_RAM__ considerations to take
into account.

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: I0844030d0a0e51eee1d29f1762f0b495777268df
Reviewed-on: https://gerrit.chromium.org/gerrit/64305
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-on: http://review.coreboot.org/4470
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:47:01 +01:00
David Hendricks 1ad77de62d exynos5420: Assign corect parent PLLs
Assign correct parent PLL's for the following clocks:
ACLK_400_WCORE (MPLL->CPLL) (400 -> 333MHz)
PCLK_200_FSYS (MPLL->DPLL) (200 -> 200MHz)
MUX_ACLK_100_NOC_SEL (MPLL -> DPLL) (100 -> 100MHz)
ACLK_266 (DPLL->MPLL) (300 -> 266MHz)
ACLK_200_DISP1(MPLL->DPLL) (200 -> 200MHz)
ACLK_400_MSCL(MPLL->CPLL) (400 -> 333MHz)
ACLK_66 (MPLL->CPLL) (66.666 -> 66.6MHz)
MUX_ACLK_400_DISP1_SEL (CPLL->DPLL) (666 -> 300MHz)
MUX_MPHY_REFCLK (MPLL->OSC)
MUX_UNIPRO (MPLL->OSC)
MUX_MIPI1 (EPLL->OSC)
MUX_DP1_EXT_VID (EPLL->OSC)
MUX_FIMD1_OPT (EPLL->OSC)
MUX_IPLL(IPLL->OSC)
This also corrects the clock dividers for few of the clocks,
as the clock parent changes affect the final frequency of the
clocks.

This is ported from: https://gerrit.chromium.org/gerrit/#/c/62437/

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: Ie833c01913d0961a6190446bd573511de8dee5f8
Reviewed-on: https://gerrit.chromium.org/gerrit/65620
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-on: http://review.coreboot.org/4469
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:46:56 +01:00
David Hendricks 7f35bbb0d4 exynos5420: don't assume MPLL for i2c parent clock
This reads the clock select field for MUX_ACLK_66_SEL in the
CLK_SRC_TOP1 register in order to obtain the source clock rate
for I2C peripherals. Before we were always assuming that the source
was the MPLL.

Unfortunately not all fields in the CLK_SRC_TOPn registers are
enumerated the same with regard to clock select. So this is just
a one-off for now.

This is basically ported from https://gerrit.chromium.org/gerrit/#/c/62443.

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: I9fa85194ae1a1fadab79695f059efdc2e2f1f75f
Reviewed-on: https://gerrit.chromium.org/gerrit/65611
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4468
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:46:52 +01:00
David Hendricks b783d4585f exynos5420: Set SPLL to 400MHz
Increase SPLL to 400MHz from 300MHz as we set SPLL as the
switching parent for ARM and KFC. This value is as per
recommendation of the hardware team.

This is ported from https://gerrit.chromium.org/gerrit/62618

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: I8a5a5b957083b0b1f3e3e318fe5753cf7ae19223
Reviewed-on: https://gerrit.chromium.org/gerrit/65432
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4464
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:46:43 +01:00
David Hendricks 401da25827 exynos5420: re-factor clock_get_periph_rate()
This re-factors clock_get_periph_rate() to be a simpler and also
make a few corrections along the way. To summarize:

- clk_bit_info is no longer used. It had numerous errors and was
  really painful anyway since it was just a bunch of opaque magic
  numbers that made bugs non-obvious.

- Clock source bitfields for peripherals handled in the switch
  statement are 3 bits, not 4. Some divider values are 3 bits,
  some are 4. The earlier code always assumed 4 bits for both
  which included reserved bits in many cases.

- UART source clock and divider shift values were wrong.

- PWM clock divider was being read from the wrong register.

- SPI3 divider value was being read from the wrong register.

- There was a really confusing calculation for SDMMC0 and SDMMC2
  clock rates, but it was never actually used since the switch
  statement never handled PERIPH_ID_SDMMC{0,2} and would thus
  return if they were ever passed into this function.

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: I0a03a64d8b42fbe83dbf377292597ce681b22f4b
Reviewed-on: https://gerrit.chromium.org/gerrit/65284
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4463
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:46:38 +01:00
David Hendricks efd4b9e936 exynos5420: add a peripheral clock select --> PLL decoder
This adds a helper function to translate between peripheral clock
select fields in clock source registers and PLLs. Some of this was
already done to handle a few special cases, this generalizes the
earlier work so that follow-up patches can do further clean-up.

Unfortunately, the PLLs represented by clock select fields in
various modules are not uniformly ordered. So for now we focus on
peripheral clock sources only.

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: Id58a3e488650d09e6a35c22d5394fcbf0ee9ddff
Reviewed-on: https://gerrit.chromium.org/gerrit/65283
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4462
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:46:33 +01:00
David Hendricks 5f6ffbab1b exynos5420: add CPLL and DPLL to the known list of PLLs
This patch adds CPLL and DPLL to the known list of PLLs.

This is ported from https://gerrit.chromium.org/gerrit/#/c/62617/

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: I2f2614e44cd9c98d98b8db9347f29de21703d1af
Reviewed-on: https://gerrit.chromium.org/gerrit/65282
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4461
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:46:28 +01:00
David Hendricks bd56bf0dcf exynos5420: correct the PMS value for CPLL
This patch matches the User Manual Table 7-2 about the PMS value for
CPLL. This doesn't change the PLL frequency (before and after both make
666MHz) but this is the suggested PMSK values for obtaining 666.
(Suggested as per user manual).

This is ported from https://gerrit.chromium.org/gerrit/#/c/62438/

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: Ia33e1971ab88da761000d443792560476514626b
Reviewed-on: https://gerrit.chromium.org/gerrit/65281
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4460
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:46:24 +01:00
Gabe Black 136e709015 exynos5420: Configure the UART pins unconditionally
Configure the pins for the UART unconditionally in the mainboard code (when we
know which UART to configure) instead of in the UART driver. This also means
the UART will work if later software wants to use it without setting up the
pins.

Built and booted on pit with the serial turned off and some serial init
in the kernel decompression stub fixed.

Change-Id: Icab5755e4f935f52d44b9cb3b43d1cb62acce08f
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/65299
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4457
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:46:20 +01:00
Julius Werner ce011ec131 exynos5250: Implement support to boot with USB A-A firmware upload
This patch implements the basic infrastructure required to use the USB
A-A firmware upload feature on Exynos5 processors with Coreboot. It will
require a corresponding host-side script that activates the feature and
uploads the correct image parts in the correct order to harcoded target
addresses, as described in the comments of alternate_cbfs.c.

Also fixes a bug in the Google Snow mainboard where it would not
correctly initialize the pinmux configuration for the SPI flash bus.
During a normal SPI boot the IROM would already do that for you, but
when booting from USB you have to do it yourself.

Change-Id: I40a39f8f5d1d70b58dbf258015c1653a27097d67
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/64875
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4456
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:46:15 +01:00
Hung-Te Lin 20316321fb armv7: Allow accessing ACTLR (Auxiliary Control Register)
The ACTLR provides implementation defined configuration and control options for
the processor.

Change-Id: I74df1ed7887eb3f16a1b8297db998ec2f8b18311
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65107
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4447
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:46:09 +01:00
David Hendricks e0cfad2b56 exynos5420: re-factor the SDMMC GPIO config routines
The existing GPIO config routines for SDMMC0-2 are over-generalized
and somewhat confusing as a result. It would work nicely if all SDMMC
ports were configured in the same fashion, but there are a few
exceptions.

For example, the inner function runs differently if we're using 8 bits
of data instead of 4, so a big chunk is skipped for SDMMC2. SDMMC0
requires SD_0_CDn to be an output rather than alternate function and
must have a value set.

This patch trades some verbosity for simplicy. Now the SDMMC GPIO
configuration a straight-forward sequence of GPIO operations
without any exceptions.

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: If75075b24c6588c4c1b3be3fb9b1aa95e2fac2d1
Reviewed-on: https://gerrit.chromium.org/gerrit/65248
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4446
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:46:05 +01:00
David Hendricks b9f267ce23 exynos5420: configure SD_0_CDn as VDDEN for eMMC
On Exynos5420 the MMC channel 0 is connected to eMMC
Which does not have a card detection pin. Also this pin
is connected as VDDEN to PMIC.

This is ported from https://gerrit.chromium.org/gerrit/#/c/60732/

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: I19048d22b7dd00df1716b6b5b332a7eb70fe0836
Reviewed-on: https://gerrit.chromium.org/gerrit/65247
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4445
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:46:01 +01:00
Hung-Te Lin 93951f4ed8 armv7: Add CPU & MP primitive instructions
To configure multi-processors, we need the intrinsic functions to get core ID,
put core into idle state, and to wake up cores.

Change-Id: I87a62dab6efd6c8bb0c8e46373da7c7eb7b16b35
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65112
Reviewed-on: http://review.coreboot.org/4444
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:45:57 +01:00
David Hendricks 792b621ac0 exynos5420: init APLL at 1800MHz
This initializes the APLL at 1800MHz.

Change-Id: I366bf4e75510847ab93d9c9f214a49c731cca08a
Reviewed-on: https://gerrit.chromium.org/gerrit/64745
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4443
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:45:52 +01:00
David Hendricks f05e871300 exynos5xxx: use oscillator clock when changing ARM frequency
Switch ARM clock source when changing the APLL frequency to avoid
stability issues.

This is ported from https://gerrit.chromium.org/gerrit/#/c/64189/5

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: I923107555e6d3287b3694cbf9e4bb548d3e5f4a8
Reviewed-on: https://gerrit.chromium.org/gerrit/64838
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4442
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:45:48 +01:00
David Hendricks 49c1be95d3 exynos5420: set L2ACTLR parameters for A15 cores
This patch does the following for the A15 cores:
- Disable clean/evict push to external
- Enable hazard detect timout
- Prevent gating the L2 logic clock

This is ported from https://gerrit.chromium.org/gerrit/#/c/60154

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: I7ac9f40acecfa7daee6fb81772676bf5119d0536
Reviewed-on: https://gerrit.chromium.org/gerrit/64862
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4441
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:45:41 +01:00
Gabe Black e6789c139b snow: Set up the i2s0 pins during boot
Change-Id: I6729a139091b40d8fd9ba2aa7a8c4e14216d95c5
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/64879
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4440
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:45:37 +01:00
Gabe Black 4e195afdf7 exynos5250: Add a pinmux function to set up i2s bus 0
This bus is hooked up on snow and, as it's the only bus hooked up on some
other boards, having it available in firmware to test is handy.

Change-Id: Icb48b9af4a67d382bd6fbce1e4c6a320d811d365
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/64877
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4438
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:45:32 +01:00
David Hendricks 36e62c2516 armv7: add wrappers to read/write L2ACTLR
This adds inline wrappers to read the L2 cache auxiliary control
register (L2ACTLR).

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: Iec603d7c738426232f7ce3a4a474d01c85fa3f2f
Reviewed-on: https://gerrit.chromium.org/gerrit/64861
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4437
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:45:28 +01:00
Gabe Black 49832975c3 ARM: Don't inject nobits since we actually want to load these bits
Change-Id: I128e3ecc3773fe7c28616e93ef60b48c5862f302
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/64839
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4436
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:45:24 +01:00
Gabe Black c1471396a4 ARM: Remove (NOLOAD) from the .car section
On ARM, if the .car section is marked as NOLOAD, there's nothing that sets it
to zero. Some code in the cbmem console depends on a global variable being
zero initially, and if that's not true bad things happen.

Change-Id: Ic72a9fb0ee0c5a608190be6f24d0d7de7c34fc1f
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/64769
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4435
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:45:20 +01:00
David Hendricks 56a7cff7f6 exynos5420: minor correction to CPU frequency print
This divides the CPU frequency by 1,000,000 instead of 2^20.

serial console shows "CPU:   S5P5420 @ 800MHz" instead of
claiming 762MHz.

Change-Id: I70cc5b62f689c5553b57c82be61233fb9f733f6e
Reviewed-on: https://gerrit.chromium.org/gerrit/64743
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4434
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:45:15 +01:00
Hung-Te Lin c0491d4fb5 armv7/exynos: Fix and remove memory reset workarounds
The memory corruption problem in Exynos suspend/resume process is caused by two
things together: PHY_RESET and MRS command.

After stop sending MRS on resume, we can now remove the workaround of skipping
PHY_RESET.

Change-Id: I64acc27c1d2bb549ae6ad7d32ecda94b0355972c
Reviewed-on: https://gerrit.chromium.org/gerrit/64736
Tested-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/4433
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:45:11 +01:00
Ronald G. Minnich c0d5eb2a33 Pit: graphics
This includes the new dp code, which is better, and the fimd code,
which is changed and improved. We took the chance to remove un-needed
files, and also to remove some foolish u-boot habits, but not all of
them. That will take time.

With these changes we get graphics.

Since the only mainboards we have with 16 bit graphics are 5:6:5,
adjust edid.c to just use that format. If at some future time we need
4:4:4, which seems unlikely, we'll need to add a function to adjust
the lb_framebuffer. Note that you can't just divine this from the EDID,
as the graphics pipe format need not match the actual final format used.

The EDID reading works. We've been requested to support hard-coded
EDIDs and that will come in the next revision. Currently the hard-coded
EDID is ignored for testing.

Change-Id: Ib4d06dc3388ab90c834f94808a51133e5b515a4d
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/64240
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4432
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:45:06 +01:00
Stefan Reinauer 052bf4ba21 kirby is dead. long live the arm pit.
Remove kirby from our tree. It's dead.

BUG=none
BRANCH=none
TEST=none

Change-Id: I0768a9ea40be5d70d845a46f6e28036a133b7aa6
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/176030
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/4548
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:45:01 +01:00
Ronald G. Minnich 01b438367c Snow: correctly disable trust zone hardware
The kernel assumes that trust zone is disabled.

Change-Id: Ia8d6fa69adcb812a747d8b89eb77e57144423eaa
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/64722
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-on: http://review.coreboot.org/4431
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 21:02:45 +01:00
Ronald G. Minnich b0efbd3910 Pit: correctly initialize trust zone
This ensures that various trust zone things are reset,
which is important because the kernel assumes they are.

Change-Id: Ie02ea89885621f58a3ccc4f1729617208a264153
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/64697
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4430
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 21:02:41 +01:00
Stefan Reinauer fffbda5897 ARMv7: Fix location of CBMEM console in romstage
The CBMEM console pointer in romstage is actually a zero byte array.
This means CBMEM area has to live at the end of the allocations or
else CBMEM console will overwrite whatever comes after it.

Change-Id: Icc59e982b724a2d396370c3a5abd8898e08baf26
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63997
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/4428
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 21:02:38 +01:00
David Hendricks 1f9f04e571 pit: update PMIC write sequence in romstage
This update the PMIC write sequence to be correct for newer board
revisions.

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: I2210b0d1945fb19c96a674c8fad1b0ff5a4a381e
Reviewed-on: https://gerrit.chromium.org/gerrit/64304
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4427
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 21:02:35 +01:00
David Hendricks d598cac656 exynos5420: update set_cpu_id()
The current function seems to be outdated...

Signed-off-by: David Hendricks <dhendrix@chromium.org>

built and booted. Now we see "CPU:   S5P5420 @ 762MHz"
instead of "CPU:   S5PC420 @ 762MHz"

Change-Id: Ieb103a5fa62bda9a6b2cbd9a82fb4f72c5dd6466
Reviewed-on: https://gerrit.chromium.org/gerrit/64302
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4425
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 21:02:31 +01:00
David Hendricks 8ccabb6877 snow: TPS69050 -> TPS65090
This corrects a minor typo used for a part number.

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: I8583cbfc3b4a6c3ad06419f5aab3ba7a8f685575
Reviewed-on: https://gerrit.chromium.org/gerrit/64301
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4424
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 21:02:26 +01:00
Gabe Black aa6061a0d0 kirby: pit: Fix up wakeup_need_reset
In a previous commit the contents of wakeup_need_reset were removed because
the GPIO it referred to wasn't connected to anything on pit. I didn't realize
at that time that that could have been because we hadn't tried getting
suspend/resume working on pit and hadn't updated that file. On snow, the GPIO
is the recovery mode pin. This change updates pit to have the right GPIO,
kirby to read that GPIO, and makes the comments for both pit and kirby more
explicit and spells out the fact that this is the recovery mode GPIO.

Having a check here at all may still be a holdover from snow that isn't
applicable to pit or kirby, but since there is a parallel as far as the
recovery mode GPIO we might as well make them match while waiting for more
information.

Change-Id: Ic1f3f605a0fddf89e8f5668c7a8df30bdfb91d94
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/64164
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4421
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 21:02:23 +01:00
Gabe Black 925ad2efad pit: Get rid of the mostly unnecessary exynos5420.h
Like on kirby, this header had a single constant in it that was actually used.
This change moves that constant inline and gets rid of the header file.

Change-Id: Ibe380396f72fddb121fb6ceb3cee24f1b9a85738
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/64163
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4420
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 21:02:20 +01:00
Gabe Black 88fdd930ac exynos5250: Add mct_start to the timer init blob in timer_monotonic_get
A previous change removed init_timer from timer_monotonic_get because its old
implementation set up the PWM based timer which was going away. It would still
be a good idea to initialize the timer at that point, just not the pwm.

Change-Id: I4816710ec2c9d5ca53b704c6b9397bcfac183fdc
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/64160
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4419
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 21:02:17 +01:00
Gabe Black 61cd11187d kirby: Clean some cruft from mainboard.c
1. Kirby doesn't have a backlight enable GPIO on the AP since that's handled
entirely by the DP-to-LVDS bridge.
2. There is no tps65090 on the other side of the EC who's settings need to be
adjusted. If we need to turn on the LCD or backlight power manually, it will
have to be done in a different way.
3. The PMIC doesn't provide a 32KHz output for the audio codec.

Change-Id: Iadc5f3aec4818805edf3f2517da9e6fee87085dc
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63883
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4413
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 19:58:31 +01:00
Gabe Black 318cb10eb9 kirby: Neutralize wakeup.c and delete the mostly unused exynos5420.h
The function in wakeup.c isn't applicable on kirby. The only constant in
exynos5420.h that was used was the speed of the 4th i2c bus. Instead of having
a whole header file for that one constant used in one place, the constant is
just moved inline along with the comment it had in the header.

Change-Id: I5ad50c5eeaecbbf7865d76afb31a12d36c3371ee
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63882
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4412
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 19:57:48 +01:00
Gabe Black 9245440eaf Add a kirby board which is mostly a copy of pit
Change-Id: Ic78c65486816015f7574a13affc6e54acbbea73e
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63875
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4411
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 19:56:56 +01:00
Gabe Black 74dbfc252f arm: Remove __image_copy_end from the ARM linker script
That symbol isn't used by anything and doesn't appear in other linker scripts.

Change-Id: Iab54ecb3be2e262d7674ef8ee7ed13ea2e5b56f3
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63776
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4399
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 19:56:24 +01:00
Stefan Reinauer 80e6293a89 Exynos 5420: Enable dynamic CBMEM
...  In order to do this, the graphics memory has to move into
the resource allocator and out of CBMEM.

Change-Id: I565c3d6dea747822fbabf6f3845232d4adfbf333
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63657
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4391
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 18:30:54 +01:00
Stefan Reinauer 662874446a Exynos 5250: Enable dynamic CBMEM
...  In order to do this, the graphics memory has to move into
the resource allocator and out of CBMEM.

Change-Id: I7396da4a7068404b0d2e4d308becab4dd6ea59bb
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/59326
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4390
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 18:30:47 +01:00
Patrick Georgi d9a98581ce armv7: Prepare tables code for dynamic CBMEM
The CBMEM API is different for dynamic CBMEM,
so hide the functions that get in the way (but
our compiler complains about)

Change-Id: I7634a202059548e56c74fe3fe6eff57bc60f1a1b
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/4546
Tested-by: build bot (Jenkins)
2013-12-21 18:30:43 +01:00
Ronald G. Minnich 88750cb3b6 google/pit: disable SYSMMU for graphics
It's not needed and it's a potential problem source.

Change-Id: Ic4cafe74e7fc3a9031d852895ad7fd5e5cd64d11
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/62279
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4410
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 18:00:00 +01:00
David Hendricks ea3a463460 max77802: update header
This adds #defines for BUCK2DVS1_1_2625V and BOOSTCTRL_OFF.

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: I363c73ff4a645da53973767fa4bfa2c120394af6
Reviewed-on: https://gerrit.chromium.org/gerrit/64303
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4426
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 13:29:42 +01:00
Furquan Shaikh 997be3d2ee Refactor code containing aux calls
Moved a lot of code from i915io.c to intel_dp.c with specific function calls

Change-Id: Ib2ed52b4f73ee0076e2dd68a26541e5bbe1366bc
Reviewed-on: https://gerrit.chromium.org/gerrit/63950
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/4429
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 13:27:03 +01:00
Furquan Shaikh 771c3aca70 Slippy/Falco: Fill in right values for PHSYNC and PVSYNC in transcoder flags
Depending upon the values decoded from edid, the function decides the appropriate bits to
be set in flags parameter (Important for fastboot to work correctly in kernel)

Change-Id: I3b0f914dc2b0fd887eb6a1f706f87b87c86ff856
Reviewed-on: https://gerrit.chromium.org/gerrit/64265
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/4423
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 13:26:59 +01:00
Furquan Shaikh db3157cfee Add cpu transcoder attribute to intel dp
Also, used this attribute in the calculation of htotal and other registers
Added intel_dp_* functions for m,n registers and dimension register calculations

Change-Id: I99dd7156700d59b0b4c85e34c9aa1c6408c7f31a
Reviewed-on: https://gerrit.chromium.org/gerrit/64001
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/4422
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 13:26:55 +01:00
Furquan Shaikh d0a81f7534 Calculate transcoder flags based on pipe config
Works fine with all three panels with the change of 6 bits per color.

Change-Id: Ia47d152e62d1879150d8cf9a6657b62007ef5c0e
Reviewed-on: https://gerrit.chromium.org/gerrit/63762
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/4402
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 13:26:51 +01:00
Stefan Reinauer 10bd772db8 Enable CAR migration on Exynos 5250 and 5420
Despite calling romstage memory CAR in this case, the variables actually
do live in SRAM on the Exynos CPUs. However, in order to share as much
generic code as possible, we're using the same infrastructure here.

Change-Id: I85173c37099a25f3e55980e88120401826cdf29c
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/62188
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/4394
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 13:00:21 +01:00
Shawn Nematbakhsh c59fda3216 peppy: Set optimal DTLE register values
Empirical testing shows that 0x5 is the optimal setting for DTLE DATA /
EDGE on Peppy.

Change-Id: I273a3a68be97b3eb7c2ee2071e5de1ef7bf7f2d9
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65717
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/4476
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 12:17:54 +01:00
Shawn Nematbakhsh 287522749e lynxpoint: Add configuration option for SATA gen3 DTLE registers
Allow DTLE DATA / EDGE registers to be configured in board-specific
devicetree.

Change-Id: I82307d08c9cf73461db3ac7fb875a4fe70d6f9ea
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65716
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/4475
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 12:03:00 +01:00
Stefan Reinauer 190688c65f haswell: add option to change DqPinsInterleaved
Some mainboards will need to have this set.

Signed-off-by: Stefan Reinauer <reinauer@google.com>

Change-Id: I4732a9af822a60b5050d03d2ac4bb7cbd6c723d0
Reviewed-on: https://gerrit.chromium.org/gerrit/65722
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4474
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 12:02:56 +01:00
Duncan Laurie 8818b9d0d4 wtm2: disable SDcard USB port
This is causing hangs in depthcharge (again?) so for now
turn that port off so the resulting coreboot images are
at least useful.

Change-Id: I32c7774a95b0020b97105e0fa42c21ccb617c718
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65615
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4467
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 12:02:53 +01:00
Duncan Laurie 3106d0ffce haswell: Misc updates from 1.6.1 ref code
These programming sequences were changed in the latest code.

Change-Id: Ia4b763a49542635713d11a9ee81f7e7f200bf841
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65612
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4466
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 12:02:50 +01:00
Duncan Laurie 4fb3a61fc6 slippy/falco/peppy: Fix EC wake events in S5
The SMI handler code was setting S3 wake events when going
into S5 and enabling a key press to wake the system.

Change-Id: I6413ef1341e0149187df9f4f7e0c314d4c9e9c6e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65323
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4459
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 12:02:46 +01:00
Duncan Laurie 727b5455fb Add a specific post code for S3 resume failures
If the firwmare is flashed and the MRC cache is blown away
then it is not possible to resume.

Right now this can be inferred from the event log but it can
be made very clear by adding a unique post code for this event.

1) boot falco
2) flash firmware
3) suspend and then resume
4) check for post code 0xef in log

0 | 2013-08-08 16:27:47 | Log area cleared | 4096
1 | 2013-08-08 16:27:47 | ACPI Enter | S3
2 | 2013-08-08 16:27:55 | System boot | 48
3 | 2013-08-08 16:27:55 | Last post code in previous boot | 0xef | Resume Failure
4 | 2013-08-08 16:27:55 | System Reset
5 | 2013-08-08 16:27:55 | ACPI Wake | S5

Change-Id: I7602d9eef85d3b764781990249ae32b84fe84134
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65259
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4458
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 12:02:43 +01:00
Duncan Laurie 7e1c83e31b Add Kconfig options to override Subsystem Vendor and Device ID
These can typically be set in the devicetree but we need a way to
override those values with a Kconfig setting so as not to expose
the Vendor ID before the product has launched.

Change-Id: Ib382e6d9359d24b128c693a657ffde52604efad3
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65310
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4455
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 12:02:40 +01:00
Duncan Laurie d538e8fb00 falco: Force enable ASPM on PCIe Root Port 1
Boot on falco and look in /sys/firmware/log for
the string "PCIe Root Port 1 ASPM is enabled"

Change-Id: Ie2111e4bb70411aa697dc63c0c11f13fbe66c8d8
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65315
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4454
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 12:02:37 +01:00
Duncan Laurie 249a03b080 lynxpoint: Add devicetree config option to force enable ASPM
The PCIe root port has ASPM settings/workarounds that are only applied
based on the value of an undocumented bit in PCI config register 0x32C.

If that bit is not set for some reason then the settings are not applied.
This devicetree config option will force the ASPM settings for each port
based on the bit map.

Change-Id: I40b08ca9a0ef52742609bac72fb821454a373799
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65314
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4453
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 12:02:34 +01:00
Duncan Laurie 0b3cd36061 lynxpoint: me: Disable some verbose messages
The default ME output is quite verbose and not all that useful
unless you are actively debugging the ME and then you can enable
the CONFIG_DEBUG_INTEL_ME option.

This commit silences the firmware capabilities and the MBP output.

Change-Id: I2b8abcb34ae0d00d9a38d029979e84ee0d0ca287
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65252
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4452
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 12:02:31 +01:00
Duncan Laurie c45dc1c081 falco: Disable unused clocks
CLKOUT for PCIE ports 1-5 and CLKOUT_XDP are not used
and can be disabled.

I couldn't test this directly without a scope so instead I
used a modified commit that also disabled PCIe Port 0 and
saw that that correctly disabled the WLAN port.

Change-Id: I0f996e90f0ae42780de3a0c8dc5db00ec600748b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65251
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4451
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 12:02:28 +01:00
Duncan Laurie 0dc0d1383d lynxpoint: me: Support ICC clock enables message
This message allows unused clocks to be disabled based on a
devicetree setting in each mainboard.

Change-Id: Ib1988cab3748490cf24028752562c64ccbce2054
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65250
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4450
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 12:02:24 +01:00
Duncan Laurie 2017b4a44f lynxpoint: me: Allow for more than MKHI MEI messages
The original ME code was assuming that the only type of messages
it would send were MKHI type and so it had some embedded checks
for that header and that type of message.

In order to support ICC messages this needs to change to handle
different header types, so now the header will be sent first
and then the data will follow, rather than the two both being
sent in the same low-level function.

This change has no real affect on the system, subsequent commit
will add new ICC messages.

Change-Id: I52848581e49b88c0a79e8bb6bda2a179419808a3
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65249
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4449
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 12:02:21 +01:00
Duncan Laurie 5fcfece756 falco: Enable EC controlled throttling
When the EC requests the host to throttle (for charging or thermal
related reasons) the package power consumption will be limited.

Right now this is set at 12W but that is somewhat arbitrary and may
need tuning.

1) define the THRT method in \_TZ scope for EC to call
2) enable SCI events for throttle start and stop
3) define the power limit at 12W and set it in NVS

1) Enable CONFIG_ACPI_DEBUG=y in the kernel

2) Enable the Debug object event in acpi module
acpi.debug_layer=0x7f acpi.debug_level=0x2f

3) Using EC console generate host event for throttle start
> hostevent set 0x20000

4) Check dmesg for throttle start events
ACPI: Execute Method [\_SB_.PCI0.LPCB.EC0_._Q12] (Node ffff8801002c5988)
[ACPI Debug]  String [0x12] "EC: THROTTLE START"
[ACPI Debug]  String [0x10] "Enable PL1 Limit"

5) Using EC console generate host event for throttle stop
> hostevent set 0x40000

6) Check dmesg for throttle stop events
ACPI: Execute Method [\_SB_.PCI0.LPCB.EC0_._Q13] (Node ffff8801002c59b0)
[ACPI Debug]  String [0x11] "EC: THROTTLE STOP"
[ACPI Debug]  String [0x11] "Disable PL1 Limit"

Change-Id: I39b53a5e8abc2892846bcd214a333fe204c6da9b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63989
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4416
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 12:02:18 +01:00
Duncan Laurie d338b46504 chromeec: Add event methods for EC requested throttle
Two new events possible from the EC for starting and stopping throttle.

These are handled in a per-board method that is defined under the
thermal zone.  This is not quite where I wanted it but the scoping
rules in ACPI don't let me have a defined external object in the
same scope.

Change-Id: I766f07b4365b29df3daa8e45e88f7c38c645c287
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63988
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4415
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 12:02:14 +01:00
Duncan Laurie 7ad61f6262 falco: Drive GPIO59/LTE_DISABLE_L low on S3/S5
Try to prevent WWAN from causing spurious wakes.

Change-Id: Ifcc44063de0eb1634cab9dd244737071568e3455
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63987
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4414
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 12:02:10 +01:00
Gabe Black 7b4c4325e9 pit: Add missing elements to the edid data structure
When the edid data structure changed a while ago, it caused hangs on snow
which were fixed by adding those missing members. Unfortunately we didn't
realize that pit needed the same fix.

Change-Id: I81780b8135b99b2e24af723e703b9befff7b5ef0
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63646
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4389
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 10:49:16 +01:00
Aaron Durbin c422002b5f tpm: provide explicit tpm register access
An issue was observed using a specific vendor's TPM in that it
chokes on access to registers that are not explicitly defined in the
PC client specification. The previous driver used generic access
functions for reading and writing registers. However, issues come
to play when reading from the status register. It read it as a 32-bit
value, but that read address 0x1b which is not defined in the spec.

Instead of using generic access functions for the tpm registers
provide explicit ones. To that end provide more high level wrapper
functions to perform the semantic access required.

Change-Id: I781b31723f819e1387d7aa25512c83780ea0877f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63243
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4388
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 10:49:11 +01:00
Gabe Black 980180962a pit: Bump the EC SPI bus speed up to 5 MHz
That speed is used with U-Boot instead of the more conservative 500 KHz.

Change-Id: Ie9d79db3b52b88c1f3bfec1745634ae6bdc9f4ee
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63193
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4386
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 10:49:08 +01:00
Gabe Black e13680bdd0 exynos5420: Fix some clock settings
Some registers and bit fields were wrong, but the difference is mostly
academic since the code that uses them are never called.

Change-Id: I0ce5e1529cdda1a4973765af8c31b79130b1111c
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63189
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4385
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 10:49:04 +01:00
Gabe Black ad88fda1cf exynos5420: Fix the clock divisor mask
The divisor mask had been set to 0xff, but the bitfield is 4 bits wide.

Change-Id: Id8a205c80ca2fb0b6f0d86a0c3be4bba9527c0b5
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63188
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4384
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 10:49:00 +01:00
Gabe Black dd8f60363a arm: Don't use const pointers with the write functions
This functions are by definition changing the data pointed to by their
arguments, so they shouldn't by const.

Change-Id: Id29b3f76526aba463f8bb744f53101327f9c7bde
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63777
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4400
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 10:48:57 +01:00
Gabe Black 713853a9c8 exynos5420: Get rid of the PWM code like on the 5250
The timer code was supposed to be using the mct, and also using the monotonic
timer infrastructure instead of the get_timer function. This change had been
made for the 5250 but not yet for the 5420.

Change-Id: I03a4fbb434f2346761f28fb6bd2218b526f2a4a2
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/64159
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4418
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 10:48:53 +01:00
Gabe Black 9b764a0dcc exynos5250: Get rid of the PWM timer code we shouldn't be using anymore
This code was left over from U-Boot and was superceded by the MCT.

Change-Id: Ia85e3b7281dcdd4740238dddd0dfc6f0ba2c94da
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63778
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4401
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 10:48:49 +01:00
Gabe Black 2c116febab exynos5420: Apply pwm const fix to the 5420 as well
When the const was removed from write function arguments, a related bug in the
5250 code was fixed so that it would still compile. Unfortunately, that same
change needed to be made to the 5420.

Change-Id: If15057c92422de91dc8e35dbd8b5c978bfae122a
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/64154
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4417
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 10:48:46 +01:00
Gabe Black 9a9d7e8ad0 exynos5250: Fix consts in the pwm code
The code generally intended to make the pointer const instead of the thing it
pointed at, but it had const backwards. Sometimes both the pointer and the
data could be const, but sometimes there were writes where only the pointer
should be.

Change-Id: Ifcd5495769b86b47d7b583cce63ed5c2158bec4e
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63775
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4397
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2013-12-21 10:48:40 +01:00
Aaron Durbin 7b6cc0403f falco: add rtd2132 settings to device tree
Now that the rtd2132 device has the full settings the
panel timings need to be implemented. Sadly, the Tx timings
in the rtd2132 aren't 1:1 with the panel's Tx timings. Below
is the table equivalent:

  RTD2132 | Falco Panel
  --------+------------
     T1   |    T2
  --------+------------
     T2   | T8+T10+T12
  --------+------------
     T3   |    T14
  --------+------------
     T4   |    T15
  --------+------------
     T5   | T9+T11+T13
  --------+------------
     T6   |    T3
  --------+------------
     T7   |    T4
  --------+------------

Change-Id: I10a3ad475d6b9485a707eb49e31afd197fc8d24d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65858
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4472
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 08:56:04 +01:00
Aaron Durbin ebad176554 rtd2132: implement full configuration
It has been disseminated that the RTD2132 chip
needs to be fully programmed for settings to take affect.
Most of the settings are note documented very well and
present themselves as magic values. Also, the wait time
for starting the sequence needs to be bumped from 2ms to 60ms.
Lastly, expose all the known settings through devicetree.

Change-Id: I9eeea9c4a13ec20b8ce1c5297e43c4dd793d90e5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65857
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4471
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 08:55:54 +01:00
Martin Roth 08637d3c9e Remove PS/2 keyboard initialization on resume from S3
When we go through the resume path, there shouldn't ever be a need to
initialize the PS/2 keyboard.  The OS is going to reinitialize it
anyway, and it just slows the resume.

Verified Code flow in normal boot/S3 resume with print statements.
Verified Keyboard was correctly disabled and flushed by booting
to recovery mode screen while pressing keys on the integrated
keyboard.

Change-Id: I48bdca2fa2cc0c965401d10fef75cadb09d2e1e9
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63648
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4396
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 08:30:07 +01:00
Stefan Reinauer 2f38b07570 Add simple hexdump function
- prints hex and ascii
 - detects duplicate all zero lines

Change-Id: I557fed34f0f50ae256a019cf893004a0d6cbff7c
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/62655
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/4392
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 08:25:44 +01:00
Ronald G. Minnich 0d0b6e20f5 Pit: set PWM to external on Parade
The PWM is controlled externally from the APU.

Change-Id: Ia5130d7616991a78dfde44043a60a32cee4f145c
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/61513
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-on: http://review.coreboot.org/4363
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 08:07:01 +01:00
Ronald G. Minnich c0872f26d7 Pit: move parade writes to mainboard.c
What gets written into the parade is highly mainboard-dependent.
So the parade_writes array needs to be there.

Change-Id: Ia382d9bf1929e67b7c14d7a09f5461b71866a16b
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/61486
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-on: http://review.coreboot.org/4362
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 08:06:52 +01:00
Shawn Nematbakhsh 3f17915361 peppy: Drive WLAN_DISABLE_L / BT_ON low in S3 and S5.
When the board is in S3 and S5 the WLAN_DISABLE_L signal
can leak power into the WLAN power well since the GPIO
controlling WLAN_DISABLE_L is in the suspend well. Therefore,
drive WLAN_DISABLE_L low to avoid the power leak.

This is a clone of a Falco change:
I1a0df80dd47fdbd535aca7a9d49253794c480606.

Change-Id: I625dfbb228d1f293b880a52dfe552842d55a17d1
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63220
Reviewed-by: Dave Parker <dparker@chromium.org>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/4383
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 08:04:21 +01:00
Furquan Shaikh aa04ed6494 Added structure members x_mm and y_mm to edid decoding
Change-Id: I9a628cec4da127a3f072d9611259dad99dfa9d29
Reviewed-on: https://gerrit.chromium.org/gerrit/63125
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/4382
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 08:04:13 +01:00
Furquan Shaikh 6b19071ffb FUI: Fill in link_m and link_n values
... based on the EDID detailed timing values for
pixel_clock and link_clock.

Two undocumented registers 0x6f040 and 0x6f044 correspond to link_m and link_n
respectively.  Other two undocumented registers 0x6f030 and 0x6f034 correspond
to data_m and data_n respectively.

Calculations are based on the intel_link_compute_m_n from linux kernel.

Currently, the value for 0x6f030 does not come up right with our calculations.
Hence, set to hard-coded value.

Change-Id: I40ff411729d0a61759164c3c1098504973f9cf5e
Reviewed-on: https://gerrit.chromium.org/gerrit/62915
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/4381
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 08:04:10 +01:00
Ronald G. Minnich 3d9b5a2931 Slippy: remove unneeded code in i915io.c
This code is left over from what the VBIOS did; It is redundant.

Change-Id: I321c867c81ec8b4d5e10f8b51b872cecb3082d97
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/62290
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/4380
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 08:03:58 +01:00
Duncan Laurie f47c4bcd01 slippy/falco/peppy: Route USB to XHCI on resume
Turn on the pei_data flag that will instruct the reference code
binary to route all USB ports to the XHCI controller on resume and
disable the EHCI controller(s).

Change-Id: I2f2ed853a6d17f90ea524bc516f3e78079222739
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63798
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4404
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 07:39:40 +01:00
Duncan Laurie 289bac6a04 haswell: Add pei_data field for USB routing
The linux kernel will unconditionally route all USB
ports to the XCHI controller at boot.  The EHCI controller
can then be disabled, and it should be left disabled
by the reference code when this is done.

However not all OS may do this unconditional route,
so provide an option to the reference code binary to
enable this behavior.

Change-Id: Iedf5af54182bf109cd1119c1999e46300665d41e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63797
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4403
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 07:39:33 +01:00
Duncan Laurie d3c5e50506 haswell boards: fix SATA interrupt in ACPI
SATA is routed to PIRQG which should be interrupt 22
and not interrupt 21.  The kernel uses MSI with this
device so this is only seen when booting with pci=nomsi

Change-Id: Ic90ca2c561fc4c53ec1d395c05872222c65ff98a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63796
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4398
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 07:39:27 +01:00
Duncan Laurie 68a8431fcf haswell: Update microcode revision
CPUID 306C3 Haswell MOB C-0 microcode to 12h
CPUID 40651 Haswell ULT C-0 microcode to 15h

localhost ~ # grep microcode /proc/cpuinfo
microcode       : 0x15
microcode       : 0x15

Change-Id: Ibdfe2b8ef0969b1ccc6dd1642a9fc352b5d11f27
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63045
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4378
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 07:39:04 +01:00
Duncan Laurie 8d716b98d0 slippy/falco/peppy: update ACPI C-state settings
Since these boards do not support C10 we should not bother
advertising that state in the ACPI _CST.

Instead use this map:

ACPI(C1) = MWAIT(C1E)
ACPI(C2) = MWAIT(C3)
ACPI(C3) = MWAIT(C7S)

Change-Id: I37eb02bf9555c74e957316a1ba9778eb2b6ee128
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/62898
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/4377
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 07:39:00 +01:00
Duncan Laurie 8056dc6574 lynxpoint: Avoid any ME device communication in S3 path
The management engine is occasionally hanging the system on resume
when it is accessed.  Since we actually don't need to do anything
with it on resume it can be disabled early in the resume path and
avoid assigning resources just to remove them later.

suspend/resume on falco and check /sys/firmware/log
to ensure that device 00:16.0 is disabled early and that no
resources are probed or assigned and that the device init path
does not execute.

Change-Id: I35573681e3a1d43d816d24954842cbe9c61f3484
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/62897
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4376
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 07:38:54 +01:00
Duncan Laurie 3d299c4b09 lynxpoint me: add support for mbp clear wait in finalize step
The management engine is slow, requiring at least 500ms between
when the Dram Init Done message is sent (right after memory training)
to when the MBP will report that it is successfully cleared and
that the ME can finally be sent the EOP message.

Currently this is adding 100-150ms to the boot time.  If we defer
waiting for the MBP Clear indicator until the finalize step we
can gain back that lost time.

boot on falco with SMI debugging enabled to
ensure that the ME is locked down in the finalize step:

Finalizing Coreboot
SMI# #0
SMI_STS: PM1 APM
ME: MBP cleared
ME: mkhi_end_of_post
ME: END OF POST message successful (0)

Change-Id: Icab4c8c8e00eea67bed5e8154d91a1eb48a492d1
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/62633
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4375
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 07:38:42 +01:00
Duncan Laurie 80fd5c4461 lynxpoint xhci: Add ACPI D0/D3 workarounds
There are specific programming requirements for the usb3 ports
on all LynxPoint chipsets when transitioning to D0 or D3.

LynxPoint-LP has additional workaround steps needed involving
resetting the disconnected ports when transitioning to D0.

The workarounds are implemented in ACPI code so the controller
can transition properly into D3 at runtime.

Change-Id: I3b428562f48c9cb250b97779a3b2753ed4f81509
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/62632
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4374
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 07:38:34 +01:00
Duncan Laurie af98062817 Revert "lynxpoint: Move ME lock down to ramstage"
This reverts commit ff81f50f0e4c068b64c4a5c7f5244196ecd24965.

Deferring this step until the finalize stage will allow us
to defer waiting for the MBP clear indicator and speeding
up the boot.

Change-Id: Ib8edffd06689e72875830cd68b5aedb7ac3b0559
Reviewed-on: https://gerrit.chromium.org/gerrit/62631
Tested-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4373
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 07:38:32 +01:00
Duncan Laurie d8c7d73283 lynxpoint: power management setup tweak
Updated from 161 ref code

Change-Id: I3e07935fec1df21f14d97d165792fe54bf9e474c
Reviewed-on: https://gerrit.chromium.org/gerrit/62128
Tested-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4372
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 07:28:57 +01:00
Ronald G. Minnich 45df5962c7 SLIPPY: final changes for FUI
The intel_ddi.c change I thought should be in but I don't see it. It just adds two functions back
that we need.

There are two new files for slippy annotated with comments about how it needs to evolve.

That said, this code has been tested on 3 different panels. Both dev and non-dev usages work.

physbase initialization to static value removed.

Moved spin calls to intel_dp_*

Change-Id: I0480af45c21c7dedcaff7e8be729f0eb554ec78a
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/61136
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4370
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2013-12-21 07:28:51 +01:00
Shawn Nematbakhsh ebb8a1a819 peppy: Duplicate SPD data for 2GB configurations.
Peppy SPD table has 4GB configurations followed by 2GB configurations.
Current implementation does remapping to point 2GB configuration to the
same SPD index as the 4GB. This is different than Falco, which simply
duplicates the SPD data for all configurations. To simplify probing in
mosys, copy the Falco implementation of duplicating SPD data.

Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>

Change-Id: Idb185a437f3cf4f40d2dae1ae59c30235df8f489
Reviewed-on: https://gerrit.chromium.org/gerrit/61847
Reviewed-by: Dave Parker <dparker@chromium.org>
Reviewed-by: Jay Kim <yongjaek@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4369
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2013-12-21 07:28:45 +01:00
Duncan Laurie 21d4a85042 chromeos: Check for recovery reason code in shared data
When using RW firmware path the proper recovery reason can
be retrieved from the shared data region.  This will result
in the actual reason being logged instead of the default
"recovery button pressed" reason.

1) build and boot on falco
2) crossystem recovery_request=193
3) reboot into recovery mode, check reason with <TAB>
4) reboot back into chromeos
5) check event log entry for previous recovery mode:

25 | 2013-07-15 10:34:23 | Chrome OS Recovery Mode | Test from User Mode

Change-Id: I6f9dfed501f06881e9cf4392724ad28b97521305
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/61906
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4368
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2013-12-21 07:28:37 +01:00
Duncan Laurie 29f7688409 haswell boards: Use PECI temp sensor id 0
The EC temperature sensors were renumbered and now PECI
is at index 0.

1) boot on falco
2) check /sys/class/thermal/thermal_zone0/temp
3) check 'temps' on ec console

Change-Id: Idde1457c42c80850b5b8ac22781060ed9b224d13
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/61896
Reviewed-on: http://review.coreboot.org/4367
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2013-12-21 07:28:30 +01:00
Duncan Laurie a9dc05130e falco: Enable RTD2132 spread spectrum at 1.0%
This may need further tuning but will start at 1.0%.

boot on falco and check /sys/firmware/log

localhost ~ # grep RTD2132 /sys/firmware/log
RTD2132: Enable 1.0% Spread Spectrum
I2C: 01:35 (Realtek RTD2132 LVDS Bridge)

Change-Id: I96e1c14dbc6a7bfaf1c8deb1806c48bf2fd3e32a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/61895
Reviewed-on: http://review.coreboot.org/4366
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2013-12-21 07:28:24 +01:00
Duncan Laurie 0cf0d1499a rtd2132: Add driver for Realtek RTD2132 LVDS bridge
This driver allows the mainboard to enable spread spectrum
clocking at 0.5%, 1.0%, and 1.5% with devicetree settings.

Change-Id: I59c61e67aa8e951fd9904ad951deb6d0ba29669e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/61894
Reviewed-on: http://review.coreboot.org/4365
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2013-12-21 07:28:17 +01:00
Duncan Laurie 8870733b59 lynxpoint: Add LPT-LP device id and smbus_write_byte
This is needed for SMBUS drivers to write to devices.
It was copied from existing intel southbridge driver.

Change-Id: Id0ce2393b2946a9c741413bca563a1a4dc0a4f5e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/61893
Reviewed-on: http://review.coreboot.org/4364
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 07:28:12 +01:00
Aaron Durbin 05d065cff5 bolt: make the gpio interrupts edge sensitive
The drivers in the kernel expect the devices using gpios
to generate interrupts to be edge sensitive. Make it so.

Change-Id: I920ef621682d33ba081f737e97f0239f903db2f7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/61678
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4361
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2013-12-21 07:28:04 +01:00
Hung-Te Lin f584218544 armv7: Remove SYS_TEXT_BASE config.
SYS_TEXT_BASE is not used by any one. To prevent confusion when changing memory
layout, remove it from current configurations.

Change-Id: I15012b864bbb9c12003843b9b24ea64c91f4578b
Reviewed-on: https://gerrit.chromium.org/gerrit/61853
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Tested-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/4371
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-20 21:56:20 +01:00
Vladimir Serbinenko f422a443d7 ec/lenovo/h8: Enable 3G modem
Just like bluetooth and wlan it need to be enabled in EC.
Set the appropriate bit in EC if CMOS config says so.

Change-Id: Ia48ca3201f013d3b4c4153f32ff536e06b6a2f6d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4516
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-19 08:58:16 +01:00
Duncan Laurie 7d14e89c54 lynxpoint: Don't write to non-existent EHCI
The LynxPoint-LP chipset only has one EHCI controller so we should
not attempt to write into the second one that only exists on LynxPoint-H.

Change-Id: I1eae060c7f0a5873c9684e5abfeea5cb5895ab62
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63799
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4405
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-18 02:24:13 +01:00
Alexandru Gagniuc b1ae0303ce cpu/intel: Do not rely on CBFS microcode having a terminator
Up until now, a dummy terminator was required for CBFS microcode files.
This was a coreboot only requirement in order to terminate the loop which
searches for updates.

Figure out where the microcode file ends, and exit the loop if we pass the
end of the CBFS without finding any updates.

Change-Id: Ib61247e83ae6b67b27fcd61bd40241d4cd7bd246
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4505
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-12-17 22:59:19 +01:00
Alexandru Gagniuc 4c37e58ea5 device/dram/ddr3: Move CRC calculation in a separate function
Calculating the CRC of a SPD may be useful by itself, so split that
part of the code in a separate function.

Change-Id: I6c20d3db380551865126fd890e89de6b06359207
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4537
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-17 19:59:22 +01:00
Vladimir Serbinenko d7813436b3 X60/T60: Implement "next display output" button.
Most of the code needed for this is already in the tree with X201
patch series but code didn't know where to send the next screen 
notification and so was disabled. Define right video device.

Tested by: Sam Noble

Change-Id: I4ff0d220afdca342617ce43c6e5d0164ad8eba27
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4494
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2013-12-16 23:59:36 +01:00
Vladimir Serbinenko dd9945bdc7 qemu/videoinit: Set required fields in fake EDID
x_resolution, y_resolution and bytes_per_line were not inited. Without them
coreboot sweared that screen is 1108630x1142817 and payload tried to draw on
such a big screen.

Change-Id: I0d0277a20c7e1976c27af4a57651ab2be0f9c5d7
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4535
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-16 23:57:43 +01:00
Vladimir Serbinenko 9bf05de5ab lenovo/x201: Add support for Lenovo X201 (Calpella-based laptop)
Was extensively tested on my X201.
More info on the wiki

Change-Id: I503d77749780422e446b48224ca98a1f22a2c180
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4514
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-15 17:50:03 +01:00
Vladimir Serbinenko 2c87668914 ec/lenovo/h8: Fix peripheral init without CMOS config
Currently H8 skips important init if unable to access CMOS config.
Change default to enable all features to have a sane system without
using CMOS config.

Change-Id: I4448ccd21beae8ad23eb22391770c6fe3b83e3b4
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4515
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2013-12-15 17:49:23 +01:00
Paul Menzel cc2f3452e4 intel/cougar_canyon2/Kconfig: Remove HAVE_ACPI_RESUME as S3 is unsupported
According to the commit message for the board Cougar Canyon 2 (48a749a8)
resuming from S3 is currently unsupported.

    The FSP does not support S3 at this time. S3 may be added
    when it is available in the FSP.

Mirror that in the configuration by not selecting the Kconfig option
`HAVE_ACPI_RESUME`.

Change-Id: I894f103ffa7d8db6342f99fff0867b02bc750752
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/4519
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-12-15 01:17:52 +01:00
Vladimir Serbinenko ad3bd9d5f2 drivers/pc80: Add ACPI description.
AT controller needs an ACPI node, otherwise FreeBSD doesn't detect keyboard
and mouse. Currently each SuperIO adds its own description. This one should
be used in the future instead.

Change-Id: Iaad5ed3846c6d9f467a02a286a1e6f60a3607af5
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4518
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-14 18:24:53 +01:00
Kyösti Mälkki 75b68d8f5b cpu/amd: Remove error messages on non-matching microcode patches
Microcode update file contains patches for various processor
revisions, it is not an error to have those.

Change-Id: Ifbca26276b66f17092afe249a2cfc229713a9fec
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4520
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-13 09:07:46 +01:00
Alexandru Gagniuc 66e0c4c8c4 cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFS
CPU_MICROCODE_IN_CBFS was designed to mean that loading microcode updates
from a CBFS file is supported, however, the name implies that microcode is
present in CBFS. This has recently caused confusion both with contributions
from Google, as well as SAGE. Rename this option to
SUPPORT_CPU_UCODE_IN_CBFS in order to make it clearer that what is meant is
"hey, the code we have for this CPU supports loading microcode updates from
CBFS", and prevent further confusion.

Change-Id: I394555f690b5ab4cac6fbd3ddbcb740ab1138339
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4482
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
2013-12-13 01:28:36 +01:00
Ronald G. Minnich 4c5b161e3f EDID: add fields specialized to the needs of framebuffers
Now that we have horizontal display areas that are not multiples of 32  bytes,
things are more complex. We add three struct members (x, y resolution and
bytes per line) which are to be filled in by the mainboard as it sets the mode.

In future, the EDID code may take a stab at initializing these but the values are
context-dependent.

Change-Id: Ib9102d6bbf8c66931f5adb1029a04b881a982cfe
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/60514
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-on: http://review.coreboot.org/4336
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12 22:21:22 +01:00
Duncan Laurie 3ece50d9db bolt: Initial mainboard commit
BUG=chrome-os-partner:20448
BRANCH=none
TEST=emerge-bolt chromeos-coreboot-bolt

Change-Id: I634a755ac7659e7a977b51bcc061f69eb8263810
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/59843
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4330
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12 22:12:09 +01:00
Duncan Laurie 0a7c49efa0 HDA: Enable Mini-HDA and fix up PCH-HDA init
The SystemAgent contains a mini-hd audio controller at PCI 0:3.0
which uses the same verb table init sequence as the southbridge.

In order to avoid two copies of the verb table loading code I
separated out the HDA verb table functions into a file that can
be re-used and then added a minihd driver to the haswell northbridge.

The minihd verb table is the same across devices so it can live
within the minihd driver rather than needing to be specified in
each separate mainboard.

I also fixed up the driver for lynxpoint HDA by following the
reference code.

Without HDMI cable plugged in driver does not find any codec,
and it does not seem to re-probe when HDMI is connected.  We may
be missing kernel patches for this.

hda-intel 0000:00:03.0: no codecs found!

With a basic kernel patch to add 0x0a0c device ID to HDA driver
and with HDMI cable connected it is much happier:

snd_hda_intel 0000:00:03.0: irq 60 for MSI/MSI-X
input: HDA Intel MID HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:03.0/sound/card0/input9
snd_hda_intel 0000:00:1b.0: irq 61 for MSI/MSI-X
input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:1b.0/sound/card1/input10
input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card1/input11

Change-Id: Ifa587984be4fc2801704a0368b9cdf8379c2450e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/59336
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4318
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12 22:11:46 +01:00
Duncan Laurie 4e3b345d16 slippy/falco/peppy: make GPIO interrupts be edge triggered
The drivers are designed to work with an edge triggered interrupt.

Change-Id: I35a121ecfb6409bb9049f4d1e034185bb3bb7557
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/61664
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4360
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12 22:07:11 +01:00
Ronald G. Minnich 6da7046f73 EXYNOS5250: be less chatty at critical moments
The 5250 DRAM code is *really* chatty. That's not a great
idea in time critical code, and DRAM init is generally
very sensitive about such things.

Finally, for those things that are errors, print them
at an error level, not a debug level.

Change-Id: Ifa86b019dfd5f8ae6c8a1da2a35b5d0808dc3623
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/60100
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-on: http://review.coreboot.org/4359
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12 22:07:00 +01:00
Aaron Durbin 3641cb1d66 falco: drive WLAN_DISABLE_L low in S3 and S5
When the board is in S3 and S5 the WLAN_DISABLE_L signal
can leak power into the WLAN power well since the GPIO
controlling WLAN_DISABLE_L is in the suspend well. Therefore,
drive WLAN_DISABLE_L low to avoid the power leak.

Change-Id: I1a0df80dd47fdbd535aca7a9d49253794c480606
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/61421
Reviewed-on: http://review.coreboot.org/4358
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-12 22:06:32 +01:00
Hung-Te Lin c5aac958ae exynos5250: Correct DDR3 Phy-reset value names.
The name "LPDDR3PHY_CTRL_PHY_RESET_OFF" is not appropriate because the real
phy-reset is a low-active pin, so "off(0)" will trigger "start to reset".

To prevent confusion, we should rename the constants to "RESET_ENABLE" and
"RESET_DISABLE".

Change-Id: Iccba5ef3a2e992f877dea90741f0308c161758c9
Reviewed-on: https://gerrit.chromium.org/gerrit/61081
Tested-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/4357
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12 22:06:08 +01:00
Duncan Laurie 356833d0b5 haswell: Fix up GPU power management setup
New/more magic values from latest ref code.

Change-Id: Ia2655333b4daca86c2f2a76f5edcd55cdaf3f851
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/61334
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4356
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12 22:06:03 +01:00
Duncan Laurie 118d105a37 haswell: Export functions for CPU family+model and stepping
These are needed to enable workarounds/features on specific
CPU types and stepping.  The older northbridge function and
defines from sandybridge/ivybridge are removed.

Change-Id: I80370f53590a5caa914ec8cf0095c3177a8b5c89
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/61333
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4355
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12 22:05:57 +01:00
Hung-Te Lin f6d6e62aaf exynos5420: Setup clocks for MMC bus controller.
To configure source clocks on Exynos 5420 for MMC drivers.
Some registers are different from the 5250. FSYS now has two parts
and MMC uses FSYS2. The MMC block uses MPLL as the clock source.
The "high-speed" MMC interface runs as 52MHz, so divider is set
accordingly.

Also, the MMC driver has changed from MSHCI (Mobile Storage Host Controller
Interface) to DWMCI (DesignWare MMC Controller Interface).

Change-Id: I9ba9cf43e2f2dcd9da747888c0c7676bd545177b
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/60858
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4354
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12 22:05:52 +01:00
Shawn Nematbakhsh 865912cec0 peppy: Add backward-compatible RAM_ID table.
Make use of google_chromeec_get_board_version to determine board
version, and apply proper RAM_ID table to load correct SPD.

Change-Id: I6a2d54759cf2ce98bf53df0db396c6e09368c714
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/61192
Reviewed-by: Dave Parker <dparker@chromium.org>
Reviewed-on: http://review.coreboot.org/4353
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12 22:05:41 +01:00
Martin Roth aa1b10617d Peppy: Update Realtek ALC283 verb table
Update peppy's verb tables for the Realtek ALC283 Audio Codec.

ALC283 Configuration:
Digital Mic - NID 12h: Disabled
Speakers    - NID 14h: Enabled
Mono out    - NID 17h: Disabled
Mic 1       - NID 18h: Disabled
Mic 2       - NID 19h: Headphone Jack
Line1       - NID 1Ah: Internal Mic
Line2       - NID 1Bh: Disabled
PCBEEP      - NID 1Dh: Enabled
SPDIF       - NID 1Eh: Disabled
HP-OUT      - NID 21h: Headphone Jack

Mic 1 doesn't seem to really be available, but the documentation
refers to NID 18h as MIC1, so it's being disabled as it's not
being used.  The onboard microphone has been moved to line 1.

I had my peppy modified to attach the mic to line1 and mic1 now
works with this patch.  Mic2 looks harder to rework, so I think
that will have to wait for the DVT boards.

Change-Id: I7d6ce6b428806b6aed1d36e7e25302fa5ae14b21
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/58880
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4352
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-12 22:04:11 +01:00
Shawn Nematbakhsh d0a6a38bb7 chromeec: Allow get_board_version to be called from romstage.
We will soon need to call google_chromeec_get_board_version to determine
correct DDR SPD. We must do so before DDR is initialized, so allow this
function to be called from romstage.

Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>

Change-Id: I882d84e38d11bf66067193a6f408f941f2cf8a81
Reviewed-on: https://gerrit.chromium.org/gerrit/61191
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4351
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12 22:04:00 +01:00
Duncan Laurie a367892c98 falco: fix usb port settings
USB2 Port A set to 6.4" and Back Panel
USB2 Port B set to 5.2" and Back Panel
USB2 Port C set to 12.3" and Internal

Other devices all set to Internal.

build and boot on falco and check settings.

Based on the config settings all ports end up with
tuning param 1 == 5 and param 2 == 2

U2ECR[0] = 0x00059501
U2ECR[1] = 0x00059501
U2ECR[2] = 0x00059501
U2ECR[3] = 0x00059501
U2ECR[4] = 0x00059501
U2ECR[5] = 0x00059501
U2ECR[6] = 0x00059501
U2ECR[7] = 0x00059e01

Change-Id: I6b9e6df2679036a501355e6b389a486a6f178f99
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/61297
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4350
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-12 22:03:54 +01:00
Duncan Laurie 7ed3976704 Log device path during resource allocation
Systems are hanging in dev_configure() without a log to
indicate which device is being processed.  Add some logging
points to save the device path before talking to the device
so we can narrow in on which device is the problem.

Change-Id: I3751c19a1ea68cdccbc33e4f6b2eeddd1bd9f2e4
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/61296
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4349
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-12 22:03:42 +01:00
Duncan Laurie 768903eac9 haswell: Update ULT microcode to rev 14h
localhost ~ # grep ^microcode /proc/cpuinfo
microcode       : 0x14
microcode       : 0x14

Change-Id: I839f29cff61abf798a619b30ad945e25c79f548f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/60658
Reviewed-on: http://review.coreboot.org/4348
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12 22:03:35 +01:00
Duncan Laurie 46cbcf6354 falco: Remove thermal thresholds that use CTDP
This CPU does not support Configurable TDP and so far does
not need to use Controllable TDP.

Change-Id: I15599cd4e6890dd5c9d9f99bc4e95307a8dcc827
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/60657
Reviewed-on: http://review.coreboot.org/4347
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12 22:03:29 +01:00
Hung-Te Lin 86148a6219 armv7: Fix dcache_clean_by_mva.
The OP assigned by dcache_clean_by_mva must be handled in dcache_op_mva.

Change-Id: Ia7631a08be6afacb13dfff406ac4db20efc98926
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/61076
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4343
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12 22:03:01 +01:00
Ronald G. Minnich c55131cdbf PIT: remove a comment that is incorrect.
The is_resume comment is wrong for this board. It only applies
to the older 5250 cpu. In fact, the is_resume parameter
is not needed for ddr init and will likely be removed soon.

Change-Id: I4e3c92fcaaa75d3c9223d90acccf053f61406307
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/60103
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-on: http://review.coreboot.org/4342
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12 22:02:57 +01:00
Gabe Black dcaaba44b6 snow: Fix the edid data structure definition so depthcharge works again.
Some new fields were added to the edid data structure, and the edid code was
changed to put estimated values into those fields which were ultimately passed
into depthcharge or other payloads. On snow we do things different and just
declare an edid structure statically which didn't have those members. The rows
and columns of the graphics console were 0, and that confused the framebuffer
driver and made it loop forever.

Change-Id: I6ca3bd948482b347a6a981e83b82b10dca995e5e
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/61057
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4341
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12 22:02:52 +01:00
Shawn Nematbakhsh d6ff9e7deb peppy: RAM_ID + storage changes for next build.
- Update RAM_ID table.
- Add DEVSLP0 signal to NGFF SATA port.

Note: After this change, old Micron 2GB boards will no longer boot.

Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>

Change-Id: Id68a1d6ace2702cca9c37305726cd55a0bde5005
Reviewed-on: https://gerrit.chromium.org/gerrit/60167
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: Dave Parker <dparker@chromium.org>
Commit-Queue: Dave Parker <dparker@chromium.org>
Reviewed-on: http://review.coreboot.org/4340
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12 22:02:42 +01:00
Shawn Nematbakhsh ccb12fbb58 peppy: Disable audio codec enable GPIO in S3 + S5.
To save power, disable audio codec in S3 + S5.

Also, refactor Lynxpoint GPIO code slightly to allow usage in SMM
binary.

Change-Id: I55c4248c89a258b5e4cecf8579eb58f1c15430c0
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/60950
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4339
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12 22:02:35 +01:00
Kyösti Mälkki f0a13ceb63 AMD boards: Fix includes for microcode updates
No ROMCC involved, no need to include .c files in romstage.c.

Change-Id: I8a2aaf84276f2931d0a0557ba29e359fa06e2fba
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4501
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-09 23:28:43 +01:00
Alexandru Gagniuc 299c265102 Refactor usage of walkcbfs to permit access to CBFS headers
walkcbfs() is used only with ROMCC. Besides finding stages during the
bootblock, it's also used when applying microcode updates during the
bootblock phase. The function used to return only a pointer to the data of
the CBFS file, while making the header completely inaccessible. Since the
header contains the length of the CBFS file, the caller did not have a way
to know how long the data was. Then, other conventions had to be used to
determine the EOF, which might present problems if the user replaces the
CBFS file. This is not an issue when jumping to a stage (romstage), but can
present problems when accessing a microcode file which has not been
NULL-terminated.

Refactor walkcbfs_asm to return a pointer to the CBFS file header rather
than the data. Rename walkcbfs() to walkcbfs_head(), and reimplement a new
walkcbfs() based on walkcbfs_head(). Thus current usage of walkcbfs()
remains unaffected.
The code has been verified to run successfully under qemu.

Subsequent patches will change usage of walkcbfs() to walkcbfs_head where
knowing the length of the data is needed.

Change-Id: I21cbf19e130e1480e2749754e5d5130d36036f8e
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4504
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-09 19:56:57 +01:00
Vladimir Serbinenko 2267658db4 snprintf: lockless operation
Instead of having global variables put them on the stack.

Change-Id: I462e3b245612ff2dfb077da1cbcc5ac88f8b8e48
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4288
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-12-07 19:27:53 +01:00
Vladimir Serbinenko f421b33edb vtxprintf: Introduce vtxdprintf for the ease of closures
It was suggested to eliminate the lock for sprintf. One way to do it is
to make the fake tx_byte into a closure. This patch allows it.

It's a bit tricky since we need to preserve compatibility with romcc.

Change-Id: I877ef0cef54dcbb0589fe858c485f76f3dd27ece
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4287
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-12-07 19:27:34 +01:00
Aaron Durbin 16cbf8983c haswell: VR controller configuration
Configure the VR controller. This enables the PSIx levels
as well as C-state ramping. PSIx thresholds are:
 - PSI3: 1A.
 - PSI2: 5A.
 - PSI1: 15A.

Before:
0x601 0x0000000000000100
0x603 0x0036000000262626
0x636 0x000000000000006f
After:
0x601 0x4010140f00000100
0x603 0x0036000000262626
0x636 0x000000000000006f

Change-Id: I6958845ac4164ebd0f1bb2d6d9be55ba63ed9344
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/60931
Reviewed-by: Sameer Nanda <snanda@chromium.org>
Reviewed-on: http://review.coreboot.org/4338
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2013-12-07 03:51:52 +01:00
Ronald G. Minnich 01ab2d14be Add kernel-derived support functions for DDI.
Newer mainboards that use haswell -- and, presumably, chipsets to come -- need
some support functions. Add them in the drivers/intel/gma directory.
Currently, this is one file: intel_ddi.c, but more may come.

Compilation of this file is controlled by INTEL_DDI, defined
in the Kconfig as default n and used in the Makefile.inc

Change-Id: I501ee291c0d4589925ed3e478f67106337fcad31
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/60612
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-on: http://review.coreboot.org/4337
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-07 03:42:55 +01:00
Duncan Laurie b17117904d haswell: Add ACPI support for Controllable TDP
Add ACPI Methods to enable and disable power limiting with PL1.
This can be used in ACPI Thermal Zone or in EC ACPI _QXX events.

This commit adds new unused methods and is fully tested with the
subsequent commit that makes use of these methods.

Change-Id: I9d8d23bfe9cf7c756ff8ab0412e5a010826b12db
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/60546
Reviewed-on: http://review.coreboot.org/4334
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2013-12-07 03:33:10 +01:00
Duncan Laurie c70353f1eb haswell: Misc power management setup and fixes
1) fix enable of power aware interrupt routing
2) set BIOS_RESET_CPL to 3 instead of 1
3) mirror PKG power limit values from MSR to MMIO on all SKUs
4) mirror DDR power limit values from MMIO to MSR
5) remove DMI settings that were from snb/ivb as they do
not apply to haswell

1) verify power aware interrupt routing is working by looking
in /proc/interrupts to see interrupts routed to both cores
instead of always to core0

BEFORE: 58:       4943          0   PCI-MSI-edge      ahci
AFTER:  58:       4766        334   PCI-MSI-edge      ahci

2) read back BIOS_RESET_CPL to verify it is == 3

localhost ~ # iotools mmio_read32 0xfed15da8
0x00000003

3) read PKG power limit from MMIO and verify it is the same
as the MSR value

localhost ~ # rdmsr 0 0x610
0x0000809600dc8078
localhost ~ # iotools mmio_read32 0xfed159a0
0x00dc8078
localhost ~ # iotools mmio_read32 0xfed159a4
0x00008096

4) read DDR power limit from MSR and verify it is the same
as the MMIO value (note this is zero based on current MRC input)

localhost ~ # rdmsr 0 0x618
0x0000000000000000
localhost ~ # iotools mmio_read32 0xfed158e0
0x00000000
localhost ~ # iotools mmio_read32 0xfed158e4
0x00000000

Change-Id: I6cc4c5b2a81304e9deaad8cffcaf604ebad60b29
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/60544
Reviewed-on: http://review.coreboot.org/4333
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2013-12-07 03:31:06 +01:00
Duncan Laurie ddf68901f7 peppy: Enable power limiting for thermal control
Limit power to 12W at 73C and remove limit at 68C.

To have the CPU consume maximum power it is necessary to stress
both the CPU and the GPU.  Bastion (chrome.supergiantgames.com)
and/or webglsamples.googlecode.com can be useful for this.

Testing this properly requires a script to report the running
average power readings.  The watch_power.sh script is attached
to this issue in the partner tracker.

1) Run watch_power.sh continuously:
localhost ~ # watch -n 0 bash -e /tmp/watch_power.sh
2) Start Bastion (or other stress apps).  The power draw should
be close to 15W if under enough load.
3) Watch until temperature climbs above 73C and is caught by
the thermal zone 10 second poll, this can be sped up by blocking
or removing the fan.
4) The ACPI thermal zone states should change to reflect that
active[2] is now enabled and power consumption should drop to 12W.
5) Stop the stress apps and wait until the CPU cools off again,
enable the fan again if it was removed.
6) The ACPI thermal zone state should switch back to active[3].

Change-Id: Ie6714a8543d4f06edf8513086fc9c968273bdb23
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/60545
Reviewed-on: http://review.coreboot.org/4335
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-07 03:28:48 +01:00
Aaron Durbin 10a070b447 elog: handle ROM_SIZE differences from detected flash size
The elog code calculates flash offsets and their equivalent
addresses in the memory address space. However, it assumes
the detected flash size is entirely mapped into the address
space. This can lead to incorrect calculations. Add code
to allow ROM_SIZE to be less than detected flash size. The
underlying assumption is that the first ROM_SIZE bytes are
programmed into the larger device.

Change-Id: Id848f136515289b40594b7d3762e26e3e55da62f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/60501
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4332
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-07 03:27:44 +01:00
Idwer Vollering 8c0cb8ae3b Correct file permissions.
Some files have incorrect/odd permissions,
correct them: remove unnecessary +x flags.

Change-Id: I784e6e599dfee88239f85bb58323aae9e40fb21c
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/4490
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-12-07 00:39:09 +01:00
Idwer Vollering 6e6d719d82 src/vendorcode/amd: remove Visual Studio remnants.
Delete files that (were overlooked and) are probably needed to
build with Visual Studio.
Remove doxygen helper files as well.

Change-Id: I6b6cece178917ad9da1081eb6b1bb9be33066a77
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/4489
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-12-07 00:38:48 +01:00
Alexandru Gagniuc a406119e9b arch/x86: Do not run UPDATE-FIT if we don't include microcode
The original intention was to only run UPDATE_FIT when a microcode file was
included in CBFS. This happens when either CPU_MICROCODE_CBFS_GENERATE or
CPU_MICROCODE_CBFS_EXTERNAL is selected, however, the makefile checked that
CPU_MICROCODE_IN_CBFS was selected instead. The end result was that on
hasswell, the UPDATE-FIT step was always run, even when no microcode was
included, generating a build error.

Instead, introduce a new variable which tells if a microcode update is
added in CBFS during the build.

Change-Id: I28638912ed6f77761ef8a584f7636dc907b7a9b7
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4480
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-12-06 23:39:50 +01:00
Kyösti Mälkki 8232bc2cdd usbdebug: Hide irrelevent options from menuconfig
No need to show the choice of USB port or controller in case of older
hardware where location for usbdebug was hardwired.

Change-Id: Ia186bf2c6ed60be2834cf6fd0a1965c8bf81ed4d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4290
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-06 18:02:31 +01:00
Kyösti Mälkki fab0c9f35d butterfly: Fix build without ChromeOS
Use a file in CBFS for keyboard layout and ethernet MAC instead
of scanning FMAP.

Change-Id: I7658c7c4e389deb20d7d8f57cce8b568efdc575d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4307
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-06 17:50:29 +01:00
Gerd Hoffmann 590e8d4558 qemu: fix GENERATE_ACPI_TABLES=n in fw_cfg.c
Change-Id: Ib8dc069c9e503747c349e96a466feb42279afd08
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/4305
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-06 12:37:01 +01:00
Ronald G. Minnich 4623b20e5a Add in the Makefile bits for the new intel gma driver
The Intel GMA driver is in, this CL splices in the Makefile bits.

Change-Id: Icf42a537575b8cc90a679ec1fc15b09294630611
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/60346
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-on: http://review.coreboot.org/4331
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-06 00:33:58 +01:00
Ronald G. Minnich 99451b174a FUI: add intel_dp driver derived from kernel functions
These functions are not all used yet, but do compile and are partially used
in the FUI testing.

They were extracted from the 3.4 kernel using coccinnelle filters. The .c files
are only compiled in if CONFIG_INTEL_DP is set.

Change-Id: Id95622a75aa02b496c9ea4717cb143394a8332e3
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/60245
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4329
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-05 20:24:03 +01:00
Ronald G. Minnich 5bcca7e982 haswell: pull in the init code for FUI
Removed two unnecessary register sets, and did the power well a bit
more correctly. Also, added a register definition include file so we can
used constants instead of magic numbers.

We also set registers to common initialized values that are
needed for FUI, VBIOS, and kernel. This set of registers
appears to be an absolute bare minimum. Since we're hoping to use
FUI for all chipsets from this one forward, we unconditionally do the
setting here.

Signed-off-by: Ronald G. Minnich <rminnich@google.com>

Change-Id: Ife3f661ba010214d92b646b336f2b06645119f17
Reviewed-on: https://gerrit.chromium.org/gerrit/59988
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-on: http://review.coreboot.org/4328
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-05 20:23:23 +01:00
Ronald G. Minnich 7982de165e google/link: use the new edid functions when in FUI mode
The new edid functions support converting the edid to an lb_framebuffer.
Use them. Also, since panels seem to set bits per color instead of bits
per pixel, just force the right value in the edid struct.

Add helpful comment because people don't always believe we need to set
the pallette.

While we're at it, fix a problem that caused it to not compile.

Change-Id: I645edc4e442d9b96303d9e17f175458dc7ef28b6
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/57619
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-on: http://review.coreboot.org/4327
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-05 20:15:18 +01:00
Duncan Laurie 4bc107bc02 lynxpoint: Update LPT-LP PM settings
- updates from 1.6.0 ref code
- remove the step comments as they are no longer even close
- add constants for LPT revisions

build and boot on Falco

Check that RCBA+2300[1] is set:
> mmio_read32 0xfed1e300
0x00000002

Change-Id: I8b3c5fda3f3170455699a7834239cb991603e7a8
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/59821
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4326
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-05 20:14:56 +01:00