Commit Graph

34409 Commits

Author SHA1 Message Date
Tao Xia e747e8557e mb/google/dedede/var/sasukette: Adding audio codec and
speaker amplifier support into devicetree

Adding audio codec and speaker amplifier support into devicetree

BUG=b:177479444
BRANCH=dedede
TEST=audio function is OK

Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I90ff3a107278c711a085d04ae708e41f95d454ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-02-24 11:29:09 +00:00
Tao Xia b7b41732c9 mb/google/dedede/var/sasukette: Adding Touchpad support into devicetree
Adding Touchpad support into devicetree.

BUG=b:177348842
BRANCH=dedede
TEST=touchpad function is OK

Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I7ecafb5b3e39ff2ed9e176531bd0939f830a6397
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-02-24 11:29:04 +00:00
Tao Xia e64513c767 mb/google/dedede/var/sasukette: Adding camera support in devicetree
and associated GPIO configuration

Adding camera support in devicetree and associated GPIO configuration.

BUG=b:177351873
BRANCH=dedede
TEST=camera function is OK

Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I539e969e180c8c71d4b54b50519d2e1ff25415f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-02-24 11:28:59 +00:00
Aamir Bohra 4742f53770 soc/intel/{adl,jsl,ehl,tgl}: Remove ITSS polarity restore
Post boot SAI PCR access to ITSS polarity regsiter is locked.
Restore of ITSS polarity does not take effect anyways. Hence
removing the related programming.

Change-Id: I1adab45ee903b9d9c1d98a060143445c0cee0968
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-24 11:28:45 +00:00
Stanley Wu a04d37ccb3 mb/google/dedede/var/boten: Configure GPP_G7 as native
Configuring GPP_G7 as NC causes SD card detection issue.
Remove the GPP_G7 override and keep the baseboard
configuration as native function (SDIO_WP).

BUG=b:179733306
BRANCH=firmware-dedede-13606.B
TEST=Built and verified Kingston 64G SD card operation on boten

Change-Id: Ied319437de0e867ee9821d0151ff0c76834c4726
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-02-24 11:28:38 +00:00
Arthur Heymans b238caaaca device/device.c: Rename .disable to .vga_disable
This makes it clear what this function pointer is used for.

Change-Id: I2090e164edee513e05a9409d6c7d18c2cdeb8662
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51009
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24 11:28:16 +00:00
Arthur Heymans 318c3ad674 nb/intel/haswell/pcie.c: remove disable NOP
The .disable function pointer is only referenced inside
set_vga_bridge_bits() and is used to unset VGA decoding on the
internal GFX device.

Change-Id: I0443a45522b2267e8e23b28e4e2033f25a7ccbf0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51008
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24 11:28:06 +00:00
Arthur Heymans 522b39e757 nb/intel/sandybridge/pcie.c: remove disable NOP
The .disable function pointer is only referenced inside
set_vga_bridge_bits() and is used to unset VGA decoding on the
internal GFX device.

Change-Id: I6888b08ac11ba2431601fa179d063cee0bb93370
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51007
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24 11:28:01 +00:00
Tim Wawrzynczak 291b58f06e soc/intel/alderlake: Add soc_get_xhci_usb_info() for elog support
Add MMIO offsets for USB2 and USB3 port status registers, for
both north (TCSS) and south (PCH) XHCI controllers; implement
soc_get_xhci_usb_info() to return the appropriate entries for
elog.

Change-Id: I5ceb73707a0af0542a07027fd5c873a9658b19d6
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-24 11:27:51 +00:00
Rocky Phagura afefa506d6 src/soc/intel/xeon_sp/cpx: Add enable IIO error masks
This adds functionality to mask certain IIO errors on the root complex as recommended by HW vendor.

Tested on DeltaLake mainboard. Boot to OS, verify IIO mask registers are programmed correctly.

Signed-off-by: Rocky Phagura <rphagura@fb.com>
Change-Id: I99f05928930bbf1f617c2d8ce31e8df2a6fd15e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2021-02-24 11:27:10 +00:00
Patrick Rudolph 52ef869b94 mb/prodrive/hermes/mb: Update SoC config in PRE_DEVICE
As one option is consumed by MPinit, update the soc config even earlier.

Tested on Prodrive hermes:
Turbo can be disabled and cores won't exceed their base frequency.

Change-Id: I9f444c3b91d2ee1a613ebac1922f1e6b60363c0b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-24 11:27:03 +00:00
Arthur Heymans e1152c401a mb/lenovo/x220: Increase MMIO space
With an external GPU connected via the expresscard slot this is
required.

Change-Id: I154721ff2c712cfe7eb79b8bf8943182c8c36548
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-24 10:41:51 +00:00
Kyösti Mälkki 813b2f030d mb/amd,google: Rename static functions to mainboard_enable
Let's not have 7 boards of all use a different name for
the .enable_dev function in mainboard chip_operations.

Change-Id: I07f3569e6af85f4f1635595125fe2881ab9ddd43
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-24 10:00:21 +00:00
Kyösti Mälkki 32b99169a5 mb/amd,google/zork: Move init_tables() call
The semantics of pirq_setup() from previous platforms was to
only setup the global pointers for PIC and APIC tables, not
to create or modify the tables themselves.

Change-Id: Iaa7c31eed21432dc2b3fe6b32803bd2658fd5e2d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-24 10:00:02 +00:00
John Zhao 2c7842407a soc/intel/tigerlake: Remove polling for Link Active Status at resume
Tigerlake TBT only has SW CM support. The polling for "LA == 1" is not
applicable for SW CM platform at the resume sequence. This change
removes the pollng for "LA == 1" to improve resume performance.

BUG=b:177519081
TEST=Boot to kernel and validated s0ix on Voxel board.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I886001f71bf893dc7eda98403fa4e1a3de6b958e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-23 22:14:04 +00:00
Kevin Chiu 5b3e995710 mb/google/zork: update USB 3 controller phy Parameter for gumboz
Recommendation from SOC to config IQ=8 for U3 port0,
vboost for all U3 ports for passing ESD pin test.

BUG=b:173476380
BRANCH=zork
TEST=1. emerge-zork coreboot
     2. run U3 SI/ESD pin test => pass

Change-Id: I0e6414f686a995536a0fd8aa0f6f70e5a36718a3
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50992
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-23 15:43:28 +00:00
Kevin Chiu dfd52bd466 mb/google/zork: Adjust Gumboz H1 I2C CLK
Adjust H1 I2C CLK:
404kHz -> 391 kHz

BUG=b:179753353
BRANCH=zork
TEST=1. emerge-zork coreboot chromeos-bootimage
     2. power on proto board successfully
     3. measure i2c freq by scope is close to 400kHz

Change-Id: Iedd47dd6fc4f7ac7f0aac480d63ddbdf85a84ec2
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-02-23 15:42:45 +00:00
Ian Feng 5273322f73 mb/google/dedede: Export EC_IN_RW GPIO to payload
Set up EC_IN_RW GPIO in coreboot.

BUG=b:180686277
TEST=Verified that EC_IN_RW signal is read correctly in depthcharge.

Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: Ic41012d3d4843dcab0f6dd9c28396cb9d5c49f08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-02-23 15:38:48 +00:00
Kyösti Mälkki 85a967f248 AGESA fam16 boards: Drop obsolete picr_data and intr_data
Change-Id: I367f6f17fff3d10be19a83d63e927959068408dd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-23 07:46:25 +00:00
Kyösti Mälkki 10de874e9f sb/amd/common: Drop dummy variable assigment
Change-Id: I9b523bda2332859074d2e12c5cb70df68e18063d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-23 07:46:11 +00:00
Kyösti Mälkki 5e82d443aa sb/intel/lynxpoint: Refactor some GNVS
Change-Id: I9524a44f8f4b8e286229d81d10704438f11c4580
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-23 05:58:18 +00:00
Aamir Bohra 01ae4a7706 intel/fsp2_0: Fix the mp_get_processor_info
FSP expects mp_get_processor_info to give processor specfic apic ID,
core(zero-indexed), package(zero-indexed) and thread(zero-indexed) info.
This function is run from BSP for all logical processor, With current
implementation the location information returned is incorrect per logical
processor. Also the processor id returned does not correspond to the
processor index, rather is returned only for the BSP.

BUG=b:179113790

Change-Id: Ief8677e4830a765af61a0df9621ecaa372730fca
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50880
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-23 03:39:54 +00:00
Aamir Bohra d192590e29 intel/common/block/cpu: Add APIs to get CPU info from lapic ID
Add support to get core, package and thread ID from lapic ID.
Implementation uses CPUID extended topology instruction to derive
bit offsets for core, package and thread info in apic ID.

BUG=b:179113790

Change-Id: If26d34d4250f5a88bdafacdd5d56b8882b69409e
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-02-23 03:39:47 +00:00
Kyösti Mälkki c92c5e5450 nb/intel/ironlake: Drop redundant clear of SLP_TYP
Bits are already cleared in southbridge_detect_s3_resume().

Change-Id: If8bb85abacd59c7968876906e126300c9e4314e2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50975
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-23 02:37:09 +00:00
Kyösti Mälkki 3051a9ecfa nb/intel/x4x: Use a variable for s3resume
This helps towards unified chipset_power_state.

Change-Id: I8f152dc9f1e0f26e4777489913e9fb2c9cd3dac0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-23 02:36:55 +00:00
Kyösti Mälkki b33c6fbfd5 nb/intel/x4x,sandybridge: Move INITRAM timestamps
Let's not have CBMEM hooks in between the different
INITRAM timestamps.

Change-Id: I46db196bcdf60361429b8a81772fa66d252ef1a3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-23 02:36:36 +00:00
Kyösti Mälkki 4ce0a07f06 nb/intel/x4x,sandybridge: Move romstage_handoff_init() call
Change-Id: I6356bb7ea904ca860cbedd46515924505d515791
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-23 02:35:53 +00:00
Kyösti Mälkki b6fc13b3db nb/intel/haswell: Use cbmem_recovery()
For consistency with other nb/intel rename variable from
wake_from_s3 to s3resume.

Change-Id: If94509c4640f34f2783137ae1f94339e6e6cf971
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-23 02:35:34 +00:00
Kyösti Mälkki 74cb3e7869 soc/intel/broadwell: Use cbmem_recovery()
For consistency with other soc/intel add s3resume variable,
this helps towards unified chipset_power_state.

Change-Id: I34a123f9fc13bd86264317c7762bf6e9ffd0f842
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-23 02:35:21 +00:00
Kyösti Mälkki c5c3e3c594 soc/intel/baytrail: Use cbmem_recovery()
For consistency with other soc/intel add s3resume variable,
this helps towards unified chipset_power_state.

Change-Id: Ida04d2292aabb5a366f3400d8596ede0dee64839
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-23 02:35:08 +00:00
Kyösti Mälkki 6ceec167f5 soc/intel/baytrail: Use a variable for s3resume
This helps towards unified chipset_power_state.

Change-Id: I532384ad6c5b2e793ed70f31763f2c8873443816
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-23 02:34:47 +00:00
xuxinxiong cdb5b56303 mb/google/oak: Add new DRAM modules K4E6E304EC-EGCG-4GB
Samsung  K4E6E304EC-EGCG-4GB   # 1011

BUG=b:179455694
BRANCH=oak
TEST=emerge-hana chromeos-ec coreboot chromeos-bootimage depthcharge,
update FW to DUTs,these DUTs can pass stress test under run-in.

Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com>
Change-Id: I02cc34157fd03edb7d715a23ed404abc40ef8ccc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50978
Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-23 02:27:35 +00:00
Felix Held a09559501c drivers/intel/fsp2_0/memory_init: check if UPD struct has expected size
If the UPD size in coreboot sizes mismatches the one from the FSP-M
binary, we're running into trouble. If the expected size is smaller than
the UPD size the FSP provides, call die(), since the target buffer isn't
large enough so only the beginning of the UPD defaults from the FSP will
get copied into the buffer. We ran into the issue in soc/amd/cezanne,
where the UPD struct in coreboot was smaller than the one in the FSP, so
the defaults didn't get completely copied.

TEST=Mandolin still boots.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia7e9f6f20d0091bbb4abfd42abb40b485da2079d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-23 01:32:14 +00:00
Kane Chen ca5ed4879f mb/google/zork/var/shuboz: Adjust GPIO settings
1. GPIO_4 to NC

BUG=b:179333669
BRANCH=zork
TEST=emerge-zork coreboot

Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I4342b2beb7fc755bee47ee4fad0023d7a6592c4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50277
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-23 01:14:58 +00:00
Nick Vaccaro 202b1899dc soc/intel/tigerlake: Enable end of post support in FSP
Send end of post message to CSME in FSP, by selecting EndOfPost
message in PEI phase. In API mode which coreboot currently uses,
sending EndOfPost message in DXE phase is not applicable.

BUG=b:180755397
TEST=Extract and copy MEInfo tool from CSME Fit Kit to voxel, execute
  ./MEInfo | grep "BIOS Boot State"
and confirm response shows BIOS Boot State to be "Post Boot".

Change-Id: I1ad0d7cc06e79b2fe1e53d49c8e838f4d91af736
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51012
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22 23:20:32 +00:00
Ritul Guru 3e945f1a23 mb/amd/bilby: updating EC FW specific options for bilby
EC does not exist in Bilby platform, so removing EC size from board.fmd
and updating bilby fmap size to 0xfef000.
Removing unused EC FW config options MANDOLIN_HAVE_MCHP_FW and
MANDOLIN_MCHP_FW_FILE.

Change-Id: I9ca4e421b0d80d041ed4046fa20cc16e24a776d0
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-22 16:00:41 +00:00
Kyösti Mälkki c79fc4737d mb/emulation: Drop cbmem_recovery(0) call in ramstage
Calling cbmem_recovery(0) late in ramstage would appear
to remove all CBMEM entries created so far.

Change-Id: I2abb079844c4b41be09354d603ad36e4a56ea2e1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50841
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22 07:39:39 +00:00
Angel Pons 70243cd801 Revert "lynxpoint: Fix SerialIO ACPI compile issue with recent IASL"
This reverts commit 1a25c9cdfd.

Reason for revert: No longer necessary.

Change-Id: I8adeeebd6e841ef2c878622559dcd15848969842
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46955
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22 07:37:26 +00:00
Angel Pons cf0cd65038 nb/intel/sandybridge: Remove stale FIXME about ECC support
Change-Id: Id0c45ff1ee4a2dc4c0f9a82f6a311f7acac156fd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-22 07:32:37 +00:00
Tim Wawrzynczak 052e439318 mb/google/brya: Fix chip driver and HID for Cr50 TPM
ChromeOS does not compile in CONFIG_OF, so PRP0001 will not successfully
register the device with its driver. Change to GOOG0005 to match other
ChromeOS devices with I2C-connected Cr50 TPM.

BUG=b:180657076
TEST=abuild

Change-Id: Ic1d4eb5e12ea7f7e693f1ffd3848e59668ac2deb
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50920
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22 07:32:06 +00:00
Raul E Rangel d75ee46d3c soc/amd/picasso/acpi: Change PCI0 BAR window
Picasso currently declares the BAR region between TOM and IO_APIC_ADDR.
This region includes MMCONF. We don't want to map any PCI BARs in this
region. This also matches what intel does.
See soc/intel/braswell/acpi/southcluster.asl for an example.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9474fd6ac75a7245b3c35151c38186e913219bb0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-22 07:29:41 +00:00
Raul E Rangel 0b123dd72e soc/amd/cezanne/acpi: Add pci0.asl
This differs slightly from picasso. The PCI BAR region is between TOM1
and CONFIG_MMCONF_BASE_ADDRESS. This matches what the Intel platforms
are doing. It also matches what linux derives from the e820 tables:

> [mem 0xd0000000-0xf7ffffff] available for PCI devices

Picasso currently declares the region between TOM and IO_APIC_ADDR.
This region includes MMCONF. We don't want to map any PCI BARs in this
region.

TEST=Boot majolica and check logs
pci_bus 0000:00: root bus resource [io  0x0000-0x0cf7 window]
pci_bus 0000:00: root bus resource [io  0x0d00-0xffff window]
pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff]
pci_bus 0000:00: root bus resource [mem 0x000c0000-0x000dffff]
pci_bus 0000:00: root bus resource [mem 0xd0000000-0xf7ffffff]
pci_bus 0000:00: root bus resource [bus 00-3f]

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4ff02012795e2166e3a4197071b1136727089318
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50893
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22 07:29:31 +00:00
Raul E Rangel 58a8ad1661 soc/amd: Move root complex SSDT TOM1/TOM2 generation function
This will also be used for cezanne. Stoney also has a similar function,
but it hard codes the scope path. I didn't have a device setup to test
if switching to this function was a no-op. So I left it.

TOM2 isn't used by any ASL, so we could remove it later.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7c8f476a7735fea61a3244b97988e3ead3b42e79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-22 07:29:19 +00:00
Raul E Rangel bde284b585 soc/amd/cezanne/acpi/soc.asl: Add platform.asl
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I01adba010bfad1bb4fdf20a8d0ab22aeeebeb10a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-22 07:29:09 +00:00
Raul E Rangel 980721b3ed soc/amd/cezanne/acpi: Add MMIO devices
The devices were copied from picasso with the following modifications:
* UART{2,3} were deleted
* I2C{0,1} were added
* eMMC was removed since it hasn't been validated

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iddfb975e9292785d0951dd7bb31c1997d2185abd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-22 07:29:01 +00:00
Mathew King 1156acbb7e mb/google/guybrush: Enable console UART
BUG=b:180530492
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I468d76d0e061431bc819ec12978203614bfe72b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50919
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22 07:28:37 +00:00
Mathew King 86a2324ee0 mb/google/guybrush: Enable guybrush variant
Enable the building of guybrush variants and configure the first variant
also called guybrush.

BUG=b:180419462
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I3bed620378f9152277b4943ead1017f61a21ea82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50845
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22 07:28:26 +00:00
Mathew King 5d47887965 mb/google/guybrush: Enable ACPI tables
BUG=b:180419454
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I1e724e78b5ef378d474063417aa2b7e57a00886f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-02-22 07:28:18 +00:00
Subrata Banik 40f53f4b87 mb/intel/adlrvp: Add support for LP5 SKU with boardid 0x17
Change-Id: I4f17f9d58d2c07264d7d8e83a6fce832c9304c24
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-22 07:26:14 +00:00
Wisley Chen cbcae2744a mb/google/dedede/var/drawcia: Configure IRQ as level triggered for elan_ts
Follow elan's suggestion to configure IRQ as level trigger.

BUG=b:180570924
BRANCH=dedede
TEST=emerge-dedede coreboot

Change-Id: I292670580b4c2c18ed0c20a9fbb4ad4289f4eca6
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-22 07:25:50 +00:00
Angel Pons a3868296ce nb/intel/ironlake: Do not call `collect_system_info` twice
Move wait for TXT and early ME init out of `collect_system_info`, and
then drop the first call to it. Also drop a useless register read.

Tested on out-of-tree HP 630, still boots.

Change-Id: I9b167f44cbd96864bf1e8b616576af19cbbfd90c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49581
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22 07:25:37 +00:00
Angel Pons e9fa37894e soc/intel/xeon_sp: Define all SMI_STS bits
As per document 336067-007US (C620 PCH datasheet), add macros for all
bits in the SMI_STS register. These will be used in common code.

Change-Id: I1cf4b37e2660f55a7bb7a7de977975d85dbb1ffa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50915
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22 07:25:09 +00:00
Angel Pons 12e2e0e609 arch/arm/armv7/thread.c: Remove stale file
This file is never built. Plus, `CONFIG_STACK_BOTTOM` does not exist.

Change-Id: I111b20e3443dca701ee8666d44261a00a161d83f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-02-22 07:24:26 +00:00
Angel Pons 5276c34654 mb/amd/padmelon: Drop unnecessary `PADMELON_SOC_IN_USE` option
The SoC can be selected in the corresponding option choices directly.

Change-Id: I226c500dd7370f4610b0117a9e70d727f1d66951
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-22 07:24:12 +00:00
Angel Pons 3d695d2e6a mb/google/oak: Clean up TPM Kconfig
Rowan was the only Oak variant that used TPM2. However, it was removed
in commit 0aa1f9e905 (google/oak: Delete rowan). Since the other three
variants use TPM1, remove now-unnecessary Kconfig options from Oak.

Change-Id: If19df00463f63f1101475f59b5ecea5a9724a9ab
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-02-22 07:23:58 +00:00
Angel Pons 2a58e187af mb/intel/harcuvar: Drop build guards for ENABLE_FSP_MEMORY_DOWN
Ensure the code gets build-tested for CONFIG_ENABLE_FSP_MEMORY_DOWN=n.

Change-Id: I6213e3e0ea3b2acfc97017739ac069ee3811d742
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-22 07:23:36 +00:00
Angel Pons 77330e5b15 mb/amd/padmelon: Replace `HAVE_S3_SUPPORT` symbol
Replace it with `HAVE_ACPI_RESUME`, which defaults to n for this board.

Change-Id: Ibb07c0d001ded8d7ff991bf63607872bf4b79c8e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-22 07:23:16 +00:00
Francois Toguo 15cbc3b599 soc/intel/tigerlake: Add CrashLog implementation for intel TGL
CrashLog is a diagnostic feature for Intel TGL based platforms.
It is meant to capture the state of the platform before a crash.
The state of relevant registers is preserved across a warm reset.

BUG=None
TEST=CrashLog data generated, extracted, processed, decoded sucessfully on delbin.

Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com>
Change-Id: Ie3763cebcd1178709cc8597710bf062a30901809
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-22 07:22:50 +00:00
Moritz Fischer 619c60f94c soc/rockchip/rk3399/sdram: Remove superfluous parameter
Remove extra parameter in phy_dll_bypass_set, since it does not
depend on the channel at hand.

Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: Iae09a6053daf58bf12604e1903c754dc9f1e986f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-02-22 07:21:48 +00:00
Frank Wu 3dba88401d mb/google/zork/var/vilboz: adjust USB phy settings for all USB ports
Sometimes the USB device will be lost after DUT resume.
Adjust USB phy settings for all USB ports to fix the failed symptom.

BUG=b:174538960
BRANCH=zork
TEST=USB devices stay connected after running suspend test

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I25bca968bb4a740161b36e2082d1e500ae648712
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50020
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22 05:58:24 +00:00
V Sowmya 738aaa24d3 mb/intel/shadowmountain: Add the romstage code
This patch includes the romstage changes for the
shadowmountain board.

BUG=b:175808146
TEST= Build and boot shadowmountain board till early ramstage.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Ifd0bbcea9d4916d82bb1e3c275dd79d97a79727a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49731
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22 05:46:58 +00:00
Kyösti Mälkki 43f6598b27 mb/: Drop the provided name in chip_ops
Little point to replicate a string already provided both
as a global Kconfig and global mainboard_part_number.

Change-Id: I1fd138c711ebbb37c39b2c8f554b1f2e1a364424
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
2021-02-21 22:54:05 +00:00
Kyösti Mälkki bb6bf5a1d8 mb/lippert/frontrunner-af: Split sections from dsdt.asl
Added file acpi/sleep.asl is really a copy from persimmon with debug
statement and some comments removed.

Added file acpi/gpe.asl is slightly modified copy from persimmon with
changes that seem valid, considering the other changes present in ASL
for the board.

Rename existing usb.asl to usb_oc.asl for consistency.

Change-Id: I493ad1c110380378bad80e49cd888f47fbe41a92
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-20 21:41:06 +00:00
Kyösti Mälkki 1943b27ea3 AGESA fam14 boards: Drop _SI scope with _SST in ASL
Change-Id: Ieb2f7a6b2721ddeef6945c3e0a0f4cc5627dd533
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-20 21:40:06 +00:00
Kyösti Mälkki 49bc3b7aee AGESA,binaryPI boards: Drop _SI scope with _SST in ASL
Change-Id: I0fca35753c93ba928a0f67bb68a6cfdc26c0e756
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-20 21:39:24 +00:00
Kyösti Mälkki c0733e1639 ACPI: Use common OperationRegion for PCI_MMCONF
Change-Id: Iadb4c3c77ecda4df8e48415d246e769ede2ce86d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50648
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-20 21:38:54 +00:00
Kyösti Mälkki c92efa3363 AGESA,binaryPI boards: Move common PCBA in ASL
Change-Id: I9d502882c4ddb54af1da42a41591804da2cee0ac
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-20 21:38:11 +00:00
Kyösti Mälkki c308f021d2 AGESA,binaryPI boards: Drop unused variables in ASL
Change-Id: I1d1323ab8bb8565c05fd50697e29c61f9932a2c7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-20 21:37:42 +00:00
Kyösti Mälkki c8d7c4834a AGESA fam14 boards: Move include for usb_oc.asl
Do this for consistency with later platforms.

Change-Id: Ia4903b40a8f617c59868aaa116115fa23603438c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-20 21:37:24 +00:00
Kyösti Mälkki ff9ba54ce1 sb,soc/amd: Drop OSFL method in ASL
Variable OSVR had a static value of 3 and OSFL() did not
actually call _OSI or _OS methods.

The conditional in HDA _INI method of OSVR is dropped and
use of DMA NoSnoop attribute remains disabled to retain
previous behaviour. For soc/amd/picasso a different decision
was made in CB:40782 as HDA _INI method was just dropped and
default configuration enables use of DMA NoSnoop attribute.

Change-Id: I967b7b2afbb43253cccb4b77f6c44db45e2989e4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50592
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-20 21:37:11 +00:00
Kyösti Mälkki b484609a02 sb/amd/cimx/sb800: Drop OSFL method in ASL
Method only set variable OSRV, which nobody evaluates.

Change-Id: Ia21b544eaaa61a8fc634eb568b4c7401a225eb76
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-20 21:33:39 +00:00
Furquan Shaikh ac204ba6b5 soc/amd/stoneyridge: Fix _INI method in SSDT for HDA
CB:40785 ("soc/amd/hda: Move HDA PCI device from DSDT to SSDT") moved
the HDA device in ACPI from DSDT to SSDT. During this, _INI method
generated in SSDT incorrectly inverted the values for NSEN, NSDO and
NSDI. This change fixes the mistake so that the _INI in SSDT matches
the original _INI in DSDT for HDA device.

Change-Id: I294b561a479b77ab8afb5f3e0de367ad24f3a764
Reported-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-20 21:32:17 +00:00
Patrick Rudolph e9b0830422 soc/intel/cannonlake: Add devicetree setting to disable turbo
Introduce a new flag to disable turbo called 'cpu_turbo_disable'.
Keep the default and enable turbo on all platforms.

Change-Id: Ia23ce4d589b5ecc5515474eea52a40788ae3d3b5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-02-20 09:02:00 +00:00
Victor Ding e0c2c06ba1 drivers/generic/bayhub_lv2: remove unnecessary configs
coreboot sets up CLK_PM, ASPM, and L1ss automatically based on related
bits in "Link Capability Register" and "L1 PM Substates Capabilities
Register". coreboot overrides these configs even if the driver sets
them. Therefore, setting up CLK_PM, ASPM, and L1ss in the driver is
redundant and useless.

BUG=b:177955523
BRANCH=zork
TEST="lspci -vvvv" prints are identical with and without this patch;
LV2_LINK_CTRL(0x90) is 0x00110102 with and without this patch.

Signed-off-by: Victor Ding <victording@google.com>
Change-Id: I17c19f4271da426ac2b926b948378dc88131e95a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-20 09:01:10 +00:00
Victor Ding 80b2f23584 drivers/generic/bayhub_lv2: move the driver to ".enable"
coreboot sets up certain configs (e.g. L1ss) based on the device's
reported capacities; however, this BayHub lv2 driver modifies some
of its capacities after coreboot uses them. Therefore, coreboot may
make incorrect configs based on out-of-date capacities.

This patch moves the driver from ".init" to ".enable" so that the
capacities are set before the rest of coreboot queries them.

BUG=b:177955523
BRANCH=zork
TEST="lspci -vvvv" reported "PCI-PM_L1.2-" and "ASPM_L1.2-" on L1SubCtl1
of both PCI device "00:01.3" and "02.00.0"

Signed-off-by: Victor Ding <victording@google.com>
Change-Id: I857b7c7c6732bbd26de561052affa3a3e7e25737
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-20 09:00:27 +00:00
Moritz Fischer d4f81bc21d soc/rockchip/rk3399/sdram: Use rank_mask in WDQL training
Add rank_mask based on the rank number and iterate based on that rather
than iterating all values.

Note: LPDDR4 uses a different rank mask.

Ported from u-boot.

Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: I1bff9d20d3d66984c49073aa21212708039d578f
Signed-off-by: Moritz Fischer <moritzf@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-20 00:55:00 +00:00
Moritz Fischer 145ecc6761 soc/rockchip/rk3399/sdram: Use rank_mask in CA training
Add rank_mask based on the rank number and iterate based on that rather
than iterating all values.

Note: LPDDR4 uses a different rank mask.

Ported from u-boot.

Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: I85f449af9f946ad677808800cdbe59e2001202c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50887
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-20 00:54:19 +00:00
Felix Held f1eaa67221 soc/amd/common/block/data_fabric: add warning about broadcast reads
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If1b65ae3dd2b5c8fe7bc29a267d108e4d3a3e567
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50883
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19 23:13:56 +00:00
Felix Held 746f438ada soc/amd: move SMM finalization to common code
This adds the SMM finalization to Cezanne.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1a2b433d92df2a76979e2e6a3d1dde996303ba78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50801
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19 22:11:30 +00:00
Felix Held 7aacdd1d35 soc/amd/cezanne: add MP init and SMM initialization
Change-Id: I38d52394b5f6ffb837fa753fc9e82c0450c6aae3
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50505
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19 22:11:14 +00:00
Moritz Fischer f6e3254a9b soc/rockchip/rk3399/clock: Add rkclk_ddr_reset() function
This adds the rkclk_ddr_reset() function equivalent for the RK3399.

Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: If1da85064d75bdf49b7555d09257409443c25e8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50889
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19 19:09:02 +00:00
Moritz Fischer c73102d0f5 soc/rockchip/rk3399/sdram: Add phy_ctrl_reset
Add support for resetting PHY PCTRL for both channel 0 and 1.

On the ROCKPro64 board this allows getting past a pctl_cfg() failure.

Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: I9f807e318ffc63c568d04518c3edd02c1064e185
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50890
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19 19:08:29 +00:00
Moritz Fischer d8f352b4fd soc/rockchip/rk3399/sdram: Clear PI_175 IRQs in data training
Clear PI_175 interrupts before attempting training in all relevant
calls.

Ported from u-boot.

Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: Ib73f58265db62494282dbec42ec4bf2950617e12
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50886
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19 19:06:35 +00:00
Angel Pons d8fcd42089 mb/hp/280_g2: Add new mainboard
This is a µATX mainboard with a LGA1151 socket and two DDR4 DIMM slots.

There are two possible BOM configurations: Sid has no legacy devices,
whereas Manny provides two serial ports, a parallel port, a PCI slot
and PS/2 keyboard/mouse connectors. These boards also have different
Super I/O models: Manny uses an ITE IT8625E, whereas legacy-free Sid
comes with an ITE IT8656E instead.

This coreboot port has been done using a Sid board, thus support for
Manny-specific features is missing. Booting should still be possible,
though: none of these legacy features is essential.

The board has an unpopulated 6-pin header, wired to PCH UART 2. This
can be used to retrieve coreboot logs.

Working:
- Both DIMM slots (Micron CT4G4DFS8213.8FA11, Hynix HMA851U6AFR6N-UH)
- PCH SerialIO UART 2 to get coreboot logs
- Rear USB ports
- Realtek RTL8111 GbE NIC
- Integrated graphics on DVI with libgfxinit
- At least one SATA port
- Flashing internally with flashrom
- S3 suspend/resume
- VBT
- SeaBIOS 1.14 to boot Arch Linux (kernel linux-5.10.15.arch1-1)

Untested:
- Audio
- VGA: DP2VGA chip uses DDI E, and libgfxinit doesn't support DDI E yet
- Front USB headers
- Non-Linux OSes
- PCI slot
- IT8625E peripherals: serial, parallel and PS/2 ports

Change-Id: Iadf11c187307a24b15039a5a716737d9d74944e6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48386
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19 14:27:19 +00:00
Mathew King 44948a7c5c mb/google/guybrush: Enable CONFIG_CHROMEOS
BUG=b:175143925
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I8d038126b3e511bd16df2144652992c2d5b56c87
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50507
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19 13:34:31 +00:00
Felix Held e09294f57a include/cpu/amd/msr: rename MSR_PSP_ADDR to PSP_ADDR_MSR
The new name is more consistent with the rest of the MSR definitions.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5666d9837c61881639b5f292553a728e49c5ceb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50855
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19 13:20:16 +00:00
Felix Held 285dd6ec3a soc/amd/common/amdblocks/psp: move MSR_PSP_ADDR to include/cpu/amd/msr.h
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5bd6f74bc0fbe461fa01d3baa63612eaec77b97a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50854
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19 13:19:24 +00:00
Julius Werner 82d16b150c memlayout: Store region sizes as separate symbols
This patch changes the memlayout macro infrastructure so that the size
of a region "xxx" (i.e. the distance between the symbols _xxx and _exxx)
is stored in a separate _xxx_size symbol. This has the advantage that
region sizes can be used inside static initializers, and also saves an
extra subtraction at runtime. Since linker symbols can only be treated
as addresses (not as raw integers) by C, retain the REGION_SIZE()
accessor macro to hide the necessary typecast.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ifd89708ca9bd3937d0db7308959231106a6aa373
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-02-19 08:39:26 +00:00
Mathew King 422501fb14 mb/google/mancomb: Add new mainboard
Mancomb is a new Google mainboard with an AMD Cezanne SOC.

BUG=b:175143925
TEST=builds

Change-Id: I1264f44a0b986f7f7c89ac7b42f1e4e4119a35e6
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50007
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19 08:38:58 +00:00
Patrick Rudolph e75f1807e1 mb/prodrive/hermes/eeprom: Add function to read HSI from EEPROM
Will be used to determine the board revision.

Change-Id: I41e4c6ad83e23c9d79e6abab3f38ad46bd3bec06
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50788
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19 08:37:59 +00:00
Patrick Rudolph b67f385b69 mb/prodrive/eeprom: Add BMC settings
Add settings describing the BMC.
Will be used by the following patch to read the board revision.

Change-Id: If464138fc1bdf02a45a21f638b179048d68d974d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50787
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19 08:37:49 +00:00
Tim Wawrzynczak 2091965973 mb/google/brya: Enable MLB USB Type-A Port
The USB Type-A port on the MLB was added to the schematic at the last
minute and it was missed when adding brya0's overridetree. Also fix
a few USB ACPI entries.

BUG=b:180403898
TEST=`lsusb` shows plugged-in flash drive

Change-Id: I8bf96a8b365cb4ea2fc07d7cf673b08e8872ff88
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-18 23:58:22 +00:00
Angel Pons 887cf3017a soc/intel/common: Drop unused `fast_spi_flash_read_wpsr` function
Also remove one macro that was only used inside that function.

Change-Id: Id798e08375c5757aa99288ca4a7df923309f4d67
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-18 23:57:54 +00:00
Angel Pons 5207243270 soc/intel/common/block/fast_spi: Define __SIMPLE_DEVICE__
Change-Id: Iff6111ab379229daec7a3892c330de6b5f0e5157
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-18 23:21:04 +00:00
Karthikeyan Ramasubramanian a7e6788ea7 drivers/i2c/hid: Enforce level triggered IRQ mode
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
This change ensures that the IRQ is appropriately configured.

References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx

BUG=b:172846122
TEST=./util/abuild/abuild. Build and boot to OS in Dedede.

Change-Id: I3245a9de6e88cd83528823251083e62288192f0d
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-18 22:48:27 +00:00
Subrata Banik 02bec2bd5c lib: Add DDR5 DRAM type
TEST=Not seeing default msg "Defaulting to using DDR4 params." with
this CL.

Change-Id: Ib751396ec74b1491fd08b88b07462b315c4a152d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50745
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18 22:47:59 +00:00
Moritz Fischer c867cd3675 soc/rockchip/rk3399/sdram: Move WDQL training into a separate function
Move WDQL training into its own function to enable better error handling.

Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: I8544d6956ca1ce655093a549e7d2928ac9b279bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50865
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18 21:28:53 +00:00
Moritz Fischer 401c7a648a soc/rockchip/rk3399/sdram: Move RL training into a separate function
Move RL training into its own function to enable better error handling.

Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: I02ffbd9deb3fff3bfd8d6e28d6e6d84a4b8c39ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50864
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18 21:27:30 +00:00
Moritz Fischer 12d360012c soc/rockchip/rk3399/sdram: Move RG training into a separate function
Move RG training into its own function to enable better error handling.

Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: I12f17123bc963ffa2dec1559343a141406a5e98d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50863
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18 21:26:43 +00:00
Moritz Fischer 68365e10e3 soc/rockchip/rk3399/sdram: Move WL training into a separate function
Move WL training into its own function to enable better error handling.

Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: I7917846c51982a2473f11d14c51c270e59e59d74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50862
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18 21:26:13 +00:00
Moritz Fischer f71902da5f soc/rockchip/rk3399/sdram: Move CA training into a separate function
Move CA training into its own function to enable better error handling.

Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: Iefaec3121afbb3b29858e03f903d2ffc5ac75da0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50861
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18 21:24:46 +00:00
Moritz Fischer a76f659840 soc/rockchip/rk3399/sdram: Order and group tsel variables
Order and group tsel variables in a meaningful way.

No functional changes.

Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: I417e0fbc129c2d9ad1b345bcff2e25ca6eca83bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50866
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18 21:23:49 +00:00
Moritz Fischer 6410a0002f soc/rockchip/rk3399/sdram: Shorten sdram_params to params
This shortens the use of sdram_params variable names to params.

No functional changes.

Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: I122035078ce37fe65b16bb1f3a2b2d58956431aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50860
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18 16:19:16 +00:00
Moritz Fischer f34bdf8c5e mainboard/pine64/rockpro64: Add initial ROCKPro64 support
This adds initial support for the Pine64 ROCKPro64 board.

The ROCKPro64 (http://pine64.org/rockpro64) is a SBC using the
RK3399 SoC with up to 4GB LPDDR4.

So far only the bootblock part works, the romstage starts to execute,
though.

For ramstage to work we'll need to port some of the changes required
for LPDDR4 vs LPDDR3. This will be addressed in follow up changes.

UART2 on the PI-2 connector can be used as a coreboot console.

  GND is pin 6
  TXD is pin 8
  RXD is pin 10

Flashing:
  I used an OpenWRT nightly for the ROCKPro64 and its builtin tool.

  $ mtd write coreboot.rom /dev/mtd0

Recovering from a bad flash:
  To recover from a bad flash bridging pins 23 and 25 on the PI-2
  connector will make the board boot from SD card.

Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: I47d0031fff8ee10b11ad74935eaeb05f1f7eb4b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50625
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18 16:18:18 +00:00
Felix Held b2d633db07 soc/amd/common/block/data_fabric: fix data_fabric_write32 broadcast case
Calling data_fabric_write32 with BROADCAST_FABRIC_ID as instance_id
would have caused an infinite recursion, so call the right function
data_fabric_broadcast_write32 for that case instead.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If7f0a80f0430e8bfb29ee510ef86c278e3a42063
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-18 11:41:15 +00:00
Angel Pons ff254ea60b nb/intel/pineview: Drop unused `GPIO32` macro
It's not used, and GPIO registers are on the southbridge.

Change-Id: I0b7b6edc22d461007f24618eca42091439a53d3c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45423
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18 10:14:56 +00:00
Angel Pons 0a20872de0 nb/intel/sandybridge: Use 133 MHz ref clock for DDR3-2400
The 100 MHz reference clock seems to be unstable when using high
multipliers. Use the 133 MHz reference clock instead.

Change-Id: I400e4f91776306d54d818fa249d7a845020ac37b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45503
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18 10:12:43 +00:00
Angel Pons fe276fb250 nb/intel/sandybridge: Clean up `dram_freq` function
The thing that this function initializes is the MPLL (Memory PLL). So,
call it by its name. Also add a missing newline in a printk, and update
a comment on the callsite of this function.

Tested on Asus P8Z77-V LX2, still boots.

Change-Id: I86ab643bc87253554346dfed3630eb9ddbd44eb3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-18 10:12:18 +00:00
Arthur Heymans 1999bc5d00 soc/intel/skylake: Move soc_fsp_load
Move this function into the compilation unit where it is called.

Change-Id: Ia4bdcd545827c2564430521a98246fc96bf0ba92
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50796
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18 10:11:55 +00:00
Angel Pons c027ece821 southbridge: Ensure common Kconfig gets included last
Change-Id: Icaa64e664499090fec3e98687b4827ef27cc201b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-18 10:11:39 +00:00
Patrick Rudolph 442bde7b62 src/cpu: Remove unused symbols
Remove the unused Kconfig symbol CPU_MICROCODE_MULTIPLE_FILES.

Change-Id: I18115e07694658a2f77c447d3ab5c899c1bdcc61
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-18 10:11:24 +00:00
Angel Pons 959a448806 sb/intel/ibexpeak: Drop obsolete SATA register settings
Code was copy-pasted from older chips and has no effect on ibexpeak.

Change-Id: I3c5b2b8e4aa6211975c3e3dc1d64432886ef9352
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47864
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18 10:11:08 +00:00
Angel Pons 805ff571e3 nb/intel/haswell: Drop incorrect MMIO_PAVP_MSG write
This write was copied from Sandy Bridge. Neither Haswell reference code
nor Broadwell perform this write. Therefore, it seems safe to remove it.

Change-Id: I8869ff3e66362d9910235c554c3a07e91f479a82
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46994
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18 10:10:54 +00:00
Angel Pons 2fa838dbab mb/google/brya: Remove `Some generic macros` comment
This comment is useless, and was dropped from the tree in the past.

Change-Id: Ie46bf13ec27ff9cd9423795fc170cc7526e18122
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49124
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18 10:10:28 +00:00
Angel Pons 9b629ad37f sb/intel/lynxpoint: Correct read width in RMW cycle
The register is 32 bits wide, so do not read 16 bits out of it.
LynxPoint PCH reference code version 1.9.1 always uses 32-bit accesses.

Change-Id: I18fbba0603579417e09ae4eb4eb273f7fcd903fc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47098
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18 10:10:13 +00:00
Julius Werner ea9c96aa9c commonlib/bsd: Fix direct inclusion of <endian.h>
<endian.h> should never be included directly in commonlib files and
should instead be chain-included via <commonlib/bsd/sysincludes.h>.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ibc67ea97da36ec58738236ef22f961d9bbaf8574
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-02-18 02:33:04 +00:00
Julius Werner 10ee7fc03a cbfs: Fix attribute tag printing in cbfs_find_attr()
Attribute tags are defined as hexadecimal constants, not decimal, so it
makes more sense to print them like that in error messages as well.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I3a5a6a8c9b8d24e57633595fc47221a483d8593a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-02-18 02:32:56 +00:00
Julius Werner 5779ca718c cbfstool: Replace FILENAME_ALIGN 16 with ATTRIBUTE_ALIGN 4
cbfstool has always had a CBFS_FILENAME_ALIGN that forces the filename
field to be aligned upwards to the next 16-byte boundary. This was
presumably done to align the file contents (which used to come
immediately after the filename field).

However, this hasn't really worked right ever since we introduced CBFS
attributes. Attributes come between the filename and the contents, so
what this code currently does is fill up the filename field with extra
NUL-bytes to the boundary, and then just put the attributes behind it
with whatever size they may be. The file contents don't end up with any
alignment guarantee and the filename field is just wasting space.

This patch removes the old FILENAME_ALIGN, and instead adds a new
alignment of 4 for the attributes. 4 seems like a reasonable alignment
to enforce since all existing attributes (with the exception of weird
edge cases with the padding attribute) already use sizes divisible by 4
anyway, and the common attribute header fields have a natural alignment
of 4. This means file contents will also have a minimum alignment
guarantee of 4 -- files requiring a larger guarantee can still be added
with the --alignment flag as usual.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I43f3906977094df87fdc283221d8971a6df01b53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-02-18 02:32:45 +00:00
Julius Werner 84446e6e54 rmodtool: Make memlayout symbols absolute and do not relocate them
Memlayout is a mechanism to define memory areas outside the normal
program segment constructed by the linker. Therefore, it generally
doesn't make sense to relocate memlayout symbols when the program is
relocated. They tend to refer to things that are always in one specific
spot, independent of where the program is loaded.

This hasn't really hurt us in the past because the use case we have for
rmodules (ramstage on x86) just happens to not really need to refer to
any memlayout-defined areas at the moment. But that use case may come up
in the future so it's still worth fixing.

This patch declares all memlayout-defined symbols as ABSOLUTE() in the
linker, which is then reflected in the symbol table of the generated
ELF. We can then use that distinction to have rmodtool skip them when
generating the relocation table for an rmodule. (Also rearrange rmodtool
a little to make the primary string table more easily accessible to the
rest of the code, so we can refer to symbol names in debug output.)

A similar problem can come up with userspace unit tests, but we cannot
modify the userspace relocation toolchain (and for unfortunate
historical reasons, it tries to relocate even absolute symbols). We'll
just disable PIC and make those binaries fully static to avoid that
issue.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ic51d9add3dc463495282b365c1b6d4a9bf11dbf2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-02-18 02:32:06 +00:00
Felix Held a2642d0ffe Revert "soc/amd: Add option to select if SOC supports ESPI sub decode"
This reverts commit 64d0ad347b. In the
current revision 3.001 of the PPR #56569 the register exists and the bit
definitions match.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie7a97843c3dac897f79f229b660b7e30b34eef93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-18 01:17:19 +00:00
Felix Held b284013065 soc/amd/cezanne/root_complex: provide ACPI name in PCI device_operations
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7f17348b1146a07fcb3e905122d7185b60da962f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-18 01:16:04 +00:00
Felix Held 51c4d68fa7 soc/amd/cezanne/chip: add soc_acpi_name
We were missing this, so we ran into the scope assert in
acpi_device_write_pci_dev for the data fabric PCI devices.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I566791527ba839ba52ec5fa28f0f6c25f547d1da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50815
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18 01:15:55 +00:00
Felix Held 74ace5cd3a soc/amd/picasso/chip: remove unneeded functionality in soc_acpi_name
Now that all ACPI names are moved to the corresponding PCI devices, the
functionality in the chip code isn't needed any more.

TEST=No warnings or errors on coreboot console or in the Linux ACPI
parser.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2d39b6d4bd53cd0ca189fb6f55ca26dab68793fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50822
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18 01:15:32 +00:00
Felix Held 8aa9edfa4e soc/amd/common/block/iommu: move ACPI name to common code
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0f1dce92475ce0ee05a8d090fc3b3d1e613f62c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50821
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18 01:15:25 +00:00
Felix Held ff092d4167 soc/amd/picasso/root_complex: provide ACPI name in PCI device_operations
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5471f7be41683ef4a14107f38e93339080d01bdd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50820
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18 01:15:15 +00:00
Felix Held 66b4f0181c soc/amd/common/block/smbus: move ACPI name to common code
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I47415be02571240d3cecfdb91cb9f8097c5b7fde
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50819
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18 01:15:04 +00:00
Felix Held 3e29ca93fc soc/amd/common/block/lpc: move ACPI name to common code
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7517d81d41422cfa10fabd12ab3da4f61c3f9034
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50818
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18 01:14:33 +00:00
Felix Held 61e60d1c16 soc/amd/picasso/chip: make soc_acpi_name static
This function isn't used outside of the same compilation unit.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I332046341bc7a5a499355f2147296e8c09d7e0ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50817
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18 01:14:26 +00:00
Kyösti Mälkki 9e74c42b1f vc/google/chromeos: Account for GNVS allocated early
We have adjusted allocation order such that GNVS is available
before ME hash needs to be stored.

Change-Id: I8428dd85f44935938a118a682767f2f8d6d539ab
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-17 22:58:32 +00:00
Kyösti Mälkki fca1797757 vc/google/chromeos: Allocate RAMOOPS late
The allocation is for the OS. Just need to take care
in the firmware that ChromeOS GNVS is allocated first.

Change-Id: I16db41b31751d7b4a8a70e638602f3f537fe392e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50609
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-17 22:58:10 +00:00
Tim Wawrzynczak 4988900789 soc/intel/alderlake: Fix PCI IRQ tables
Both the IO-APIC and PIC mode PCI IRQ tables are incorrect for ADL; the
2nd field in each package is supposed to be pin, not function number,
and some of the IRQ #s differ from what the FSP programs, therefore
align the ACPI table to match what the FSP is currently programming.

BUG=b:180105941
TEST=boot brya, no more `GSI INT` or `failed to derive IRQ routing`
errors seen in dmesg

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I182be69e8d9ebd854ed74dbb69f4d1f1a539cf2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-17 22:28:13 +00:00
Ritul Guru 286c2f6d4a mainboard/amd/bilby: Add Bilby CRB board
Bilby is the reference board for AMD Raven, Raven2 and Picasso APUs.
Bilby mainboard code is taken from mandolin variant Cereme.
These new files are a renamed copy and subsequent patches will be
applied to create a working bilby implementation.

Change-Id: I426966d782e259a971ec36bac2498bc62b4ce7e2
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-17 20:00:41 +00:00
Raul E Rangel 65819cd364 soc/amd/cezanne: Add FCH IO-APIC to MADT
TEST=Boot majolica to linux and see IO-APIC logs
ACPI: Local APIC address 0xfee00000
ACPI: LAPIC_NMI (acpi_id[0xff] high edge lint[0x1])
IOAPIC[0]: apic_id 16, version 33, address 0xfec00000, GSI 0-23
ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 low level)
ACPI: IRQ0 used by override.
ACPI: IRQ9 used by override.
Using ACPI (MADT) for SMP configuration information

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib8094c3edf401659d9d740e2cc6266ddd5f91da9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-17 19:19:35 +00:00
Felix Held 0810538b63 soc/amd/cezanne/pcie_gpp: add pci_driver for external root ports
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic63ca41ae484cc34c560cf78de37dc1cde32f364
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50805
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-17 18:52:16 +00:00
Felix Held abeececf18 soc/amd/cezanne/pcie_gpp: replace PCI ID list with single PCI ID
Since all bridges to the internal buses have the same PCI ID, we can
just add this one ID to the pci_driver struct and don't need to use a
list of PCI IDs.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ice024b91f49f03995acbd8dfc8b33d3ae3559dde
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50804
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-17 18:52:06 +00:00
Martin Roth 062c4a17a9 vc/intel/fsp: Change line endings to unix
These files have windows line endings.  Change to unix to match the
rest of the tree.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I5bb3338745a6a47b6714aa268d16866aada27790
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-17 17:30:40 +00:00
Martin Roth 5c7341331d treewide: Remove trailing whitespace
Remove trailing whitespace in files that aren't typically checked.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I8dfffbdeaadfa694fef0404719643803df601065
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-17 17:30:05 +00:00
Nikolai Vyssotski 175e4c59a0 drivers/intel/fsp2_0: Allow larger FSPS UPD than expected in coreboot
Enforcing the exact match of FSPS UPD block size between FSP and
coreboot mandates simultaneous updates to coreboot and FSP repos. Allow
coreboot to proceed if its UPD structure is smaller than FSP one. This
usually indicates that FSPS has an updated (larger) UPD structure which
should be soon matched/updated on the coreboot side to keep them in
sync.

While this is an undesirable situation that should be corrected
ASAP, it is safe from coreboot perspective. It is safe (as long as
default values in FSP UPD are sane enough to boot) because FSPS UPD
buffer is allocated on the heap with the size specified in FSPS
(larger) and filled with FSPS default values. This allows FSP UPD
changes to be submitted first followed by changes in coreboot repo.

Note that this only applies to the case when entire FSPS UPD structure
grows which should be rare as FSP should allocate enough reserve space,
anticipating future expansion, to keep the structure from growing when
new members are added.

BUG=b:171234996
BRANCH=Zork
TEST=build Trembyle

Change-Id: I557fd3a1f208b5b444ccf76e1552e74ecf4decad
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-02-17 17:15:07 +00:00
Felix Held 7a92e3895f soc/amd/picasso/agesa_acpi: add cast before right shift
Without the cast the left shift is done on a 32 bit variable that gets
extended to 64 bits afterwards which results in missing MSBs. To avoid
this, do the cast to 64 bits before the left shift.

Found-by: Coverity CID 1443793, 1443794
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7cfa5b9b6ad71f36445ae2fa35140a8713288267
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-17 15:45:57 +00:00
Patrick Rudolph 35f0a8fec7 mb/prodrive/hermes: Write board layout
The I2C EEPROM on SMBUS needs to be updated with the current board
layout, so that the BMC knows the actual configuration.

Collect all needed information and update the EEPROM if something
changed. Every byte written add a delay of 5 msec.

Change-Id: Ic8485e6c700eede75b1e829238ee70da65118ace
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-17 13:38:03 +00:00
Patrick Georgi 71555955e9 mb: guard irq_tables for clang-format
Some (notably older Intel) boards use a tabular description of irq
routing that we want to keep pristine no matter what clang-format
considers correct (as that's ugly).

Change-Id: I259255a9f60208c659b658ecb81535e84a2aaa8c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-02-17 11:34:27 +00:00
Arthur Heymans 2cba9e44b6 soc/intel/xeon_sp/smmrelocate: Don't run twice on the BSP
This only makes sense if relocation via MSR is possible, to relocate
APs in parallel. xeon_sp hardware does not support these MSR.

TESTED: ocp/deltalake boots fine. SMM is relocated on CPU 0 just like
all other cores.

Change-Id: Ic45e6985093b8c9a1cee13c87bc0f09c77aaa0d2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-17 10:36:27 +00:00
Matt DeVillier 1174dad2e2 mb/purism/librem_mini: Enable DRAM Refresh2X
Enable Refresh2X to mitigate RAM corruption during long
(> 1hr) periods of S3/suspend, which leads to failure to
successfully resume from S3. Unknown if an issue with all
DRAM types, but tested w/Kingston KVR24S17D8 16GiB DDR4 SODIMMs.

Test: Build/boot Librem Mini v1/v2, put device in suspend,
wait > 1hr, ensure resume from S3 successful 100% of the time.

Change-Id: Ie8e3ebbb1ebdcd98813b5f36f580a235712d2f97
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50756
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-17 10:35:48 +00:00
Felix Held 63d2008308 soc/amd/cezanne/uart: write ACPI tables
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0faa94fb20daa50c69f25eae3e99e4519323bf5b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-17 10:35:26 +00:00
Felix Held b1b0294e6f soc/amd/picasso/uart: move uart_inject_ssdt to common code
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic033fc2817d44ff873f93a45e069c0e8aa0be99f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-17 10:35:22 +00:00
Angel Pons 0bc878db19 soc/intel/common/block/memory: Always write `data->spd_len`
The `data->spd_len` option always needs to be initialised. However, it
did not get set when using a mixed memory topology. Correct this bug.

Fixes: commit 859ca18ced
Change-Id: I8a165f000e5d52e49de18d7648d02fe76d2dd296
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50786
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-17 07:45:51 +00:00
Subrata Banik d93a5bc115 mb/intel/adlrvp: Fix incorrect SPD address issue on DDR4/DDR5
Assign 7-bit address of the targeted slave SPD.

TEST=Able to read correct SPD data from SMBUS.

Change-Id: If24e61b583638be7c055541c6eb126da28b542f6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50748
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-17 06:04:11 +00:00
Subrata Banik a7adf77afe soc/intel/common/block/smbus: Remove unused macro
TEST=Able to build and boot ADLRVP.

Change-Id: Ic92271700185977f0be83cbc1d3adde37d5b6253
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-17 06:03:44 +00:00
Subrata Banik 486eabce80 mb/intel/adlrvp: Early program SMBUS CLOCK and DATA
TEST=Ensure SMBUS CLK/DATA GPIO is in NF1.

Change-Id: Id615462cc21fc24e7ec6ef16274d784d41bd9bd4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-17 06:03:28 +00:00
Felix Held 547e58db8b soc/amd/*/iomap: remove unused ACPI_SMI_CTL_PORT
This was replaced by APM_CNT defined in src/include/cpu/x86/smm.h, so
remove the now unused definitions.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibd25dcdb57de14fe42352f01067cedca53712d56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-02-17 00:28:57 +00:00
Felix Held e18a97813b soc/amd/common/*/Kconfig: remove unneeded default n for bool options
n is the default of bool Kconfig options, so no need to have that added
to each option.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8775d84caee6fda95eb7749e96090fe05417e764
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50779
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-16 23:54:54 +00:00
Raul E Rangel 5c5f211b5b soc/amd: Move aoac.asl from picasso into common
I also removed the unnecessary #include in soc.asl.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifbd79871fd49b18f45d97f64ccd68fa96eaaebce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50572
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-16 22:30:19 +00:00
Raul E Rangel 24d024ae24 soc/amd/cezanne: Enable ACPI_SOC_NVS
This fixes the undefined reference for NVB0, NVB1, and NVB2.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib4ba24b66b9ae7899ccd40f91cdd23074f6afc4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-16 21:00:43 +00:00
Elyes HAOUAS 98f7d60d97 nb/intel/i945: Use UPMC4 macro
Change-Id: Id3fb39edb0f14d48b9ea84b882fc46790fc37524
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50632
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-16 20:57:56 +00:00
Elyes HAOUAS 608a75c05a sb/intel: Add missing <types.h>
Add needed but missing <types.h>.

Change-Id: I19d01e1837b1ee946c66d4cc22a5138b64d72078
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50577
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-16 20:57:37 +00:00
Elyes HAOUAS 030d338bb2 nb/intel: Add missing <types.h>
Add needed but missing <types.h>.

Change-Id: I801be1ca8da4b1641941d5571d2aa298470f407b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50578
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-16 20:56:56 +00:00
Kyösti Mälkki 06c761ca94 soc/intel/xeon_sp: Use common acpi_fill_mcfg()
Add MMCONF_BUS_NUMBER=256 as this was not defined for
this SoC.

Change-Id: I6ba861d3b7d5ac083c9b16c8f6ad179efd403bcd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-16 20:10:19 +00:00
Elyes HAOUAS 4a6d441637 src/soc/intel/{jasperlake,xeon_sp}: Remove unused <string.h>
Found using:
diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strstr\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/)|grep '<'

Change-Id: I0c2da6b0e019c53ac963ebf851243c126ae930b0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-16 17:32:04 +00:00
Elyes HAOUAS 2b04c0c1bd soc/intel/elkhartlake: Remove unused <string.h>
Found using:
diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strstr\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/)|grep '<'

Change-Id: I66a288df5c10c3ee5b9df599edc02aaed9a334e2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-16 17:30:27 +00:00
Elyes HAOUAS aeb5268a62 soc/intel/{alderlake,apollolake}: Remove unused <string.h>
Found using:
diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strstr\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/)|grep '<'

Change-Id: Iacf390e98eaa3e855e1df78acdee3f738945a1d2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-16 17:29:19 +00:00
Elyes HAOUAS 4a3fab0cba soc/intel/{baytrail,braswell,broadwell}: Remove unused <string.h>
Found using:
diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strstr\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/)|grep '<'

Change-Id: Idc1a8a93a779f92079a0fbbcbc63530ffc061112
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-16 17:28:12 +00:00
Elyes HAOUAS 86cf75acfb soc/mediatek: Remove unused <string.h>
Found using:
diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strstr\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/)|grep '<'

Change-Id: I7706ffe6f82e3ae2c61cacbea12d94aca48757d8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-16 17:26:16 +00:00
Elyes HAOUAS fe33f96366 soc/qualcomm: Remove unused <string.h>
Found using:
diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strstr\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/)|grep '<'

Change-Id: I78f8e115a54f869b990950a1c7d686e0f25033c8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-16 17:24:15 +00:00
Elyes HAOUAS 7e821a1526 mb/google: Remove unused <string.h>
Found using:
diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strstr\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/)|grep '<'

Change-Id: I3ba39077014c50c2dfb9fddf78813f1058c45cc1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-16 17:23:38 +00:00
Elyes HAOUAS e5446cafd6 sb/intel/*/lpc: Remove unused <string.h>
Found using:
diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strstr\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/)|grep '<'

Change-Id: I8f8655853fd1fc1f3679a4549fdaa08702f96c7b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-16 17:22:41 +00:00
Elyes HAOUAS 0526554699 soc/intel/common: Remove unused <string.h>
Found using:
diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strstr\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/)|grep '<'

Change-Id: I4cdf64119e9bfa377520d7e343434f5a6ddab3a8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-16 17:20:47 +00:00
Elyes HAOUAS a9cbfc7029 src/{drivers,security}: Remove unused <string.h>
Found using:
diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strstr\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/)|grep '<'

Change-Id: Ief86a596b036487a17f98469c04faa2f8f929cfc
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-16 17:19:01 +00:00
Elyes HAOUAS 037137de15 nb/intel: Remove unused <string.h>
Found using:
diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strstr\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/)|grep '<'

Change-Id: Ica0354fdfe6861551689e3baef94d364d9ded16d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-16 17:18:22 +00:00
Elyes HAOUAS 0c510a2ac3 mb/{intel,prodrive,protectli}: Remove unused <string.h>
Found using:
diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strstr\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/)|grep '<'

Change-Id: Id2aa085a4762355d9fb1628df40f7b43fbc81fc0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-16 17:12:49 +00:00
Elyes HAOUAS 72bb8aa940 mb/ocp/deltalake: Remove unused <string.h>
Found using:
diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strstr\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/)|grep '<'

Change-Id: I0d2c362ba9b494bf4cce280192ec0b91dce3e8bb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2021-02-16 17:11:27 +00:00
Elyes HAOUAS 485a83f1f3 mb/siemens/mc_apl1/variants/mc_apl2/mainboard.c: Clean includes
Change-Id: I14ec7d6faa20542707a1b6041e1ce358ce4a537a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-02-16 17:09:20 +00:00
Patrick Rudolph ff251d21d0 device/dram: Move SPD manufacturer names out of arch/x86
Move SPD manufacturer ID decoding to device/dram. Will be used by the
following patch outside of SMBIOS scope as well.

Change-Id: Iec175cd6ab1d20761da955785e4bc0e87ae02dbb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-16 10:43:11 +00:00
Angel Pons 20eb3506ca mb/prodrive/hermes: Improve board config EEPROM handling
* Check and print errors returned from reading from I2C
* Rework offset calculation by using more macros
* Get rid of stage-specific preprocessor code
* Define the EEPROM layout as struct
* Make use of the defined EEPROM layout to calculate offsets
* Read the UPD to disable VT-d from EEPROM

Change-Id: Iad77811318c7dfd3a3a4f8d523cfa0f457f168b6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48808
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-16 09:43:32 +00:00
Angel Pons f5502310e2 nb/intel/sandybridge: Fix description of auto-precharge bit
This bit is primarily used to issue RDA commands. There doesn't seem to
be any limitation regarding the number of address bits.

Change-Id: I2804f67319c9bc736f9086af408853056aabedd6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-16 09:43:07 +00:00
Kyösti Mälkki fce36e448d vc/google/chromeos: Always use CHROMEOS_RAMOOPS_DYNAMIC
Always allocate RAMOOPS from CBMEM and drop the related
static variable CHROMEOS_RAMOOPS_RAM_START.

Change-Id: Icfcf2991cb78cc6e9becba14cac77a04d8ada56a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50608
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-16 09:39:04 +00:00
Kyösti Mälkki 11c6b8b531 nb,soc/intel: Switch to CHROMEOS_RAMOOPS_DYNAMIC
Change-Id: I4ec59cea256a39a94b05cdeb8f914830ac0bd3f7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-16 09:38:29 +00:00
Kyösti Mälkki b8b41338aa nb/intel/sandybridge,haswell: Use chromeos_reserve_ram_oops()
Communicate the RAMOOPS section via ChromeOS GNVS.

Change-Id: I75170e6e34c20db88efa268080d2c38916b31f37
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-16 09:37:47 +00:00
Kyösti Mälkki dc0c02fe34 soc/intel: Switch guard to CHROMEOS_RAMOOPS
Change-Id: I484220342b5c1055471403f562a8c9db6a403a05
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-16 09:37:28 +00:00
Kyösti Mälkki 7fb69b01c3 soc/inteL/broadwell: Move select CHROMEOS_RAMOOPS_DYNAMIC
With this selected, chromeos_reserve_ram_oops() is a no-op.

Change-Id: I2f3b7b3c4a9549a14f2ba039c769546f9698409a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-16 09:37:07 +00:00
Kyösti Mälkki 4de1a31cb0 ACPI: Add acpi_reset_gnvs_for_wake()
With chipset_power_state filled in romstage CBMEM hooks and
GNVS allocated early in ramstage, GNVS wake source is now
also filled for normal boot path.

Change-Id: I2d44770392d14d2d6e22cc98df9d1751c8717ff3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-16 09:28:42 +00:00
Elyes HAOUAS cdd2f63947 src/acpi: Add missing <types.h>
Change-Id: Iec78183b43ea26d9de14e0ce28eef6fc0361cc95
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-16 08:15:31 +00:00
Elyes HAOUAS 826459dad9 console/vtxprintf.c: Add missing <types.h>
Change-Id: Icc2b99f9125e9059dbf3de42a1b5ca9727888166
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-16 08:15:26 +00:00
Elyes HAOUAS 8f20b12c95 nb/i945/raminit.c: Don't hard code 'bool integrated_graphics'
Change-Id: I735fa6413128cb9c17d99dfe9ffc3ee93ede51ae
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-16 08:14:22 +00:00
Kyösti Mälkki 6d085446fe soc/intel/baytrail,braswell: Drop aliases on MMCONF_BASE_ADDRESS
Add MMCONF_BUS_NUMBER=256 to match previous allocation.

Change-Id: I01a86481e392a9347afdc2860b58617b20c4f05a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-16 08:08:01 +00:00
Kyösti Mälkki c4b3903361 soc/intel: Drop aliases on MMCONF_BASE_ADDRESS
Change-Id: I5ba60c1d8c314d37b4ef71c4613e6e0629da8149
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-16 08:07:52 +00:00
Felix Held 4ef37ae68d soc/amd/cezanne/data_fabric: add ACPI names and SSDT entries
Additionally to the PCI IDs of Cezanne it also handles the Renoir ones.
The main difference between those two is that Renoir has two core
complexes while Cezanne only has one core complex. I haven't seen
incompatible changes between those two though, so for example the fabric
IDs are the same and the one that's only present in Renoir is just not
used in Cezanne. Also adding the ACPI parts for those don't have
anything to do with those differences.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3b2517bc15d872f41183a33857333f1972ff2cb9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-16 00:08:06 +00:00
Paul Menzel c4062c78a9 device: Add unit to Kconfig option name: `PRE_GRAPHICS_DELAY_MS`
It’s good practice to put the unit into the name.

Change-Id: I1493f61d4e495c22f09abf1829bb2eab9b1fd2b6
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-15 17:05:18 +00:00
Patrick Georgi 6b688f5329 src: use ARRAY_SIZE where possible
Generated with a variant of
https://coccinelle.gitlabpages.inria.fr/website/rules/array.cocci

Change-Id: I083704fd48faeb6c67bba3367fbcfe554a9f7c66
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50594
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15 11:30:40 +00:00
Elyes HAOUAS 036d66be05 soc/qualcomm/sc7180: Remove unused <console/console.h>
Change-Id: Ie71cc6f79db9f2d722f9931e887f309e0bc9ce0b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50533
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15 10:51:59 +00:00
Elyes HAOUAS b1db6744b6 commonlib/cbfs.c: Remove unuse <console/console.h>
Change-Id: I263db3c3d26a8690b3fa493cb2e317000c4dc89d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50532
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15 10:51:24 +00:00
Elyes HAOUAS 2ed14dbc80 sb/amd: Remove unused <console/console.h>
Change-Id: I8c0a40a14d0a9050b83fe5e9988db70b7f94b81c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50531
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15 10:51:10 +00:00
Elyes HAOUAS e9514a43ee soc/qualcomm: Remove unused <console/console.h>
Change-Id: Idd93ed91e854c8775cbcf721e4e332aef7b36e42
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50530
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15 10:50:47 +00:00
Elyes HAOUAS 804bb522a3 soc/mediatek: Remove unused <console/console.h>
Change-Id: If025d4c0b2ba9868d8df699fcddfcec349cdc0ea
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50529
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15 10:50:23 +00:00
Elyes HAOUAS 7cb4cb64ba soc/intel: Remove unused <console/console.h>
Change-Id: I630b7b0b1d564bcd99358caaaef4afd78c22866c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50528
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15 10:50:09 +00:00
Elyes HAOUAS f81d09d653 src/security: Remove unused <console/console.h>
Change-Id: I2b81a57ded80ef9c5cbdff06d8ca9d6b4f599777
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50526
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15 10:49:53 +00:00
Elyes HAOUAS 6f35c53bbb src/nb: Remove unused <console/console.h>
Change-Id: I55aa05f72e06b509c85f0754320c389de7e75f8d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50525
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15 10:49:08 +00:00
Elyes HAOUAS 39239e6fff src/mb: Remove unused <console/console.h>
Change-Id: I6e0f33172fbcecebddfccdf64c22685636a23936
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50524
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15 10:48:53 +00:00
Elyes HAOUAS ca77b35e4e src/drivers: Remove unused <console/console.h>
Change-Id: I38d565f82d078cb75f74f8502fcafdedd907b97d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50523
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15 10:48:39 +00:00
Elyes HAOUAS da00a298f4 src/device: Remove unused <console/console.h>
Change-Id: I30ed9661d8e84be49d362baafbb2bc624952c287
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50522
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15 10:48:28 +00:00
Elyes HAOUAS f6c4eeab1a src/arch: Remove unused <console/console.h>
Change-Id: Idb80b21bb5dc4b461f89a3414d51b7d98a8328d8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50521
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15 10:48:12 +00:00
Kyösti Mälkki e050a01a90 mb/lippert/frontrunner-af: Drop OSFL method in ASL
Method only set variable OSRV, which nobody evaluates.

Change-Id: I76d86af8ef6b75531f11612935dd097ee1e1a388
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-02-15 10:01:49 +00:00
Angel Pons 59626b8670 drivers/spi: Stop using a variable-length array
Only the call in `spi_flash_cmd_write_page_program` uses non-constant
values for the array length. However, the value for `data_len` has an
upper bound: `flash->page_size` is set to `1U << vi->page_size_shift`
which depends on the flash chip vendor info, and the largest value it
can currently have is 8. Thus, the maximum page size is currently 256.

Define the `MAX_FLASH_CMD_DATA_SIZE` macro to place an upper bound on
the amount of data that can be written in one command. Then, use this
value to allocate a fixed-size buffer in `spi_flash_cmd_write`. Also,
add a check to prevent buffer overflow problems. Finally, ensure that
the `spi_flash_cmd_write_page_program` function always writes no more
than 256 bytes of data when using the `spi_flash_cmd_write` function.

Tested on Asrock B85M Pro4 (Winbond W25Q64FV), MRC cache still works.

Change-Id: Ib630bff1b496bc276616989d4506a3c96f242e26
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-02-15 09:58:05 +00:00
Angel Pons 9cf9b85476 soc/intel/broadwell/pch: Use Lynxpoint GPIO code
This allows dropping `gpio.c` from Broadwell.

Change-Id: I6b34e11f849cdf01e402fe79d078711af94e1ec0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50081
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15 08:54:28 +00:00
Angel Pons 52e48b56e2 broadwell boards: Switch to Lynxpoint GPIO headers
Move `CROS_GPIO_DEVICE_NAME` to a new `chromeos.h` header, because
Lynxpoint uses a different value. Also drop unnecessary includes.

Tested with BUILD_TIMELESS=1, Google Tidus remains identical.

Change-Id: I38baed2c114fb93cfb82535a6ec00fb67e596d64
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50080
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15 08:53:49 +00:00
Angel Pons 733f03d6f4 soc/intel/broadwell/pch: Prepare to drop `gpio.h`
Use `lp_gpio.h` from Lynxpoint instead. Subsequent commits will update
the mainboards and then drop all GPIO code from Broadwell.

Tested with BUILD_TIMELESS=1, Google Tidus remains identical.

Change-Id: Idef89037c2ca781ac3e921abb4b3dc3f7c4b3b5f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50079
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15 08:53:28 +00:00
Angel Pons 9602a4ac77 mb/google/auron/var/samus: Replace define with literal
The `GPIO_OUT_HIGH` macro is not present on Lynxpoint headers.

Change-Id: I12dd065bee49097c602febf18c6c9940ecec5106
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50078
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15 08:52:47 +00:00
Angel Pons e80fb4bd30 mb/google/jecht/var/tidus: Switch to Lynxpoint GPIO macros
Prepare to unify Lynxpoint LP and Broadwell GPIO code.

Tested with BUILD_TIMELESS=1, Google Tidus remains identical.

Change-Id: I1521a51455e2aa148298853bb1878e82b9f0c368
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50077
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15 08:52:03 +00:00
Angel Pons c1dacb9a41 mb/google/jecht/var/rikku: Switch to Lynxpoint GPIO macros
Prepare to unify Lynxpoint LP and Broadwell GPIO code.

Tested with BUILD_TIMELESS=1, Google Rikku remains identical.

Change-Id: I4d5bec4ec18b645a14d21fbee7334761901a30df
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50076
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15 08:51:48 +00:00
Angel Pons 19a3c49539 mb/google/jecht/var/jecht: Switch to Lynxpoint GPIO macros
Prepare to unify Lynxpoint LP and Broadwell GPIO code.

Tested with BUILD_TIMELESS=1, Google Jecht remains identical.

Change-Id: I193fe1471b8ade5d03e874f92425962c1ed960c8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50075
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15 08:51:37 +00:00
Angel Pons 79520c6e94 mb/google/jecht/var/guado: Switch to Lynxpoint GPIO macros
Prepare to unify Lynxpoint LP and Broadwell GPIO code.

Tested with BUILD_TIMELESS=1, Google Guado remains identical.

Change-Id: I3a806d07b0ca147492b90feaf90235ed919b1bb2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50074
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15 08:51:23 +00:00
Angel Pons c26b567478 mb/google/auron/var/samus: Switch to Lynxpoint GPIO macros
Prepare to unify Lynxpoint LP and Broadwell GPIO code.

Tested with BUILD_TIMELESS=1, Google Samus remains identical.

Change-Id: I465457ea8e9a9716121eacc0f6d64de463f41d89
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50073
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15 08:51:10 +00:00
Angel Pons 4dadeb3f22 mb/google/auron/var/lulu: Switch to Lynxpoint GPIO macros
Prepare to unify Lynxpoint LP and Broadwell GPIO code.

Tested with BUILD_TIMELESS=1, Google Lulu remains identical.

Change-Id: I0f0a584b3354971ee8d478fd17825e498ff3e423
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50072
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15 08:50:56 +00:00
Angel Pons 7ad729c136 mb/google/auron/var/gandof: Switch to Lynxpoint GPIO macros
Prepare to unify Lynxpoint LP and Broadwell GPIO code.

Tested with BUILD_TIMELESS=1, Google Gandof remains identical.

Change-Id: I168fcad7088706ca5b21f5fbf6790b13054499e9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50071
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15 08:50:36 +00:00
Angel Pons d1ff7e43b5 mb/google/auron/var/buddy: Switch to Lynxpoint GPIO macros
Prepare to unify Lynxpoint LP and Broadwell GPIO code.

Tested with BUILD_TIMELESS=1, Google Buddy remains identical.

Change-Id: I6e6256a9cc88c9d0743150bfdf12b1b482fe157d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50070
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15 08:50:21 +00:00
Angel Pons 6259aeb86e mb/google/auron/var/auron_yuna: Switch to Lynxpoint GPIO macros
Prepare to unify Lynxpoint LP and Broadwell GPIO code.

Tested with BUILD_TIMELESS=1, Google Auron Yuna remains identical.

Change-Id: I17e6bf20114f43da2897ec320ca26d8c6f6a4b09
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50069
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15 08:49:42 +00:00
Angel Pons bb95f24115 mb/google/auron/var/auron_paine: Switch to Lynxpoint GPIO macros
Prepare to unify Lynxpoint LP and Broadwell GPIO code.

Tested with BUILD_TIMELESS=1, Google Auron Paine remains identical.

Change-Id: I00b9184fe6f002c3e089c9fbc815862d60e7694f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50068
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15 08:49:17 +00:00
Angel Pons 2d11f71220 mb/intel/wtm2: Switch to Lynxpoint GPIO macros
Prepare to unify Lynxpoint LP and Broadwell GPIO code.

Tested with BUILD_TIMELESS=1, Intel WTM2 remains identical.

Change-Id: I422421cc3c336a7a1aceaff7b37ab7c82f64a03f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50067
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15 08:48:46 +00:00
Angel Pons 2126aecb32 mb/purism/librem_bdw: Switch to Lynxpoint GPIO macros
Prepare to unify Lynxpoint LP and Broadwell GPIO code.

Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.

Change-Id: I573cd439e8284d84036e71615944f7a195155593
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50066
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15 08:48:32 +00:00
Tim Wawrzynczak d4749184c2 mb/google/brya: Add EC I/O decode windows
BUG=b:180013349
TEST=console shows successful EC <-> SoC communications

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ie09dcfa8b0de2706ffc236a978dc159594e327c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-02-15 08:25:47 +00:00
Tim Wawrzynczak ad21d6bfca mb/google/brya: Enable cr50 support
Add Kconfig options and devicetree entries for cr50 TPM.

BUG=b:180017621
TEST=verify (via console) successful cr50 communications in
verstage and payload (depthcharge).

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I80e27d0377960fb81f9149efb6f062d06432d40d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-02-15 08:25:36 +00:00
Mathew King 91a2cd4770 mb/google/guybrush: Configure non-native function GPIOs
Second pass GPIO configuration to enable the non-native function
GPIOs based on the guybrush Proto 0 reference schematic 0210.

BUG=b:177909472
TEST=builds

Change-Id: I0fdc4d7369353f88cf05e2e1ec08898d4605e602
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-02-15 08:22:53 +00:00
Raul E Rangel f41ca1ed76 soc/amd/cezanne: Add uart.c to smm so we can support DEBUG_SMI
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ife43352db564654ed538383a157431ee10856518
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-15 08:22:27 +00:00
Angel Pons ec38570ead nb/intel/sandybridge: Correct description of QCLK
QCLK means "quadrature clock", and is equivalent to one half of a full
clock cycle (tCK). Fix the comment. The `QCLK_PI` value is still valid.

Change-Id: I7089fc32381addc280a71761a377075f107b5c62
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49363
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15 08:21:33 +00:00
Patrick Rudolph fc36e9fb0e soc/intel/*: Move prmrr_core_configure
Move prmrr_core_configure before clearing MCEs.

This is required for the following patch in order to update microcode
after PRMRR has been configured, but before MCEs have been cleared.

According to Document 565432 this should be no issue in regards to
SGX activation.

Change-Id: Id2808a3989adff493aaf4175cbeccd080efaaedf
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-15 08:20:19 +00:00
Angel Pons aacbd66a85 sb/intel/lynxpoint: Clean up lp_gpio.h
Move `mainboard_gpio_map` declaration inside header and reorder some
function declarations. This is to align the header with Broadwell.

Change-Id: I436d7fdabf8d574e5dd2787fb6097f384cc8e453
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50065
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15 08:19:14 +00:00
Angel Pons f76822a75c soc/intel/broadwell/pch: Rename GPIO identifiers
Rename structs, types and functions to match Lynx Point's names.

Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.

Change-Id: I11ea27b00b5820eb5553712e0420836470ec0d27
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50064
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15 08:19:03 +00:00
Maxim Polyakov 19d4364ed6 intel/xeon_sp/util: Use get_stack_busno instead of get_cpubusnos
This function is more convenient to get the value of a single bus number
than get_cpubusnos(). Now get_cpubusnos is not used anywhere, so remove
it.

Change-Id: I71c06c2d69344d97e48609e67a3966ed8c671152
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-15 08:18:07 +00:00
Felix Held b03dc9c12b soc/amd/picasso: always include PSP secure OS in amdfw
When USE_PSPSECUREOS isn't selected, we get stuck in FSP-S.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I60d0e5ab0bd9f4d76cc48d08ca05d27c60e898c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-14 21:58:10 +00:00
Angel Pons 6ab87664b7 arch/x86: Drop `cstates` pointer from CPU drivers
Nothing uses this pointer anymore.

Change-Id: Id2dee8f4cb243114d6f7f7485402acb9b73b7900
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49808
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14 21:57:13 +00:00
Angel Pons e49dec45c8 cpu/intel/haswell: Constify ACPI c-state arrays
Change-Id: I5538d8279392238e59aba99ade4b5fe13f250ca8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49805
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14 21:57:00 +00:00
Angel Pons 618b9ade15 cpu/intel/haswell: Drop c-state table indirection
Accessing it directly allows proper bounds-checking.

Change-Id: Ifb539051e4a91ddcdb5ffec4850dc2fb30482aea
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49804
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14 21:54:55 +00:00
Angel Pons 85790d028f cpu/intel/model_206ax: Drop c-state table indirection
Accessing it directly allows proper bounds-checking.

Change-Id: I2582a7edf5fba28febe570bddccacb85a3269684
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49801
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14 21:54:48 +00:00
Angel Pons d8b9e562d0 cpu/intel/model_206ax: Replace `generate_cstate_entries`
Leverage the existing `acpigen_write_CST_package` function.

Yes, bad devicetree values can trigger undefined behavior. The old code
already had this issue, and will be addressed in subsequent commits.

Change-Id: Icec5431987d91242930efcea0c8ea4e3df3182fd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49093
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14 21:54:39 +00:00
Felix Held ea32c52a0e soc/amd/cezanne: add partial data fabric setup
I'm not 100% sure yet if this code will be common for all AMD SoCs, so
I'll add a copy for Cezanne for now. This part of the code should
probably be reworked after the initial bringup of Cezanne anyway.

DF MMIO register configuration at the beginning of
data_fabric_set_mmio_np:

=== Data Fabric MMIO configuration registers ===
Addresses are shifted to the right by 16 bits.
idx  control     base    limit
  0       a3     fc00     febf
  1       a3  1000000 fffcffff
  2       a3     d000     f7ff
  3       a0        0        0
  4       a3     fed0     fed0
  5       a0        0        0
  6       a0        0        0
  7       a0        0        0

DF MMIO register configuration at the end of data_fabric_set_mmio_np:

=== Data Fabric MMIO configuration registers ===
Addresses are shifted to the right by 16 bits.
idx  control     base    limit
  0       a3     fc00     febf
  1       a3  1000000 fffcffff
  2       a3     d000     f7ff
  3     10a3     fed0     fedf
  4       a0        0        0
  5       a0        0        0
  6       a0        0        0
  7       a0        0        0

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia243a0cad311eb210d14d6242c52f599db22515c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50624
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14 21:48:23 +00:00
Felix Held eb89ca67ef soc/amd/cezanne/include/iomap: add HPET base address
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I72559147a3f86f0cb843b74af9b148d23229ff14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50623
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14 21:48:03 +00:00
Felix Held 906f9be383 soc/amd/common/block/data_fabric: add data_fabric_print_mmio_conf
Output on Picasso at the beginning of data_fabric_set_mmio_np:

=== Data Fabric MMIO configuration registers ===
Addresses are shifted to the right by 16 bits.
idx  control     base    limit
  0       93     fc00     febf
  1       93  1000000 ffffffff
  2       93     d000     f7ff
  3       90        0        0
  4       93     fed0     fed0
  5       90        0        0
  6       90        0        0
  7       90        0        0

Output on Picasso at the end of data_fabric_set_mmio_np:

=== Data Fabric MMIO configuration registers ===
Addresses are shifted to the right by 16 bits.
idx  control     base    limit
  0       93     fc00     febf
  1       93  1000000 ffffffff
  2       93     d000     f7ff
  3     1093     fed0     fedf
  4       90        0        0
  5       90        0        0
  6       90        0        0
  7       90        0        0

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I74617dfc6099489f3c81d0e385b502f1bbecea78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50640
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14 21:46:23 +00:00
Kyösti Mälkki 05af850b28 sb/amd/cimx/sb800: Move common OSFL method in ASL
We deal with mb/lippert/frontrunner-af later since it currently
does not include <cimx/sb800/acpi/fch.asl>.

Change-Id: I30b611fc1fb01777223d7222adc96308a247a35c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50591
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14 21:36:48 +00:00
Kyösti Mälkki 29b030dfcf AGESA,binaryPI boards: Drop OSV in ASL
Not referenced anywhere in ASL.

Change-Id: I52ac4722e48e1cc377386316dc034fb45a98181a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50471
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14 21:36:14 +00:00
Kyösti Mälkki d591a5a328 ACPI: Move common _PIC method
Change-Id: I659835354570fb1d4860fcbddf2a51831170a374
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-14 21:35:47 +00:00
Kyösti Mälkki fa6a85c850 sb,soc/amd: Drop empty CIRQ call from _PIC
Change-Id: Iaa51e0530a3f72456d3d4e7a0c55b768ba63e322
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49904
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14 21:35:11 +00:00
Kyösti Mälkki 3942a902cd sb/amd/cimx/sb800: Drop CIRQ method from _PIC
Change-Id: Ie4aad7b6580100377c12f128905f7f409bdb5295
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50590
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14 21:34:22 +00:00
Felix Held 985f3e05e3 soc/amd/picasso/data_fabric: factor out common MMIO register defines
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I663a73308d33f48c6b945007f3eaac84d4712f59
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50639
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14 20:53:47 +00:00
Felix Held 602f93ed52 soc/amd/picasso/data_fabric: move more helper functions to common code
The number of data fabric MMIO registers is SoC-specific, so we need to
keep that in the SoC code. This also removes a redundant pair of
brackets and moves a loop counter declaration into the head of the loop.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8499f1c1f7bf6849b5955a463de2e06962d5de68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50638
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14 20:53:22 +00:00
Felix Held 0a1491366b soc/amd/picasso/data_fabric: use common access functions
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib8cda860ca0ff81d7703c3277aeec629d89eab45
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50622
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14 20:53:08 +00:00
Felix Held 789f6f7c35 soc/amd/common/block/data_fabric: add data_fabric_broadcast_read/write32
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I81e7ff293865ef22ed74606e1e79f67a460de4a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50621
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14 20:52:53 +00:00
Felix Held 45df9c1b91 soc/amd/common/block/data_fabric: add data_fabric_write32
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9c1ae03e9aec1dec45333e697060308cb6cbda4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50620
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14 20:52:38 +00:00
Felix Held dba3fe7ad1 soc/amd/picasso: move data_fabric_read32 to common code
The exact same mechanism is used on Cezanne.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3179d8ec35efa29f9bc66854c3690b389d980bba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50619
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14 20:52:03 +00:00
Kyösti Mälkki 6962b6ecd3 sb,soc/amd: Move _PIC method to global scope
Fix regression with commit aa969e887a ACPI: Move PICM declaration.

While mentioned in the commit message there already, the default
value for AMD boards changed from IOAPIC mode to PIC mode.

ACPI 6.3 spec has this text regarding _PIC method:

  If the platform CPU architecture supports PIC mode and the method
  is never called, the platform runtime firmware must assume PIC mode.

If MADT has IOAPIC entries, OS will want to change to APIC model. But
the method _PIC was not in the global scope so it could not be called
and therefore _PRT continued to report PIC model interrupt routing.

Already fixed for soc/amd/picasso in commit 839f668.

Change-Id: I7f3bb0d45946cec315694de1d540fea4d828348e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-02-14 19:21:03 +00:00
Felix Held aed4aca3fc soc/amd/cezanne/chipset.cb: add SMBus and data fabric PCI devices
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ica9b4adb1ec2b3663ce2d623cfe7b6539cd9c71b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50631
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14 19:09:22 +00:00
Felix Held 65418cc8b5 soc/amd/cezanne: move CPU cluster to chipset device tree
This will be common for all boards, so move it to the chipset device
tree.

TEST=CPU cluster and LAPIC still show up in console logs.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia49e7b4cfc09c60b6152b8ccc47f37b6adc1e319
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50613
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14 18:22:49 +00:00
Raul E Rangel ffdf840dbb mb/amd/majolica/mainboard: Set ACPI IRQ
We now pass the ACPI SCI IRQ to the OS, so make sure the board routes it
correctly.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1b4d5e0bfb1d9df9ac8a8c41cdf466a67f2673d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
2021-02-14 18:15:56 +00:00
Raul E Rangel 12c6a58857 soc/amd/cezanne: Fill FADT and MADT
The MADT doesn't populate the IO-APICs yet since we need FSP to
configure those.

The FADT differs from picasso in the following ways:
* The duty_offset is supposed to be 0
* Don't clear x_firmware_ctl_l
* Make the extended addresses use MMIO

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib6c3a01084a0de33894885b47c637a292d252ed4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-14 18:13:56 +00:00
Raul E Rangel 35dc4b0ede soc/amd/cezanne: Enable uCode update
TEST=Boot majolica and see microcode update
CBFS: Found 'cpu_microcode_blob.bin' @0x6900 size 0x15c0 in mcache @0xcf7fe9d8
microcode: patch id to apply = 0x0a50000b
microcode: being updated to patch id = 0x0a50000b succeeded

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: If50b1d8b3ebf4b3e6f8a9dd3ab96073e0cb92424
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-14 18:05:26 +00:00
Raul E Rangel 394c6b0922 soc/amd: Move update_microcode.c to common/block/cpu
We also want to support uCode loading on cezanne.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6f10564c93ce72aea7ff52a8565d65d8b56452f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-14 18:05:17 +00:00
Elyes HAOUAS 844775059d superio/smsc/sch5545: Add missing <types.h>
Add needed but missing <types.h>.

Change-Id: I16c6a86e8c8863a8e16a63a379484c2b47d5185e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-13 22:06:28 +00:00
Raul E Rangel f5552cef97 include/acpi/acpi.h: Add ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS
This is a magic value that means all processors.
See Table 5-52 Local APIC NMI Structure in ACPI Spec 6.3.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic2fc060fda21bec44258bcae62ddb230be542759
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-13 21:54:54 +00:00
Felix Held 86024954df soc/amd/cezanne: select ACPI support and make the compiler happy
Follow-up patches will add more functionality.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9b806569154e46418fa7d4fa35575a0acfec9132
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-13 21:39:16 +00:00
Raul E Rangel 07acbfc6a5 soc/amd/common/acpi/gpio_bank_lib.asl: Add missing header
This file references ACPIMMIO_GPIO0_BASE.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic65a1f8759d10e7d78e30cfc82895e5af8cd83a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50571
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-13 21:38:53 +00:00
Raul E Rangel 984ecf9e74 mb/google/guybrush: Add plain dsdt
Needed to enable ACPI support for cezanne.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia5869905ed053cdca5f61697cffc7f9b59370859
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-13 21:38:30 +00:00
Raul E Rangel ec38e67d6c mb/amd/majolica: Add plain dsdt
Needed to enable ACPI support for cezanne.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifd71635d3493e0cf104b60ecf94ebdf70d512b94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-13 21:38:12 +00:00
Raul E Rangel 3ac44141ba soc/amd/cezanne/acpi: Add plain soc.asl
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I227cdb7cb4848d1d26f6d7fa13ac2cc1aea08d1d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-13 20:58:57 +00:00
Felix Held 604ffa6d23 soc/amd: introduce and use common IOAPIC IDs
Stoneyridge used CONFIG_MAX_CPUS and CONFIG_MAX_CPUS + 1 directly as
IOAPIC IDs and Picasso had Kconfig options to configure that, but still
used the common SMBus controller code that used CONFIG_MAX_CPUS as ID
for the FCH IOAPIC. If a board overrides the PICASSO_FCH_IOAPIC_ID
Kconfig option to a value that isn't CONFIG_MAX_CPUS, we'll get a
mismatch between the ID that gets written into the FCH IOAPIC register
and the ID in the corresponding ACPI table. In order to avoid that add
defines to each SOC's southbridge.c and use them in all soc/amd code.

Change-Id: I94f54d3e6d284391ae6ecad00a76de18dcdd4669
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50575
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-13 20:57:23 +00:00
Felix Held 5f5b7ddbf3 soc/amd/cezanne: always include PSP secure OS in amdfw
When USE_PSPSECUREOS isn't selected, we don't even get post codes on
Majolica, so remove this option.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0ec976f40d962a2d9f2bd36dc97d86526bd661ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-13 20:53:12 +00:00
Felix Held bb3e9ef507 soc/amd/cezanne: always add S0i3 firmware part to amdfw
Without this part being present in amdfw the PSP won't enter its normal
operation mode, but goes into recovery mode instead.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If13b5495e9f246afd0317daaa53c3d2cefbaa4dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
2021-02-13 20:52:49 +00:00
Felix Held 2e1384aa47 soc/amd/cezanne/bootblock: call write_resume_eip in bootblock_c_entry
Change-Id: I0b785abdd56af3bb67e3e36e5e3b40e544f0ca5a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-13 17:09:11 +00:00
Kyösti Mälkki 84355a1aad mb/lippert/frontrunner-af: Use common sb800/acpi/pcie.asl
Change-Id: I6e6cdc49da540bd9901128bd1ef9f7060bc91f4f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-13 14:52:36 +00:00
Angel Pons ec2ee184f7 sb/intel/bd82x6x: Clean up early_me.c cosmetics
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical.

Change-Id: I0dfbaaf4cb17841de109ea6abc08022846b5bd4e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49994
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-13 11:00:32 +00:00
Angel Pons 5152f16a2b sb/intel/bd82x6x/me_smm.c: Deduplicate finalisation code
The only difference between ME7 and ME8 is the MKHI message handling.
Remove duplicated code, and also clean up includes.

Change-Id: Ia44eb29d3509eb4208ba2aed9e0cf7e8f8d2c41a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49992
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Evgeny Zinoviev <me@ch1p.io>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-13 11:00:03 +00:00
Angel Pons 5deff30059 sb/intel/bd82x6x: Move ME SMM code into a separate file
This allows dropping some preprocessor usage. The `mkhi_end_of_post`
static functions had to be renamed to avoid a name clash. A follow-up
will tidy up the code in me_smm.c to reduce some duplication.

Change-Id: I6357fed3540be87f42d1fd59534666b9092d0652
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49991
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Evgeny Zinoviev <me@ch1p.io>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-13 10:59:49 +00:00
Angel Pons c94bc8e2d0 sb/intel/bd82x6x: Relocate some static functions
This allows us to get rid of the `__unused` attributes. Subsequent
commits will separate ramstage and SMM code into separate files.

Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical.

Change-Id: I1aaef5aa23561bee04f8dd9ddca66738bca91bb4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49990
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Evgeny Zinoviev <me@ch1p.io>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-13 10:59:30 +00:00
Kyösti Mälkki 505320375e sb/intel/bd82x6x: Use HPTS() for HPET visibility
Platforms with bd82x6x do not initialise OSYS, so HPET is
always hidden.

The two boards lenovo/x201 and packardbell/ms2290 using
sb/intel/ibexpeak but still including <bd8x62x/acpi/lpc.asl>
initialised OSYS using _OSI() method and showed HPET selectively.

Change-Id: I02fffd439be2a5a9d22afd67e68abce888361214
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49486
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-13 06:28:46 +00:00
Kyösti Mälkki 4797bb9be0 intel/broadwell,lynxpoint: Use HPTS() for HPET visibility
Platforms do not initialise OSYS so HPET is always hidden.

Change-Id: I5f030b156355ea407d37cdb2eda8a3161085436f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-13 06:28:32 +00:00
Kyösti Mälkki 9a05600004 sb/intel/i82801jx: Use HPTS() for HPET visibility
Change-Id: I741d94341ed59f5b5fbb8526205e8b502764a15a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50481
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-13 06:28:20 +00:00
Kyösti Mälkki e1738143e1 sb/intel/i82801gx,ix: Use HPTS() for HPET visibility
Change-Id: Id38228265ad89e3f96ea6f37bcc0da574a3f8c3f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49484
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-13 06:28:02 +00:00
Kyösti Mälkki 4ff99a2655 sb,soc/intel: Add HPTS() for HPET visibility
Based on the detected OS the HPET ACPI device needs to
be hidden sometimes.

Change-Id: I4c6f87f30ea0de5c073b1fcf57794bb9e19d4d91
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49483
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-13 06:27:21 +00:00
Julius Werner a39c577257 trogdor: Add fingerprint power sequencing
Some Trogdor variants will include a fingerprint sensor, so this patch
adds support for its power sequencing. There is a requirement that the
fingerprint power needs to be *off* for at least 200ms, and when it is
turned back on it needs to stabilize for at least 3.5ms before taking
the FPMCU out of reset. We meet these timing requirements by splitting
the sequence across bootblock, romstage and ramstage. On current Trogdor
boards we measured <end of bootblock> to <end of romstage> at ~430ms and
<end of romstage> to <start of ramstage> at 12ms, so we easily meet the
required numbers this way.

BRANCH=trogdor
BUG=b:170284663

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Iccd77e6e1c378110fca2b2b7ff1f534fce54f8ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2021-02-12 22:17:53 +00:00
Felix Held 43ccd6a4ad mb/amd/majolica/devicetree: add CPU cluster
Change-Id: I8d8b7f3ea2502e4e49a1290b07d84d5bbb2924a7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50506
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 22:03:31 +00:00
Felix Held 34fc29ae96 soc/amd: add and use fch_enable_hpet_decode
On Picasso we missed setting this bit in coreboot and since the default
after reset is 0, we had to rely on the FSP to set this bit. Stoneyridge
and Cezanne have the HPET decode enable bit in the same position in the
same register. In the ACPI table entry written by
southbridge_write_acpi_tables the HPET entry gets added, so we should
make sure that we enable the decode.

TEST=HPET still works on Mandolin.

Change-Id: Ie98dae1d6036748f700f884d4b9653f2e59c24da
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50512
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 20:49:10 +00:00
Felix Held 1b33205909 soc/amd/common: add and use fch_enable_ioapic_decode
The default value of this bit is 0, so set it right before calling
setup_ioapic to make sure that it's set and not to have to rely on FSP
doing the right thing.

Change-Id: Ife886451a6927965769282fc5644c2085abb9585
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50513
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 20:48:28 +00:00
Felix Held 428a682abe soc/amd/cezanne: drop PWRS from GNVS
A copy of Picasso's include/nvs.h was added to Cezanne right before the
commit d6ccbb9d48 that removed it for the
other mainboards and SoCs, so apply the equivalent change here as well
to keep everything in sync.

Change-Id: I76b551c05b3c3028a3afb3bc3b77df2401aed7a8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-12 20:47:35 +00:00
Raul E Rangel ffab5e64d1 soc/amd: Move MADT IRQ override settings into common_config
This is another common ACPI setting.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iefecabae1d83996a9a4aaadd2a53c2432441e1b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50558
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 20:45:59 +00:00
Raul E Rangel 1c88b10be2 soc/amd: Move fadt device tree settings into common_config
This is ACPI specific config that applies to all the AMD SoCs. Stoney
doesn't currently use this, but we can add that functionality later.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0be7d917d7c5ba71347aa646822a883e2cf55743
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50557
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 20:45:37 +00:00
Raul E Rangel 0e560e7015 soc/amd: Move acpi_fill_mcfg into common/blocks/acpi
This is common between stoney, picasso, and cezanne.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5fb40e8c6817773212c5fbd66c5c06bd2bae1eda
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50556
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 20:45:17 +00:00
Raul E Rangel 0f3bc81210 soc/amd: Move southbridge_write_acpi_tables
This is common between all the chipsets.

It's also required by common/block/lpc/lpc.c.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I361dfabfe0c04667a2c112955133831a985d5cc0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-12 20:44:48 +00:00
Raul E Rangel 48c99db6d6 mb/amd/majolica: Add FCH IRQ routing
I left most everything as NC since we don't expose the values to the
OS yet.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7c3195ef27091f1bc61892c475ffe09137b63083
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50511
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 20:43:09 +00:00
Raul E Rangel a6529e789f soc/amd/cezanne: Add PCI IRQ Router definitions
These definitions were identical to picasso. The only thing I changed
was that I renamed Misc1 and Misc2 to HPET_L and HPET_H.

This change still doesn't write the PCI_IRQ register for all the PCI
devices. We need to refactor the picasso pci_gpp code first.

TEST=Boot majolica and see FCH IRQs being programmed.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic7e637f234d3af426959a9bbd82a0dcf25bb3c8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50451
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 20:42:35 +00:00
Angel Pons 77ef99be22 mb/google/slippy: Factor out SPD indexing
The code to read the SPD file and index it is not variant-specific.

Change-Id: Ifaedc39b683901b60abbb1d984f1d38c1ed364e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50542
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 19:52:50 +00:00
Angel Pons 9a094c4b63 nb/intel/haswell/pei_data.h: Define `SPD_LEN`
Change-Id: I34561372bcdd00b1b3e4dcd6be89fa47d2af9b42
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50541
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 19:49:16 +00:00
Angel Pons fb95555088 nb/intel/haswell: Drop unused function declaration
Change-Id: Ica612bcdac373ac013a877bb96b77b2a3f522f7f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50540
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 19:48:52 +00:00
Angel Pons a3c6ed0dff haswell boards: Correct USB config indentation
Change-Id: I72b717a41c5611cf578ce178722029b8646cbb35
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50539
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 19:48:34 +00:00
Angel Pons 33b59c9170 haswell: Drop `mainboard_fill_pei_data`
Use global variables to provide mainboard USB settings, and have the
northbridge code copy it into the `pei_data` struct. For now.

To minimize diffstat noise, this patch does not reindent the now-global
mainboard USB configuration arrays. This is cleaned up in a follow-up.

Change-Id: I273c7a6cd46734ae25b95fc11b5e188d63cac32e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50538
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 19:48:26 +00:00
Angel Pons 3b0a4899d8 mb/msi/h81m-p33: Add new mainboard
This is a µATX mainboard with a LGA1150 socket and two DDR3 DIMM slots.

Working:
 - Both DIMM slots
 - Serial port to emit spam
 - Some USB ports
 - Integrated graphics (libgfxinit)
 - DVI
 - Realtek GbE
 - All PCIe ports
 - At least one SATA port
 - RAM initialization with MRC binary
 - Flashing with flashrom
 - S3 suspend/resume
 - VBT
 - SeaBIOS 1.14 to boot Arch Linux (kernel linux-5.10.15.arch1-1)

Broken:
 - Audio. It doesn't work on stock firmware either.
   I suspect the codec hardware on my board is dead.

Untested:
 - PS/2 mouse
 - EHCI debug
 - Front USB headers
 - Non-Linux OSes
 - TPM header
 - VGA

Change-Id: I9e47747a99c65e488487fbbcac1de15b9bf5c235
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41260
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 19:39:25 +00:00
Angel Pons 11235d6875 cpu/intel/haswell/acpi.c: Correct `get_cores_per_package`
CPUID result does not change when HyperThreading is disabled on
HT-enabled CPUs, which breaks `generate_cpu_entries`. Use MSR 0x35
instead, which returns the currently-enabled core and thread count.
Also rename the function to `get_logical_cores_per_package, which is
more accurate. Based on commit 920d2b77f2 (cpu/intel/206ax/acpi.c: Fix
get_cores_per_package). The MSR definition is the same for Sandy Bridge
and Haswell.

Change-Id: I5e1789d3037780b4285c9e367ff0e2b0d4365b39
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49099
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 19:29:07 +00:00
Daniel Kang a554122553 mb/google/volteer: Correct AT24 NVM address size
Currently, the address size field of AT24 NVM is incorrect, and
Linux v5.4 kernel logs the message below:

    at24 i2c-PRP0001:02: Bad "address-width" property: 13

The valid size of the AT24 NVM is 16 bits so modify the value from
0x0D to 0x10.

BUG=b:177655681
BRANCH=none
TEST=Boot volteer and check the kernel log and see "Bad address-width"
error message is not shown.

Signed-off-by: Daniel Kang <daniel.h.kang@intel.com>
Change-Id: Ice6c3eac1e023b981217e1d7dc06587fc46b1a02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Bingbu Cao <bingbu.cao@linux.intel.com>
2021-02-12 16:59:57 +00:00
Felix Held d51fd30eef soc/amd/cezanne/smihandler: add psp_notify_smm call
TEST=Majolica still gets to SeaBIOS. Like before this patch the PSP
still has the recovery flag set in its return value, but we likely still
have some problem in the amdfw part or miss some PSP initialization in
FSP.

Change-Id: I9f343452ef2ea6b01f9b2fd0cf6371218d046046
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-12 15:29:35 +00:00
Felix Held 7cd81b91ac soc/amd/cezanne: select RTC
The RTC functionality will be used by elog.

Change-Id: I3a8d0a353620f64207d5ba8e17c145090f0c7506
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-12 14:40:13 +00:00
Felix Held 1a39aa01d1 soc/amd/picasso: move bert_reserved_region to common/block/cpu/noncar
The same functionality will eventually be needed on Cezanne.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib49124c2c774ad3352ea2f7d8d827388029be041
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-12 14:39:53 +00:00
Felix Held 9d5e724010 soc/amd: select ACPI_AMD_HARDWARE_SLEEP_VALUES in common ACPI code
Change-Id: Ib03c6799017c9f51f3ffac8400c85675ac5d63f1
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-12 14:39:30 +00:00
Felix Held ec54445cd4 soc/amd/picasso/psp: move to common code and rename to psp_smm_gen2
Change-Id: I771a7d36eea7307754386824190624a09c0e38f7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-12 14:39:09 +00:00
Matt DeVillier 218038428e mb/purism/librem_mini: move mainboard asl under variant
Upcoming librem_cnl variant(s) won't share mainboard asl.

Change-Id: I9c2c43e5ae5efe161cc2135c920a1b9dee5a1317
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-12 10:33:28 +00:00
Patrick Rudolph 90c27e9611 mb/up/squared: Select NO_UART_ON_SUPERIO
Change-Id: I4c1cadb6d38ffd3f9eddcd1292c2e6aea08791d0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49395
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 08:00:03 +00:00
Angel Pons 6f5f376b95 mb/gigabyte/ga-h61m-series: Drop useless `mainboard.asl`
Was copy-pasted from another board and is completely useless.

Change-Id: Iedb03284b4509597cff5d39dda4f98669f2e814b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-12 07:59:13 +00:00
Angel Pons b27e7db0dc mainboard: Drop unneeded `default_brightness_levels.asl`
Desktop boards do not have any backlight control.

Change-Id: Ie9f5f4d7e6ae09b3d664d53e4c03157fd4ed088e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-12 07:58:43 +00:00
Angel Pons ecbd1a0f06 my boards: Do not include `superio.asl` twice
The southbridge ASL already includes this file.

Change-Id: I492d4c860a50ac98acbcb3a51fa4d47c94baade3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-12 07:58:06 +00:00
Angel Pons 22ad95394e sb/intel/x/lpc.c: Drop commented-out `gpio_init` call
Change-Id: I4255c63f87e8243237204ac86eb85e34b5aaa225
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-12 07:56:57 +00:00
Angel Pons 6324759784 sb/intel/x/lpc.c: Drop `pch_disable_smm_only_flashing`
The southbridge common SPI support already does this.

Tested on Asrock B85M Pro4, internal flashing and MRC cache still work.

Change-Id: I7ce0ca584cd3d42a10cdb74f45742f1eadc01bfa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-12 07:56:48 +00:00
Angel Pons 9382f0c251 sb/intel/lynxpoint: Do not mask out TCO status bits
Not all TCO status bits have a corresponding enable bit. Masking out the
status register with the enable register causes these events to be lost.

Tested on Asrock B85M Pro4, BIOSWR_STS events are now detected.

Change-Id: I49abb5a4a99e943e57e0aaa6f06ff63bdf957cd3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-12 07:56:33 +00:00
Angel Pons 04f1de3e14 sb/intel/lynxpoint: Only generate SerialIO SSDT for PCH-LP
Lynxpoint PCH-H does not have SerialIO, so do not generate its SSDT.

Change-Id: Ie816ebd470df93a45826498bf21be59ff0a813bf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-12 07:56:04 +00:00
Angel Pons 1afe46913a sb/intel/lynxpoint/pch.h: Guard macro parameters
Guard against unintended operator precedence and associativity issues.

Tested on Asrock B85M Pro4, still boots.

Change-Id: I2b22af17816e5383c7eb215a773eb6750d4ed9bc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-12 07:55:24 +00:00
Angel Pons 06f1fed3a1 sb/intel/common: Move named packages out of method
IASL complains that creation of named objects within a method is highly
inefficient. Avoid this by moving these named objects out of the method.

Change-Id: Iabfb20dcb3f655658844d99ab7a3b479684d9d19
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-12 07:54:55 +00:00
Angel Pons 3529024071 nb/intel/common/fixed_bars.h: Add casts to `uintptr_t`
64-bit builds need this, as the Kconfig values fit in a 32-bit integer.

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I570374f92394f839a97e28fabc8fa07a7e673e83
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-02-12 07:52:37 +00:00
Angel Pons f95b9b4b09 nb/intel/haswell: Use common {DMI,EP,MCH}BAR accessors
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I3ff4577ce662697cb3d8fb34003217fd6275dd42
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-02-12 07:52:25 +00:00
Angel Pons ea573b04d8 sandybridge MRC boards: Drop channel disable masks
Platform code will overwrite these values anyway, so do not program them
in mainboards.

Change-Id: I7571d336a1402c6cfae5835a95dc706a28106271
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49751
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 07:52:01 +00:00
Angel Pons 64c6a746ac soc/intel/broadwell: Use southbridge common RCBA
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.

Change-Id: I94953bed3f331848271464bee829f8209167f150
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-12 07:51:22 +00:00
Karthikeyan Ramasubramanian e49dfb6c44 mb/razer/blade_stealth_kbl: Configure IRQs as level triggered for HID over I2C
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.

References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx

BUG=b:172846122
TEST=./util/abuild/abuild

Change-Id: Ifdc3f061d919c8db9001c7a4cc26eb21117958d7
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-12 07:48:54 +00:00
Karthikeyan Ramasubramanian 6bcaf6f908 mb/system76/lemp9: Configure IRQs as level triggered for HID over I2C
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.

References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx

BUG=b:172846122
TEST=./util/abuild/abuild

Change-Id: Ice096777077bd2e9cfbaf744371fc372c0c05606
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-12 07:48:42 +00:00
Felix Held e22eef7c51 soc/amd/*/Kconfig: remove redundant SMM_TSEG condition
Since SMM is in TSEG on the platforms which is the default, drop the
SMM_TSEG condition for the default of SMM_TSEG_SIZE.

Change-Id: I7bd965c0794efa12ea4886a55522cc5193a1d3ac
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50498
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 00:42:32 +00:00
Felix Held 373769f103 soc/amd/common/block/acpi/pm_state: don't rely on undefined behavior
Change-Id: I5a76a38f8d84666f6b9c0bfffecca064fa82d593
Found-by: Coverity CID 1445994
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-11 19:00:44 +00:00
Felix Held 5dd52c77f7 soc/amd/picasso/fch: remove comment about ForceStpClkRetry
The corresponding bit is marked as reserved in the PPR. Also there's no
BKDG for Picasso any more; the BKDG was mostly replaced by the PPR. Also
fix the style of the comment.

Change-Id: Iffdbb9e951cb140e4352ab0f198f72a71ba798dc
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50495
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11 17:01:11 +00:00
Raul E Rangel ea120f96c9 soc/amd/common: Fix missing header in amd_pci_utils.h
This was causing a build error because size_t wasn't defined.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia467c7d6cc0f71580d0b323cb560c444d53bd7f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-11 16:45:04 +00:00
Angel Pons ffdf1f9503 sb/intel/ibexpeak: Drop Global NVS support
Was copy-pasted from bd82x6x and no mainboard actually needs it.

The few globals moved outside the GNVS will be removed, relocated or
replaced with acpigen later.

Change-Id: I590a355f1bd1e54365b2e329cfdc62384446a15c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49280
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11 16:38:44 +00:00
Angel Pons 00f11c0290 sb/intel/i82801jx: Drop Global NVS support
Was copy-pasted from i82801ix and no mainboard actually needs it.

Change-Id: I400424540b52dc5d43aba15720b18ad57ea2ebda
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49279
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11 16:38:15 +00:00
Kyösti Mälkki aa969e887a ACPI: Move PICM declaration
Variable PICM was not inside GNVS region and can use a static
initialisation value.

For most AMD platforms PICM default changes from 1 to 0.

Fix comments about PICM==0 used to indicate use of i8259 PIC for
interrupt delivery.

Change-Id: I525ef8353514ec32941c4d0c37cab38aa320cb20
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49905
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11 16:37:28 +00:00
Kyösti Mälkki f6f1215cdb sb,soc/intel: Drop OSYS from GNVS
The value should be set by OSPM using some combination of
_OSI() queris in the \_SB._INI() method.

To maintain previous behaviour with this commit, boards where
GNVS osys initialisation was removed now do the same in ASL.

Change-Id: Id4957b12a72fbf7fa988e7ff039e47abcc072e1c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49353
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11 16:36:15 +00:00
Kyösti Mälkki d6ccbb9d48 mainboards: Drop PWRS from GNVS
Initialize variable to 1 to indicate AC power supply.
If platform has EC it will set this correctly based on
whether plugged on the charger or not.

Change-Id: I3f834cf7563b9e512fcab34cdb7a27a9f0fd31c0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49352
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11 16:35:32 +00:00
Raul E Rangel e0936a56ec mb/amd/majolica: Add chromeos support
This change enables vboot support. To use it add CHROMEOS=y to your
config.

TEST=Boot majolica and see verstage run, and then see depthcharge load.

coreboot-4.13-1730-g881092709a5e Fri Feb  5 23:50:28 UTC 2021 verstage starting (log level: 8)...
Phase 1
FMAP: area GBB found @ 805000 (458752 bytes)
VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
Phase 2
Phase 3
FMAP: area GBB found @ 805000 (458752 bytes)
FMAP: area VBLOCK_A found @ 30000 (8192 bytes)
FMAP: area VBLOCK_A found @ 30000 (8192 bytes)
VB2:vb2_verify_keyblock() Checking keyblock signature...
VB2:vb2_verify_digest() HW RSA forbidden, using SW
VB2:vb2_rsa_verify_digest() HW modexp forbidden, using SW
FMAP: area VBLOCK_A found @ 30000 (8192 bytes)
FMAP: area VBLOCK_A found @ 30000 (8192 bytes)
VB2:vb2_verify_fw_preamble() Verifying preamble.
VB2:vb2_verify_digest() HW RSA forbidden, using SW
VB2:vb2_rsa_verify_digest() HW modexp forbidden, using SW
Phase 4
FMAP: area FW_MAIN_A found @ 32000 (3137280 bytes)
VB2:vb2api_init_hash() HW crypto forbidden by TPM flag, using SW
VB2:vb2_verify_digest() HW RSA forbidden, using SW
VB2:vb2_rsa_verify_digest() HW modexp forbidden, using SW
Saving secdata firmware
Saving secdata kernel
Saving nvdata
Slot A is selected
FMAP: area FW_MAIN_A found @ 32000 (3137280 bytes)
CBFS: mcache @0x02017000 built for 9 files, used 0x1ec of 0x800 bytes
CBFS: Found 'fallback/romstage' @0x0 size 0x753c in mcache @0x02017000
BS: verstage times (exec / console): total (unknown) / 116 ms

coreboot-4.13-1730-g881092709a5e Fri Feb  5 23:50:28 UTC 2021 romstage starting (log level: 8)...
Family_Model: 00a50f00
FMAP: area FW_MAIN_A found @ 32000 (3137280 bytes)
CBFS: Found 'fspm.bin' @0x15440 size 0x2257d in mcache @0x02017138

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I43f0c6e33649332057f41f8813a86571b06032f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-02-11 16:35:13 +00:00
Felix Held be35a3a012 soc/amd/cezanne/smihandler: add basic SMI APMC and sleep handler
Only the ACPI enable/disable functionality is implemented and sleep is
also not implemented yet. This will be added in future patches.

Change-Id: I7701944023ce2e86586679c32c4138d4488768a1
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50488
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11 16:18:48 +00:00
Felix Held bb4bee8572 soc/amd/cezanne: select soc-specific ACPI functionality
This doesn't select HAVE_ACPI_TABLES, so no ACPI tables will be
generated for now. There's also no globalnvs.asl that corresponds to
nvs.h yet. The added nvs.h has some currently unused fields, but still
having them in the struct aligns it with Picasso and also might reduce
the noise in future ACPI patches a bit. When most of the ACPI code for
Cezanne has landed, we need to do a cleanup though.

Change-Id: I3d658d284fa67e4da43a89d74686445fd5e93b1f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-11 16:18:01 +00:00
Felix Held 2e97897ea3 soc/amd/*/smihandler: use size_t and unsigned int
signed int should only be used when we need negative values and in those
cases the value shouldn't became negative.

Change-Id: Iefac021260ff363c76bf5cd3fe3619ea1dbabdba
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50486
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11 16:17:15 +00:00
Felix Held a2db88eb5a soc/amd/*/smihandler: remove replace southbridge references with fch
Change-Id: I96fc8082263800b731f1d4d9ecdc8a99c28bff32
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50485
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11 16:17:01 +00:00
Felix Held c3ce09cdac soc/amd/cezanne/chip: set device operations for UART MMIO devices
Change-Id: I5df3a61741f05364e2c20725b0b85164b197dbdc
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50484
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11 16:16:47 +00:00
Felix Held b2d8a5c017 soc/amd/cezanne: add empty mp_init_cpus
Change-Id: I845a7e2cfea58ca08cd2a6f0d884dbbbe1a7bdef
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50483
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11 16:16:37 +00:00
Felix Held aa77d1364f soc/amd/cezanne/cpu: add basic zen_2_3_init functionality
The MCA MSRs aren't getting cleared and no microcode update gets applied
for now. Both will be added later.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I38ce5d11787ffefdd0183c5540ae2683158cbee8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50482
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11 16:16:29 +00:00
Elyes HAOUAS ad581984a6 src: Remove unused <cpu/intel/model_206ax/model_206ax.h>
Change-Id: I67862a6a5110e2cab4f77388caa702494e4d71c9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-11 10:25:44 +00:00
Elyes HAOUAS 45ce5d8973 src: Remove unused <arch/cpu.h>
Change-Id: I1112aa4635a3cf3ac1c0a0834317983b4e18135a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-11 10:25:23 +00:00
Angel Pons d152837d34 soc/intel/broadwell: Remove _ADR from SerialIO ACPI devices
SerialIO is in ACPI mode for google/auron and intel/wtm2, and is
disabled for google/jecht and purism/librem_bdw. Since Broadwell
SerialIO is never used in PCI mode, _ADR can safely be dropped.

Change-Id: I9a99b8209b5c139146012aa4a92f563692b62c5e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-11 10:24:43 +00:00
Elyes HAOUAS 4f880b9ab8 sb/amd/agesa/hudson/acpi/fch.asl: Sync whitespace
Make it look more like the file under amd/pi/hudson.

Change-Id: I5b40dc5b6f54bf68113826e693ca5963fec83d38
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-02-11 10:24:03 +00:00
Elyes HAOUAS a03058a22a soc/intel/xeon_sp; Remove unneeded whitespace before tab
Change-Id: I56f0d4aa627155ee318362f626347d7990571dcb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-11 10:23:45 +00:00
Elyes HAOUAS f4f2132c64 src/mainboard: Remove unneeded whitespace before tab
Change-Id: I37f12f5cb35ea1a6ad33edb114688ce1619030a4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-11 10:23:17 +00:00
Elyes HAOUAS 388aaf734b security/intel/txt/Makefile.inc: Use tab for indent
Change-Id: Ic85a3b6cfb462f335df99e7d6c6c7aa46dc094e7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-11 10:23:04 +00:00
Elyes HAOUAS c2dd4c7a6b mb/google/volteer/variants: Remove unneeded whitespace before tab
Change-Id: I4c991e6119f14d949a2e103024132d70674f29a1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-11 10:22:34 +00:00
Elyes HAOUAS e2856be098 mb/amd/mandolin/Kconfig: Remove unneeded whitespace before tab
Change-Id: I2b52c32a607386cdc1ca00531eda4dfc0bfaab1e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-11 10:22:25 +00:00
Elyes HAOUAS f26b2e5c91 arch/x86/id.S: Remove unneeded whitespace before tab
Change-Id: I053a2a8cff3fda1a1074f74e4d4c174a0cb24d86
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-11 10:22:07 +00:00
Elyes HAOUAS 89c05c56c0 src/superio: Fix typo in comment
Change-Id: I2e5cac310af824eb9756b2aa9459239e0b5784da
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-11 10:21:54 +00:00
Angel Pons 4dc85f11d1 sb/intel/common/rtc.c: Define __SIMPLE_DEVICE__
Change-Id: Ie11fffdf907227ab315bfd4887aaa5de3602bd24
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-11 10:19:31 +00:00
Angel Pons 6f4dc8f7a4 lib/selfboot.c: Fix indentation and drop one newline
Change-Id: Ica4254297f5d05e75f852d7e9a9e7bb833dfcea7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50397
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11 10:19:17 +00:00
Elyes HAOUAS 56a676e5d0 cpu/intel/microcode: Fix typo in function parameter
Change-Id: I9b03105a6808a67c2101917e1822729407271627
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-11 10:19:04 +00:00
Elyes HAOUAS f843e0a8ef nb/intel/{haswell,sandybridge}/*/mchbar.h: Fix typo in comment
Change-Id: Ie41433ed8fcadec25007c436ec12163d729a2afe
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-11 10:18:54 +00:00
Angel Pons b53dfc727e sb/amd/agesa/hudson/amd_pci_int_defs.h: Fix comments
Change-Id: Iff701d8e6d672b3ca97d9d6361ba48736c06c6c1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-02-11 10:18:37 +00:00
Angel Pons 39a223724d sb/amd/agesa/hudson: Drop setting `ACPI_FADT_RESET_REGISTER`
It is already set in `src/arch/x86/acpi.c` function `arch_fill_fadt`.

Change-Id: Ica7e112ca253d1332ed2ea414948c8f1970d0a69
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-02-11 10:18:28 +00:00
Angel Pons 73c73dded6 sb/amd/agesa/hudson/sm.c: Drop unused `BITx` macros
Tested with BUILD_TIMELESS=1, Lenovo G505s remains identical.

Change-Id: I759bdef44f7ca0f35350901998f6820820005b38
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-11 10:18:21 +00:00
Angel Pons c64465f212 sb/amd/pi/hudson/pci.c: Remove empty init operation
Change-Id: I5620867b3044936be8ad1bf95255be5a3565bb51
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-02-11 10:17:58 +00:00
Angel Pons c3d88eee64 sb/amd/pi/hudson/imc.c: Remove duplicated comment
Change-Id: Ie2de3948a78352bbb68c9215222b8489cacb91ce
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-02-11 10:17:55 +00:00
Kevin Chiu 788eb99448 mb/google/zork: modify ELAN TP i2c IRQ to LEVEL active for dirinboz
configure IRQs as level triggered to prevent TP lost.

BUG=None
BRANCH=zork
TEST=1. emerge-zork coreboot chromeos-bootimage
     2. power on, suspend DUT to check TP is functional

Change-Id: I81ffa889fbdfb01bf3057a8258fb4dd4ad7e88d5
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50420
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11 10:17:35 +00:00
Patrick Georgi d510b60f5b Revert "mb/intel/shadowmountain: Add the ASL code"
This reverts commit 2151f7561d.

Reason for revert: It depends on the shadowmountain ramstage patch.

Error on the builder:

    IASL       /cb-build/coreboot.0/default/INTEL_SHADOWMOUNTAIN/dsdt.aml
src/mainboard/intel/shadowmountain/dsdt.asl:4:10: fatal error: baseboard/ec.h: No such file or directory
 #include <baseboard/ec.h>
          ^~~~~~~~~~~~~~~~
compilation terminated.

Change-Id: I9fa5e8cc2ad485bf82bfbda151bc46d26faef7ab
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-11 10:15:41 +00:00
V Sowmya 2151f7561d mb/intel/shadowmountain: Add the ASL code
This patch includes the DSDT ASL code for shadowmountain board.

BUG=b:175808146
TEST= Boot shadowmountain board, dump and verify the DSDT ASL entries.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I511b2d23c424b0565ad1abcc3b41cace1b89936e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49733
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11 07:43:16 +00:00
Felix Held a90854d429 soc/amd: fully commonize clear_tvalid
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I90526a566a5fbc19a7368f90421067a6c716614e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50466
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11 02:49:34 +00:00
Felix Held 3c4fd70d61 soc/amd/cezanne/smihandler: add missing southbridge_io_trap_handler
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4140fbf93e84a2620ffb88e5c65df17b23135553
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50465
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11 02:47:49 +00:00
Felix Held 574b1b9674 soc/amd: include cpu/x86/smm directory in common SMM Makefile
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id6be7aa7f295e61f873bfae1fca42260d3b0db78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50464
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11 02:46:41 +00:00
Felix Held a3a66b6e68 soc/amd: move southbridge_smi_handler to common code
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I650498321736eee3d33af51216eda1b650f11744
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50463
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11 02:45:48 +00:00
Felix Held bc134812c3 soc/amd: factor out common SMM relocation code
The common code gets moved to soc/amd/common/block/cpu/smm, since it is
related to the CPU cores and soc/amd/common/block/smi is about the SMI/
SCI functionality in the FCH part. Also relocation_handler gets renamed
to smm_relocation_handler to keep it clear what it does, since it got
moved to another compilation unit.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I45224131dfd52247018c5ca19cb37c44062b03eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50462
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11 01:44:24 +00:00
Felix Held a6fc2125e7 soc/amd*/smihandler: factor out and rename clear_smi_sci_status
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifd6c3bebee1ccf7e7e7987d8ae3d9fa654019791
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50460
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11 00:50:52 +00:00
Felix Held 4f69ab729a soc/amd*/smihandler: factor out and rename clear_all_smi_status
The old name was misleading, since it doesn't disable the generation of
SMIs, but clears the status registers.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iddadbec013091c2e5993a6303e291451c3d1e7ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50459
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11 00:50:14 +00:00
Felix Held ee2a365872 soc/amd/cezanne: add empty SMM-handler
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I95908fac3b1e17a16542e5d80001fac3d22d839a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50455
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11 00:49:23 +00:00
Felix Held a8d4a718e3 soc/amd/stoneyridge: drop empty sb_enable
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9b6e0bd5c7358e2f18f929d5b098d95acbf59a5c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50437
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11 00:46:12 +00:00
Felix Held e094b1f137 soc/amd/cezanne/fch: add HAVE_SMI_HANDLER case to fch_init_acpi_ports
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie7bab29ae8d0e28c392210f8dcbaa4441ca61114
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50454
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10 23:25:21 +00:00
Paul Fagerburg 259cccd7e7 mb/google: order matters in mem_parts_used.txt
* Add comments to mem_parts_used.txt to point out that the order of
the entries matters when assigning IDs, so always add a new part
to the end of the file.
* Update existing mem_parts_used.txt to add the same comment.
* No updates to Zork variants, because they use an optional ID, so
the order actually doesn't matter there.

BUG=b:175898902
TEST=create a new variant of dalboz, trembyle, volteer, waddledee,
or waddledoo, and observe that mem_parts_used.txt has the new
verbiage.

Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: Iffbd8e69a89b1b7c810c5d25c7a6148d459d8b02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-02-10 22:15:52 +00:00
Felix Held 237bc2efaa soc/amd/stoneyridge/chip: rewrite enable_dev as switch case statement
This also aligns Stoneyridge with Picasso and Cezanne.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I35bf9915e3502c22e9dd9efa80b00a1ce70f187d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50436
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10 21:50:36 +00:00
Raul E Rangel 72616b3813 soc/amd/cezanne: Add verstage support
Setup the config required to support verstage.
The offsets are the same as picasso.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I82874d649db3c9c370e32841e6a9898efb70082e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-02-10 21:46:54 +00:00
Felix Held a634257f13 soc/amd/common/psp_gen2: print error for uninitialized MSR_PSP_ADDR
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8b6362a9eb2344293dad22357651f646774af789
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50448
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10 21:11:09 +00:00
Felix Held 583d531bd6 soc/amd/common/block/psp: factor out soc_get_psp_base_address
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib73ac92e69f1be5852a1406ba714acb6a8a04989
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-10 21:10:11 +00:00
Elyes HAOUAS 517453a6cc src/ec/quanta/ene_kb3940q/acpi/battery.asl: Convert to ASL 2.0
Change-Id: I7cc47536b0c1e2c903df29402090abfccde82406
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-10 19:18:09 +00:00
Elyes HAOUAS 81d55cf6d6 src/ec/lenovo/h8/acpi/battery.asl: Convert to ASL 2.0
Change-Id: I5de6c7da2440d682378a4ceb89b4bedd689dad60
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-10 19:17:34 +00:00
Raul E Rangel 5461662c66 soc/amd/cezanne: Enable SOC_AMD_COMMON_BLOCK_SPI
Required so we pass SPI information down to depthcharge.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4ce819b537333c28d394c925331e3dbf260b7732
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-10 19:01:22 +00:00
Raul E Rangel 466edb51b4 soc/amd/common/blocks/lpc: Remove common SPI registers
Use the SoC versions instead.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia0b8129b165f8a2e6be6706ab2e3f2d39e1025a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-10 19:00:49 +00:00
Raul E Rangel 6ba1fcac34 soc/amd/cezanne: Add SPI registers
These are identical to picasso.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3ef4c51ef6d656b3b035d97a56b1875b40e89210
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-10 19:00:34 +00:00
Raul E Rangel 4f1147b541 soc/amd/picasso: Add SPI registers
The picasso SPI registers are different than the ones defined in
amdblocks/lpc.h. The BASE_ALIGNMENT has changed and the
PSP_SPI_MMIO_SEL bit has been added.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0b5a0c88c6dbb95cdbc62b949a7d30bfad1fa725
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-10 19:00:22 +00:00
Raul E Rangel f87427f1a4 soc/amd/stoneyridge: Add SPI registers
This is a copy/paste of amdblocks/lpc.h. The registers are different for
picasso and cezanne, so I'm moving them to soc.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4dfadcdc025d3581cb1423e9793a9b2181742b9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-10 19:00:17 +00:00
Elyes HAOUAS 78452a584a sb/intel/bd82x6x/acpi: Convert to ASL 2.0
Change-Id: Ib587d7a982852e7123e43337407ef20d96811719
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-10 18:04:48 +00:00
Elyes HAOUAS 93329d8189 soc/intel/xeon_sp/include/soc/acpi_asl.h: Convert to ASL 2.0
Change-Id: Ie1d31b9d02584b97b85afe970894cfe557174733
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-10 18:02:42 +00:00
Elyes HAOUAS 9edeb31d4a mb/google/poppy/var/baseboard: Convert to ASL 2.0
Change-Id: Ic3d0ea9893c3c25305e2da94681cb5ac466782fc
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50321
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10 18:01:42 +00:00
Elyes HAOUAS fc29afbdd4 soc/intel/skylake: Convert to ASL 2.0 syntax
Change-Id: Iea915b60d8ec9a1a7a2aa5926b0277cae58113a6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-10 17:52:29 +00:00
Elyes HAOUAS b4b4fa5b2f mb/intel/wtm2: Convert to ASL 2.0 syntax
Generated 'build/dsdt.dsl' files are same.

Change-Id: Id68623cfb57e889e60d66cd465612336cd8298ca
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-10 17:46:38 +00:00
Benjamin Doron e166cb38bf soc/intel/skylake/acpi: Add PEP table
PEP table is applicable to Skylake platform as well. It is required to
make the kernel load `intel_pmc_core`. Skylake boards can also use S0ix
hooks.

Tested on an out-of-tree Acer Aspire VN7-572G (Skylake-U),
intel_pmc_core kernel module is loaded and reports statuses predictably
via debugfs.

Change-Id: I08d8c1fde4f447e9292a0508649f802fdc2721e1
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49140
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10 17:45:15 +00:00
Raul E Rangel d86db1ca8e soc/amd/common/block: Fix guards for PSP transfer buffer
The transfer buffer is only required when using
VBOOT_STARTS_BEFORE_BOOTBLOCK.

The VBOOT workbuffer is only required when VBOOT_STARTS_BEFORE_BOOTBLOCK
or VBOOT_STARTS_IN_BOOTBLOCK.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I444bede3f2b716e1900e7621453351d7fddadaa3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-10 16:23:56 +00:00
Kevin Chiu 1deca23f0a mb/google/zork: modify ELAN TS i2c IRQ to LEVEL active for dirinboz
EDGE IRQ from TS might be invalid to HOST, configure IRQs
as level triggered to prevent TS lost.

BUG=b:179594439
BRANCH=zork
TEST=1. emerge-zork coreboot chromeos-bootimage
     2. power on, suspend DUT to check TS is functional

Change-Id: Ibbbc73b37932ba1359ffe6f572a15564bb341025
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50416
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10 16:21:00 +00:00
Elyes HAOUAS 6dd2e7b926 soc/amd/common/block/cpu/noncar: Remove unneeded whitespace before tab
Change-Id: Ib88358ca26876cd25247cd9619fb2b70f6859ac2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-10 16:20:13 +00:00
Kane Chen 0967d78490 mb/google/zork/var/shuboz: Adjust touchscreen settings
Modify GPIO_140 delay time and add "disable_gpio_export_in_crs"
to meet touchscreen controller power on sequence.

BUG=b:174442484
BRANCH=master
TEST=emerge-zork coreboot chromeos-bootimage

Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I36a7055b7be0963479f8a0f4dc49c92bc8fbdc9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50228
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10 16:19:12 +00:00
Felix Held 37fbbfd3bf soc/amd/picasso/smihandler: replace southbridge.c in comment with fch.c
southbridge.c was renamed and split into early_fch.c and fch.c.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie439e746fb3dfe9ec865481a76a09eab378242bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50458
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10 16:17:57 +00:00
Felix Held c8a0faab5c soc/amd/cezanne/chip: add empty set_mmio_dev_ops
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2ac5fcd17b6aed464a0d1e55f2860574501f7a8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-10 16:09:32 +00:00
Felix Held fd05601eb0 soc/amd/cezanne/chip: add empty cpu_bus_ops
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I658294c84d64c7de0ccfa74b0e830d787a3a42fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50438
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10 16:09:19 +00:00
Kane Chen c023839a84 mb/google/zork/var/shuboz: Modify touchpad setting for Jelboz
Since Jelboz support number pad,
due to one single coreboot for both Jelboz and Shuboz,
modify "overridetree.cb" setting to number pad support for Jelboz.

BUG=b:174964012
BRANCH=master
TEST=emerge-zork coreboot chromeos-bootimage

Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Ie0219419834b34b6eac589f28d3604f5f1b65679
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-02-10 16:03:08 +00:00
Felix Held 35b3cc9b6d soc/amd/block/psp/psp: raise log level of PSP failure messages
If the PSP didn't like a command this should be at least a warning on
the console and not just a debug message.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If7e5f6320631cca86813e98f82b8c0c21bf18af1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-10 14:45:21 +00:00
Elyes HAOUAS 6564842857 sb/amd/cimx/sb800/acpi: Convert to ASL 2.0 syntax
Also, fix typo on "success".
Built gizmosphere/gizmo generate identical 'build/dsdt.dsl'.

Change-Id: I6fd7056d8053f0097b5c9de6b4e2e6db38910a2e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-10 09:25:49 +00:00
Elyes HAOUAS b5a237d911 sb/amd/pi/hudson/acpi/fch.asl: Convert to ASL 2.0 syntax
Change-Id: Ie413f36ef11a42a23d7d265d7a66f5e0d088892e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-10 09:25:35 +00:00
Angel Pons 6b486e1588 soc/intel/broadwell/pch: Simplify PCI RMW operations
This reduces the differences between Lynx Point and Broadwell.

Change-Id: Ib53d73e3f89c538ba0f052a98c7aabe815a59472
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46891
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10 07:33:35 +00:00
Angel Pons 4299cb4829 nb/intel/i945: Use common {DMI,EP,MCH}BAR accessors
Tested with BUILD_TIMELESS=1, Getac P470 remains identical.

Change-Id: If6d6cba76bdd1134372ab2faa475e574fdc5fddf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-10 07:30:05 +00:00
Angel Pons e88f705946 nb/intel/x4x: Use common {DMI,EP,MCH}BAR accessors
Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change.

Change-Id: I33c17f56eac0277a12b32af777e2e1ceb086685f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-10 07:29:54 +00:00
Angel Pons 24b1d8af06 nb/intel/pineview: Use common {DMI,EP,MCH}BAR accessors
Tested with BUILD_TIMELESS=1, Foxconn D41S remains identical.

Change-Id: Ic390d3431e2aa9f5f59cb266d4c358d0eb48576c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-10 07:29:46 +00:00
Angel Pons a8df6cff16 nb/intel/ironlake: Use common {DMI,EP,MCH}BAR accessors
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.

Change-Id: I166dbebf0eaf9fe0454145d4d48a0622743916fd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-10 07:29:29 +00:00
Angel Pons d9e58dca9e nb/intel/sandybridge: Use common {DMI,EP,MCH}BAR accessors
Drop unused sandybridge.h includes to avoid build failures on Ironlake.

Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical.

Change-Id: If2f0147fe50266e2fe2098cafdf004e51282f5e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-10 07:29:14 +00:00
Angel Pons a2a9e607b1 soc/intel/broadwell: Use common MADT code
Save for some cosmetic differences, the code is equivalent.

Change-Id: I48d4b522009eee9053d247217ca03d8bfea80cdf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-10 07:28:12 +00:00
Angel Pons f21e5c06cd soc/intel/broadwell/pch: Drop `acpi_sci_irq` function
The SCI IRQ is always set to IRQ 9 in the bootblock. To allow using
common MADT code on Broadwell, hardcode it as 9 everywhere.

Change-Id: I84345b7985b1996369cecc4bcb0a3668d002a922
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-10 07:27:57 +00:00
Julius Werner e0f058ffa8 coreboot_table: Use precision when printing lb_gpio name
The lb_gpio coreboot table entries use name fields fixed to 16 bytes.
GCC will not allow creating a static initializer for such a field with a
string of more than 16 characters... but exactly 16 characters is fine,
meaning there's no room for the terminating NUL byte. The payloads (at
least depthcharge) can deal with this as well because they're checking
the size when looking at that table entry, but our printk("%16s") does
not and will happily walk over the end until somewhere else in memory we
finally find the next NUL byte.

We should probably try to avoid strings of exactly 16 characters in this
field anyway, just in case -- but since GCC doesn't warn about them they
can easily slip back in. So solve this bug by also adding a precision
field to the printk, which will make it stop overrunning the string.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ifd7beef00d828f9dc2faa4747eace6ac4ca41899
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-10 07:27:38 +00:00
Elyes HAOUAS caef68968c mb/intel/adlrvp/bootblock.c: Remove unused includes
Change-Id: I73234da6e77f83c6aeb5c40cf6ffdb3cccc4074c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-10 07:26:46 +00:00
Elyes HAOUAS 9bbb108f24 mb/emulation/qemu-q35/bootblock.c: Remove unused includes
Change-Id: I568c7260f838c03c285f2afc0e20794c06a47645
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-10 07:26:22 +00:00
Elyes HAOUAS 19b66235aa mb/gizmosphere/gizmo2/bootblock.c: Remove unused includes
Change-Id: Ibdc94e59ffa345670bbed246e94b02a7148a1971
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-10 07:25:47 +00:00
Sheng-Liang Pan 076d9b9778 mb/google/volteer/var/voxel: Add settings for noise mitgation
Enable acoustic noise mitgation for volteer platforms.

BUG=b:179328166
BRANCH=none
TEST= Measure the change in noise level by changing the values
in devicetree.

Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I279a85c7741094bb7ddf0c1fde74b31189b12171
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-02-10 07:25:33 +00:00
Benjamin Doron 448ecc0e06 soc/intel/{cnl,skl}: Add alignment check for TSEG base and size
Port commit 14d5991 (soc/intel/icelake: Add alignment check for TSEG
base and size) to remaining SoCs.

Change-Id: I90be6dfd3eb71ce66d6dfdcd711df061d880266f
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-10 07:24:32 +00:00
Shreesh Chhabbi 3c6ad8d184 mb/google/volteer: Enable external bypass, clkgate & phygate
This change sets the soc config options for external_bypass,
external_clk_gate and external_phy_gate.

BUG=b:177821896
TEST=Build coreboot for volteer

Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Change-Id: I9e5218cda79d7453bf830639ccea4e5be019b070
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50290
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10 07:23:22 +00:00
Shreesh Chhabbi fbad99f347 soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design
This change uses the following information to determine the
appropriate S0ix states to enable as per PDG document: 607872
for TGL UP3 UP Rev2p2 (section 10.13):

1. SoC - UP3 v/s UP4
2. H/W design - external phy gating, external clk gating, external bypass
3. Devices enabled at runtime - CNVi, ISH

In some cases, it is recommended to use a shallower state for
S0ix even if the higher state can be achieved (e.g. with external
gating not enabled). This recommendation is because the shallower
state is determined to provide better power savings as per the
above document. Deepest state expected on tigerlake up3 based
platforms is S0i3.2.

BUG=b:177821896
TEST=Build coreboot for volteer. Verify that deepest
S0ix substate that is enabled is S0i3.1

Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49766
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10 07:23:09 +00:00
Paul Menzel 79cc5e01b8 mb/google/zork: devicetree: Fix typo in *Coprocessor* in comment
Fixes: b3c41329fd (mb/google/zork: Add Picasso based Zork mainboard and variants)
Change-Id: I68cd5ffc3117e714919bbce56e9af4c9982b3d54
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-10 07:22:51 +00:00
Lijian Zhao 94e4961a01 acpi: Fix Coverity Scan report
Fix the issue that return value "r" in line 534 will get overwritten
problem.

BUG=CID 1445995
TEST=Build sucessful and boot up in QEMU

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Icf760b142cfecfed7c929c15ad190ac74df027b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Francois Toguo Fotso <francois.toguo.fotso@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-10 07:22:35 +00:00
Elyes HAOUAS f7a7e65aa4 src: Remove unused <boot_device.h>
Change-Id: Idbb4d72e1ba620f71e8bf882d434c103cb422615
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50201
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10 07:22:08 +00:00
Angel Pons 80594b79f9 mb/prodrive/hermes: Set Port C VREF as per EEPROM config
Configure Port C VREF according to the settings in the EEPROM.

Change-Id: I5b4f0d91fc30c6b585434b9450544281f4411ff4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50396
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10 07:21:32 +00:00
Angel Pons 082b36009c mb/prodrive/hermes: Configure 'internal audio'
Implement `mainboard_azalia_program_runtime_verbs` to configure the
Realtek ALC888 codec according to the settings in the EEPROM. The
encoding of the `internal_audio_connection` field is:

0: Disabled
1: Front HP out
2: Internal speaker

Change-Id: I5e0013217838888977aaa9259e0cfb78c82f719f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-10 07:21:22 +00:00
Angel Pons d6d71ce442 device/azalia_device: Add mainboard hook to program codecs
On some mainboards, codec configuration depends on settings that are
only known at runtime, which is impossible to specify using one verb
table. Add an optional `mainboard_azalia_program_runtime_verbs` hook
where mainboards can program runtime-dependent codec verbs.

Change-Id: I7efeba5c26051aeb5061cce191ace08c304a6c70
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-10 07:21:11 +00:00
Angel Pons 44c431e161 device/azalia_device: Add function to program a verb table
On some boards, Azalia configuration depends on config settings that are
not known at compile-time. Expose a function to program a verb table, to
be used in subsequent commits.

Change-Id: Ie9607f6e733df66f0ca26a4bb70e0864ce1d4512
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-10 07:21:00 +00:00
Angel Pons 2e77443e47 device/azalia_device.c: Correct print format
The type of `verb_size` is unsigned, thus use `%u` to print its value.

Change-Id: I2b353b940e881dc8b5f0b902509d97d89c997a70
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-10 07:20:50 +00:00
Angel Pons 06d224f65e nb/intel/x4x: Correct DDR3 turnaround table
Comparing against MRC, looks like the values for TA3 and TA4 are
backwards. All of them. Thus, correct the tables accordingly.

Tested on Acer G43T-AM3, DDR3-1066 and CL = 8 now works.

Change-Id: I2c99502b8f105c77098c888b024a4c3c2c8877d4
Tested-by: Michael Büchler <michael.buechler@posteo.net>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49388
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Büchler <michael.buechler@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10 07:20:38 +00:00
Patrick Rudolph 082f0b94ee mb/prodrive/hermes: Set mb_hda_amp_enable based on cfg
Change-Id: I13c2ece729128fe245de88c0d36ce7b4bcaf6b6d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-10 07:20:14 +00:00
Patrick Rudolph 6c2f34ab32 mb/prodrive/hermes: Drop reset functions
The reset GPIOs are already configured in bootblock.
Drop the unused ramstage code.

Change-Id: Ic99fcae2a3f00be7eebd7be618df838522dac69f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-10 07:19:48 +00:00
Mario Scheithauer 1cd95b0acf mb/siemens/mc_apl2: Switch I2C bus for RX6110SA
With a new HW revision of this board, the connection of the external RTC
RX6110SA was changed from I2C bus 0 to I2C bus 3.

Change-Id: I10dd44949973ea490b3c7e4ad83d56ce2e566adf
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-10 06:22:09 +00:00
Felix Held a3544e47fb soc/amd: Move southbridge_smi_set_eos to common/blocks/smi/smi_util
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I69466143315c1c9870a97c9ef8f68ed85f38e779
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50415
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10 01:32:03 +00:00
Felix Held 063fc1747a soc/amd: Move global_smi_enable to common/blocks/smi/smi_util
Change-Id: I4410772a8d3f2dedbb96601d87efb23b14e5f438
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42989
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10 01:31:39 +00:00
Felix Held 1a973434c5 soc/amd: Move soc_route_sci to common/blocks/smi/smi_util
Change-Id: Ic379723c0bf6e5edf5f3d63cc11b24d0e59b5075
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42988
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10 01:31:28 +00:00
Kyösti Mälkki 2fec394913 soc/amd/picasso: Move APM_CNT_SMMINFO callsite
Triggering SMI is not part of the semantics of global_smi_enable(), so
move it to the post_mp_init handler. Even without the !acpi_is_wakeup_s3
check we don't get PSP warnings/errors during resume, so we can drop the
workaround introduced in commit 5dbe45e0f5
in this patch.

Change-Id: Id0e7723c2bb9811f80fe36c38199a01445dc1d7d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42987
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10 01:31:09 +00:00
Elyes HAOUAS 708e4cb596 mb/amd/gardenia: Convert to ASL 2.0 syntax
Change-Id: I8c8845ed6eb466acff568247184c6ad6b186e9ec
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46145
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10 00:30:57 +00:00
Elyes HAOUAS db53013b18 mb/amd/olivehill: Convert to ASL 2.0 syntax
Change-Id: Icacd8c8a7b5604354a7fd04ed73ecb3bbc86e669
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46147
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10 00:30:35 +00:00
Elyes HAOUAS 67444fb952 mb/jetway/nf81-t56n-lf: Convert to ASL 2.0 syntax
Generated 'build/dsdt.dsl' are same.

Change-Id: I16eceec980c10e77f2a0aec9a420437d03fc2352
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46187
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10 00:30:13 +00:00
Elyes HAOUAS f232d30f38 mb/amd/persimmon: Convert to ASL 2.0 syntax
Generated 'build/dsdt.dsl' files are identical.

Change-Id: I492118c9287b5853e8784a6de6bc514e97c93e96
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46150
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10 00:29:56 +00:00
Elyes HAOUAS 5e03bd4f6d mb/amd/south_station: Convert to ASL 2.0 syntax
Generated 'build/dsdt.dsl' files are identical.

Change-Id: I52c33679fbb7e9807423fc0fcc470e54105013db
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46151
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10 00:29:41 +00:00
Elyes HAOUAS 94bcbca32f mb/amd/union_station: Convert to ASL 2.0 syntax
Generated build/dsdt.dsl are identical.

Change-Id: I8127b5b22e2822f4ace07c28409e501c3fcb309b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46153
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10 00:29:14 +00:00
Elyes HAOUAS e963532a96 mb/amd/inagua: Convert to ASL 2.0 syntax
Generated 'build/dsdt.dsl' files are identical.

Change-Id: I0ee0d2b83cbfd81fab43eec255bcc214b9543f82
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46146
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10 00:27:43 +00:00
Elyes HAOUAS b9c5445638 sb/amd/common/acpi: Convert 'sleepstates.asl' to ASL 2.0 syntax
Change-Id: I16919a0fd5a78d666dc7003d4e495fd41c24613d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-10 00:21:59 +00:00
Elyes HAOUAS 0a76e7a493 sb/amd/{agesa,pi}hudson/acpi: Convert 'pci_int.asl' to ASL 2.0 syntax
Change-Id: I1a382eaf122e40aeaefedf88425749616a2090d9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-10 00:19:41 +00:00
Elyes HAOUAS 668cad1c9d mb/gizmosphere/gizmo: Convert to ASL 2.0 syntax
Built for gizmosphere/gizmo (Gizmo), it provides identical dsdt.dsl file.

Change-Id: I8647080cda7715d323d38f93c33176dfe9608652
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-10 00:10:00 +00:00
Elyes HAOUAS a81c46180c sb/amd/{agesa,pi}hudson/acpi: Convert 'AmdImc.asl' to ASL 2.0 syntax
Change-Id: Ica6998026031e1b3d7286ce74a2334237d29ac74
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-10 00:09:43 +00:00
Elyes HAOUAS 0f21996c1d mb/lippert/frontrunner-af/acpi/sata.asl: Convert to ASL 2.0
Change-Id: Ife718dcec765d3b2861bce16f9ca2b6355166800
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-10 00:09:16 +00:00
Elyes HAOUAS 3759e26c87 sb/amd/agesa/hudson/acpi/fch.asl: Convert to ASL 2.0
Change-Id: I8903450b505701e1fd62c1a70b896a4dfb37d5a1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-10 00:08:20 +00:00
Elyes HAOUAS 01ae7e7de6 sb/amd/{agesa,pi}/hudson/acpi: Convert 'audio.asl' to ASL 2.0 syntax
Change-Id: I976b4c2e2aa878d8b591c3e416ffb76d7a699b39
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45863
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10 00:07:55 +00:00
Martin Roth 567e8eacfb Revert "soc/amd/picasso: Change GPIO _HID to AMDI0030"
This reverts commit 75f6ab35ff.

Reason for revert: The 5.4 Linux kernel is not configured for AMDI0030.  This causes an issue where the WP pin is not recognized.

BUG=b:179320024
TEST=WP pin shows up properly in crossystem after reverting this change.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I0850fd085b5ee70522752633900f69d4d3732321
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50052
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-09 22:48:33 +00:00
Kevin Chiu da996f893d mb/google/zork: update USB 3 controller phy Parameter for dirinboz
Recommendation from SOC to config IQ=8 for U3 port0,
vboost for all U3 ports for passing ESD pin test.

BUG=b:175192931
BRANCH=zork
TEST=1. emerge-zork coreboot
     2. run U3 SI/ESD pin test => pass

Change-Id: I42a94e03fb6f8230d4356d16b8e0d2164bc61e3f
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-02-09 22:16:18 +00:00
Felix Held 9a6fc577d1 soc/amd/picasso/cpu: move set_cstate_io_addr to common code
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3b8a38ea39d8dc56ff1249a3212fe352b3e805ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-09 21:57:24 +00:00
Felix Held dd2f3fa533 soc/amd/picasso/cpu: move get_cpu_count to common code
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0690787f492d764a20a4219822eb10fb5cd86de0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-09 21:32:15 +00:00
Raul E Rangel cf6dc7d3a1 soc/amd/cezanne: Add root_complex
This is a copy/paste of picasso with a few things removed. With this
change we can jump into depthcharge.

Allocated resources:
   PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0
   PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
   PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 2
   PCI: 00:00.0 resource base 100000 size 1f00000 align 0 gran 0 limit 0 flags e0004200 index 3
   PCI: 00:00.0 resource base 2000000 size 1c0000 align 0 gran 0 limit 0 flags f0004200 index 4
   PCI: 00:00.0 resource base 21c0000 size cde40000 align 0 gran 0 limit 0 flags e0004200 index 5
   PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
   PCI: 00:00.0 resource base 100000000 size 30e340000 align 0 gran 0 limit 0 flags e0004200 index 6
   PCI: 00:00.0 resource base 40e340000 size cc0000 align 0 gran 0 limit 0 flags f0004200 index 7
   PCI: 00:00.0 resource base 40f000000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index 8
   PCI: 00:00.0 resource base 410000000 size 20000000 align 0 gran 0 limit 0 flags f0004200 index 9
   PCI: 00:00.0 resource base cfffe000 size 2000 align 0 gran 0 limit 0 flags f0004200 index a
   PCI: 00:00.0 resource base ceffe000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index b

TEST=Boot majolica and see depthcharge finally loading:
Starting depthcharge on MAJOLICA...
new_rt5682_codec: chip = 0x1A
Looking for NVMe Controller 0x3004cac8 @ 00:01:07

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I52682ec2a06c7e219c221648f241e18e26a9358e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50339
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-09 21:29:59 +00:00
Felix Held aecca7592b soc/amd/stoneyridge/cpu: use MSR_PSP_ADDR define instead of hex number
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id9042def0f5e9d2fa994d6729c592c7e2152976b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-09 21:16:10 +00:00
Felix Held 060b8ad7a3 soc/amd/cezanne: add empty CPU driver
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I54299cadae4cb562e04a16c3b8e051c9c454db79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-09 20:46:50 +00:00
Raul E Rangel ccf99a39d2 security/vboot/bootmode: Add weak fill_lb_gpios
This change allows VBOOT to build when the mainboard hasn't implemented
any of the VBOOT functions yet.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I42ca8f0dba9fd4a868bc7b636e4ed04cbf8dfab0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50341
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-09 20:43:12 +00:00
Zheng Bao 3da5569488 soc/amd/cezanne: Enable early LPC support in bootblock stage
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I739d97ddc5afd84a4bbc7e505b423158eb820767
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-09 20:41:03 +00:00
Felix Held 6e2f5f2ee7 soc/amd/picasso: move smm_region to soc/amd/common/block/cpu/noncar
The same functionality is needed on Cezanne.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I40f9d2fe7d144e94369a417225bcca0a299d1f45
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-09 19:15:54 +00:00
Felix Held fa265fdc3b vc/amd/fsp/cezanne: add FspGuids.h
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I54579a7998d1a4a232cb5286d3f481e2e63a4476
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50402
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-09 19:13:29 +00:00
Felix Held 6302f8de83 soc/amd/picasso/memmap: drop __SIMPLE_DEVICE__
No PCI or PNP functions are used in here.

TEST=Timeless build results in identical image.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I577e2ecdc59dbd09e739ae800cbe021168a34812
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50399
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-09 19:13:08 +00:00
Felix Held 2fff484961 soc/amd/stoneyridge/memmap: drop __SIMPLE_DEVICE__
No PCI or PNP functions are used in here.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I46851656db1f1866a82f06ceab67c93019cc6af1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-02-09 19:11:17 +00:00
Elyes HAOUAS 26a692145a src: Add missing <cbmem.h>
Change-Id: I75a816c594b326df8a4aa5458bb055fca35e1741
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-09 15:26:51 +00:00
Kyösti Mälkki cc93c6e474 soc/amd,intel: Drop s3_resume parameter on FSP-S functions
ACPI S3 is a global state and it is no longer needed to
pass it as a parameter.

Change-Id: Id0639a47ea65c210b9a79e6ca89cee819e7769b1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-09 07:53:23 +00:00
Kyösti Mälkki 4949a3dd62 drivers/intel/fsp1_1,fsp2_0: Refactor logo display
Hide the detail of allocation from cbmem from the FSP.

Loading of a BMP logo file from CBFS is not tied to FSP
version and we do not need two copies of the code, move
it under lib/.

Change-Id: I909f2771af534993cf8ba99ff0acd0bbd2c78f04
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-09 07:52:31 +00:00
Elyes HAOUAS df89df7e59 security/tpm/tss/vendor/cr50/cr50.c: Fix typo
Change-Id: I71c0b3b28979053b73f22f280ff11ba19ee0eee2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-09 07:48:40 +00:00
Elyes HAOUAS dc41371ce6 sb/intel/i82801{dx,ix,jx}/lpc.c: Fix typo in comment
Change-Id: Id7110bb2229e7c8f5f49aae40cfdf50719d0fa25
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-09 07:48:24 +00:00
Elyes HAOUAS 7ac6ae95ca mb/google/auron/var/buddy: Convert to ASL 2.0
Change-Id: Ifd4e7b4dbdd51affb5d7696b8f3d50a7a93e767b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50319
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-09 07:47:28 +00:00
Elyes HAOUAS e7fc29740b mb/google/cyan/var/terra: Convert to ASL 2.0
Change-Id: Ice6158943c61b3e2156a2ebbf96aa73e7cf87a7e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50320
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-09 07:47:16 +00:00
Evgeny Zinoviev a24efbcb96 mb/apple/macbook21: Use common ACPI code
Use common ACPI code from ec/apple to avoid duplication between boards.

Change-Id: I790d1353adea432e9697c5edf0dbb7841d308728
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-09 07:47:05 +00:00
Evgeny Zinoviev 60aef5f8b5 mb/apple/macbookair4_2: Fix USB ports config
Disable unused ports and add comments.

Used 820-3023 board schematics as a source.

Change-Id: I2862546ca6f6929a86e77fae7337368742bb9ba8
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-09 07:46:55 +00:00
Elyes HAOUAS eb26530e2c sb/amd/pi/hudson/acpi/lpc.asl: Convert to ASL 2.0
Change-Id: Id50b9a0f0e3f90f5288b420280d762b8a86a6527
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-09 07:46:47 +00:00
Elyes HAOUAS e20a2b4427 src/ec/acpi/ec.asl: Convert to ASL 2.0
Change-Id: I078ca86cf9e948d4dd4338fca842ae3e580228ef
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-09 07:46:40 +00:00
Elyes HAOUAS 72ff4b774d soc/amd/stoneyridge/acpi: Convert to ASL 2.0
Change-Id: I71c296cdc0180a2832aeb51434de3302a54b5db8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-09 07:46:35 +00:00
Kevin Chiu 2f33a671b4 mb/google/zork: update telemetry settings for dirinboz
update telemetry to improve the performance.

BUG=b:168585079
BRANCH=zork
TEST=1. emerge-zork coreboot
     2. run AMD stardust test => pass

Change-Id: Ie0c941815d062d9af01858faf2121bc69f23ab44
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-09 00:46:32 +00:00
Felix Held b743178ab3 soc/amd/common/memmap: add comment about types in memmap_early_dram
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reported-by: Angel Pons <th3fanbus@gmail.com>
Change-Id: I295bfcb05571492adbe81ffc579a835be4abffe1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-08 22:08:14 +00:00
Felix Held 278963b91a soc/amd/picasso/iomap: change ACPI_CPU_CONTROL to match AGESA
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I80e11d9792ee4138cb376ebbe0438dc304b54527
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50288
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-08 20:11:45 +00:00
Angel Pons e4c8dc8bb1 soc/intel/{baytrail,broadwell}: Add missing <cbmem.h>
Change-Id: Ic4e55f8233e5cb5cea575ad0581adf457a45ba9a
Fixes: commit 0322bc5ed8 (src: Remove unused <cbmem.h>)
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50375
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-08 07:25:20 +00:00
Kyösti Mälkki 05d1e9e2fd soc/intel/braswell,skylake: Drop logo parameters from devicetree
We can never pass memory location of dynamically loaded BMP files in the
static devicetree. The parameters passed to FSP are filled at runtime.

Change-Id: Ib835ec0d9349ec96d5635e228063f2b7000b70fd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-08 04:57:30 +00:00
Kyösti Mälkki 62044c3e57 soc/intel: Drop CID1 from GNVS
The only reference to CID1 is in common/acpi/wifi.asl and
only two braswell boards include it. Everywhere else
the value in GNVS was unused.

Change-Id: I09ea756fb3743e33d1e221f0a0df3a6fdc3fc3ba
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-08 04:57:04 +00:00
Kyösti Mälkki 80a2e0d9b9 soc/intel: Guard TRAP method in ASL
Needed to support build with ACPI_SOC_NVS=n as SMIF object inside
GNVS disappears then.

Change-Id: Ib798187c24996b74d6345080f7d48c3f657eb512
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-08 04:56:34 +00:00
Evgeny Zinoviev 833e9bad47 sb/intel/bd82x6x: Support ME Soft Temporary Disable Mode
- Add support for ME Soft Temporary Disable Mode. In this mode, ME
  doesn't load its kernel and freezes at Bring UP (BUP) phase. This mode
  is saved in ME NVRAM (and thus will remain for next reboots and
  poweroffs).

- Add support of new CMOS option for Sandy Bridge and Ivy Bridge
  ThinkPads.

HOW TO USE

To disable ME:
1. nvramtool -w me_state=Disabled
2. reboot

To enable it back:
1. nvramtool -w me_state=Normal
2. reboot

To check current status:
intelmetool -m

Tested on ThinkPad X230 and ThinkPad X220.

BACKGROUND

There's no Intel documentation that would explain how this should be
implemented, in public. Working binary sequence for MKHI command to put
ME in Soft Temporary Disable Mode, as well as a way to bring ME out of
it (by writing to H_GS register), was found and published by researchers
from PT Security:

1.  To disable ME, BIOS issues the disable command (before End of Post)
    and reboots. ME is supposed to be disabled on the next boot after
    DID (DRAM Init Done).

    My numerous tests show that issuing the command and rebooting is not
    enough. If we reboot too early, ME will not be disabled. Apparently,
    it is doing something in background after receiving the command. It
    works with a delay of 500-1000 ms.

    I also tried to dump all known (documented) registers, such as GMES
    and HFS, before and during the next 2 seconds after execution of the
    disable command to find a possible indication that something's
    changed in ME and we're ready to reboot. Found nothing
    unfortunately.

2.  To enable ME back, host writes value 0x20000000 to H_GS.

    PT slides don't contain any more information on it, but my tests
    show, that after writing this value, GMES[31:28] is changing from
    0x01 (BUP phase) to 0x03 (Policy Module) to 0x06 (Host
    Communication). Then, after some more time, fw_init_complete bit of
    HFS becomes 1.

    This means that ME starts loading its kernel immediately, without
    reboot.

    On the other hand, Lenovo BIOS clearly perform a reboot after
    enabling it (one reboot after saving the settings, then ThinkPad
    logo appears, and then one more reboot). I'm assuming we have to
    reset too.

Change-Id: Ic01526c9731cbef4e8552bbc352133a2415787c2
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-07 23:06:52 +00:00
Angel Pons 20a609f0f7 sb/intel: Extract `set_global_reset` function
To avoid duplicating this function in ramstage, factor it out.

Change-Id: I64c59a01ca153770481c28ae404a5dfe8c5382d2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-07 23:06:06 +00:00
Angel Pons a6daff192f nb/intel/x4x: Constify write leveling arrays
Change-Id: I3be3952aaba1fe2da5490b071b4e3609773e84a5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-07 22:36:57 +00:00
Angel Pons 9e58afef59 nb/intel/x4x: Update write leveling comment
Fix a typo and do some style improvements.

Change-Id: Ibc7e1869faa6b9ae12a51b1c3d209bbd8e54b0d2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-07 22:36:48 +00:00
Elyes HAOUAS ffa2adf2ae arch/x86/cpu.c: Remove redundant <arch/cpu.h>
<arch/cpu.h> is chain included through <cpu/cpu.h>.

Change-Id: Iad7f23080814c6606603d9472a1bd34a6b1bd1a9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50304
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-07 22:02:26 +00:00
Elyes HAOUAS 0d2086b1ee soc/intel/broadwell/include/soc/me.h: Clean includes
Change-Id: I740b0f3341ecc49382f44e8ccabc07148c5cad79
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-07 22:02:12 +00:00
Elyes HAOUAS b3a69e12cb soc/intel/quark/storage_test.c: Remove redundant <commonlib/cbmem_id.h>
<commonlib/cbmem_id.h> is already included through <cbmem.h>.

Change-Id: I0fb22114621a52359dd876fa70d881a1379d4cc2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-07 22:02:01 +00:00
Angel Pons 94eea6fe16 nb/intel/pineview: Rewrite hex values in lowercase
Most hex values are already lowercase. For consistency reasons, rewrite
uppercase hex values in lowercase.

Tested with BUILD_TIMELESS=1, Foxconn D41S does not change.

Change-Id: I185b448ca7822fa89c57efe788e05b582b259c37
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50356
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-07 21:59:51 +00:00
Angel Pons 896a1f7609 nb/intel/pineview: Delete rude and useless comment
Change-Id: I5bcadf04b5d5b9dad3523bce98942f2792be905f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50357
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-07 21:59:34 +00:00
Nico Huber 12d3768ec5 nb/intel/pineview: Clean up FIXMEs in raminit
Using MCHBAR32_AND_OR() in these two cases changes the order of
additions slightly. Originally, the MCHBAR offset and the base
register offset (0x5a4/0x5b4) were added first. Due to the added
parentheses in the register macros, now the complete register
offset is calculated first and then added to MCHBAR. Associativity
tells us that this doesn't change the result.

Changes in the resulting binary were verified manually on the
object file.

Change-Id: Id10882225c8e82b02583aa73e73d661c25abdef9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50355
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-07 21:59:19 +00:00
Angel Pons b35adab862 nb/intel/x4x: Constify DDR2 ODT table
Change-Id: Id5b5dc584ab93620ae58cf43fe0d47015d512f82
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-07 21:57:38 +00:00
Angel Pons 7d3bd6b505 nb/intel/x4x: Clean up RCOMP cosmetics
Clean up cosmetics after refactoring the code. Reflow long lines and
align values in the tables, and also remove a now-unnecessary scope.

Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical.

Change-Id: I2712c1ad5404d6968d18d762e6048c5da120ff78
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-07 21:57:29 +00:00
Angel Pons a0b97f3743 nb/intel/x4x: Drop unused first array index
The first RCOMP group (data) is programmed differently, and has its own
tables. Remove the unused first index from the other tables, and adjust
the loop bound accordingly. Cosmetics are cleaned up in a follow-up.

Tested on Asus P5QL PRO (DDR2), still boots.

Change-Id: I3010acbd00f762c91aebeaf1625ed7543b14bf74
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-07 21:57:20 +00:00
Angel Pons 244391a075 nb/intel/x4x: Unroll programming RCOMP data group
The RCOMP data group is special and is programmed differently. Prepare
to simplify the code by programming it outside of the loop. Subsequent
commits will simplify the logic even further, then clean up cosmetics.

The special DDR3 case in the loop overwrites the command group strength
multiplier value. It doesn't need to be programmed for each RCOMP group.
Add a comment to justify not programming this register while programming
the settings for the RCOMP data group.

Tested on Asus P5QL PRO (DDR2), still boots.

Change-Id: I5c2484f48e3c07e8e787b1894932e342e8e8a75c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-07 21:57:13 +00:00
Angel Pons 6b17794dda nb/intel/x4x: Report if running in async mode
Change-Id: I84d5457173598e8ff41dfb048a6858b41c5692ac
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-07 21:56:55 +00:00
Angel Pons 43a5e0cc07 nb/intel/x4x: Factor out setting Tx DLL tap and PI
These settings can be programmed with a single register write. Factor
the writes out into a single function to avoid some redundancy.

Tested on Asus P5QL PRO, still boots.

Change-Id: I3a08c255dd2b0deae650c7fe2ba4e1f4d1cef581
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-07 21:56:45 +00:00
Angel Pons 22fd0dca17 nb/intel/x4x: Correct ctrlset{2,3} register mask
MRC uses an incorrect mask when programming this register, but the reset
default value is zero and it is only programmed once. As it makes no
difference, we can safely use the correct mask. Document this difference
in a comment to indicate the deviation from MRC behavior is intentional.

The default value for this register was dumped from Asus P5QL PRO.

Change-Id: I93b0c382f76e141b319414258e40a8bfe6c7848a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-07 21:56:24 +00:00
Angel Pons b99d592752 nb/intel/x4x: Clean up cosmetics of raminit tables
Consistently use commas after the last element of arrays, and also align
columns of values and comments. Remove `MHz` units from DDR speed values
to avoid confusion, as the memory's actual clock speed is half of these.

Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical.

Change-Id: Id13022483c6221ce87d21dd21a5cfe4317a55ccd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-07 21:56:11 +00:00
Angel Pons 32f9bcaa91 nb/intel/x4x: Drop commented-out statement
Time has proven this statement to be unnecessary. Uncommenting it would
not have any effect on the existing code, thus remove it completely.

Change-Id: Iff4cdd71435e4fd69d4f3284e9fb2830fdd5b173
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-07 21:56:00 +00:00
Sheng-Liang Pan c87bcf4d9f mb/google/volteer/var/voxel: Add gpio-keys ACPI node for PENH
Use gpio_keys driver to add ACPI node for pen eject event.  Also
setting gpio wake pin for wake events.

BUG=b:176213181
TEST=emerge-volteer coreboot chromeos-bootimage

Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: If0959df5d0f069048777df81b0d4092ea90314eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-07 21:55:27 +00:00
Benjamin Doron 07dda337b7 acpi: Fix BERT size_t printf format error
Fix compilation on GCC 10.2.1 and address the underlying issue. The
printf format specifier for a size_t type is z.

Change-Id: Ieb1db6c0c3eb4947bd3617e418bac238b70ec08f
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-07 21:54:00 +00:00
Elyes HAOUAS dd754fce72 src: Remove redundant <commonlib/bsd/compiler.h>
Change-Id: Icb3108a281dfb3f21248a7065821b8237143be1a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-07 21:53:42 +00:00
Elyes HAOUAS d30d9a27dc src: Remove redundant include <rules.h>
Change-Id: Ie4692246d059734bb5bad6c64042b64068636ab6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-07 21:53:23 +00:00
Maulik V Vaghela 996bab4a20 soc/intel/alderlake: Increase VBT size to 9 KiB
Alderlake includes latest VBT (version 237 onwards),which has size of
8.5 KiB. This change is specific to alderlake so utilizing Kconfig option
to increase VBT size specifically for ADL platforms.

BUG=None
BRANCH=None
TEST=Include new VBT and boot the platform. Able to see firmware screen

Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Change-Id: I438f4bce0a2dfa208e1cd59d1cd5dd1c5ad50833
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50299
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2021-02-07 21:52:02 +00:00
Angel Pons f462b3d379 nb/intel/gm45: Factor out {DMI,EP,MCH}BAR accessors
These accessors can be reused for several other northbridges.

Tested with BUILD_TIMELESS=1, Roda RK9 remains identical.

Change-Id: Ia16ccc63dddebf938f4e9a7f5518e4d25d3e7e66
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49748
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-07 20:20:00 +00:00
Felix Held dd1fb4e38c soc/amd/stoneyridge: remove STONEYRIDGE_ACPI_IO_BASE Kconfig option
No board in tree selects a different base address, so this can be
removed from Kconfig and be treated like the other base addresses in the
I/O space that are defines in iomap.h.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iec3d4476e3a6a5d2b226edef4c41f503a0c81f33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-07 19:38:33 +00:00
Felix Held 2f8228d3c9 soc/amd/stoneyridge: remove STONEYRIDGE_ prefix of ACPI_IO_BASE define
Since I'm not sure if there are non-upstream boards that change the
default of the Kconfig value and the comment says that it needs to match
the binaryPI build, I'll do that change in a follow-up patch to allow
easy local reverts of that.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic0f08c6cb951994be6db19e10f73f0c621521c70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-07 19:37:56 +00:00
Angel Pons c715dc80f9 soc/intel/broadwell: Use common {DMI,EP,MCH}BAR accessors
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.

Change-Id: I04dbeade44d480301c9f7d336449bc54e56cb7bc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50169
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-07 19:31:34 +00:00
Angel Pons 84a37b9d55 nb/intel/ironlake: Avoid pointer arithmetics
Drop casts to prevent pointer arithmetic and for consistency with other
platforms. These macros will be factored out in a subsequent commit.

Change-Id: I959e7378a8bf46fd1772192090a751d7a2f6f470
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49747
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-07 19:30:00 +00:00
Angel Pons f1f560568b nb/intel/pineview: Guard {MCH,DMI,EP}BAR macros
Guarding the MCHBAR macro breaks reproducibility, but should not have
any functional impact.

Change-Id: I8be8d7b8a0f289d2be76d3dec43999f6b42e3265
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49746
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-07 19:28:03 +00:00
Raul E Rangel 6d26d8077a arch/x86/smbios: Add missing guard
smbios_type0_bios_version is only defined if HAVE_ACPI_TABLES is set.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I626ab954496833f46d6a785d92cc3b7e7d87e165
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-07 18:08:59 +00:00
Raul E Rangel b9e8044b28 soc/amd/cezanne/romstage: Store early dram region
Needed so we can reserve the memory.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8f5bb9d97932f75ca4ce22fbe9df4c0148acbea5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-07 18:08:07 +00:00
Raul E Rangel 899be1b352 soc/amd/picasso: Move memmap_early_dram to common blocks
We need the same functionality for cezanne.

TEST=Boot ezknil

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0800c662bb473eb571c74e76a8247298f534b53f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-07 18:07:24 +00:00
Raul E Rangel 969a5c8e85 soc/amd/cezanne/Makefile.inc: Fix indentation
We don't use spaces.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Id617e98db5b0895071ee98265f68f6106058bd63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-07 17:49:14 +00:00
Felix Held 0ffebacfd7 soc/amd/cezanne/pcie_gpp: scan internal PCI buses
TEST=The devices on the internal buses now get resources assigned.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If7ff0f2ecde9189691548e071ddcfe1916933571
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50334
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-07 17:48:59 +00:00
Felix Held 5a7e4a5982 soc/amd/cezanne/chip: add PCI bus scanning
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I76b0eb4470ac4a48e1caeaf507b5e6c45bb88119
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-07 17:48:48 +00:00
Elyes HAOUAS ad6f6d6bf1 sb/intel/lynxpoint/acpi/gpio.asl: Convert to ASL 2.0
Change-Id: I37d6cf75ee5a5cb2ff92c89178cd4469dc059403
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-07 14:57:51 +00:00
Elyes HAOUAS 7b78cde554 soc/intel/broadwell: Convert to ASL 2.0 syntax
Change-Id: Ie1b36e35c564414a4f9b36e120719857f55b862d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46238
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-07 14:54:16 +00:00
Patrick Rudolph d12f030150 mb/emulation/qemu-q35: Mark TSEG region as reserved
Mark TSEG as reserved, which is done on other platforms as well.

For some reason CorebootPayloadPkg crashes when using the region where
TSEG typically resides, which is basically RAM.
UefiPayloadPkg doesn't show this issue.

Change-Id: I3ae3659349d2a88bc3575fe9675433c054e28832
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-06 18:51:29 +00:00
James Ye a85d4a5a9c sb/intel/{bd82x6x,ibexpeak}: hide MEI if ME inoperable
- Add Kconfig option to hide the Management Engine Interface device so
  the OS doesn't try to access it, if the Management Engine is in an
  inoperable mode, e.g. if me_cleaner is used.

- Also hide the MEI if the ME is in Soft Temp Disable mode.

Change-Id: Ie4a35bf5fc196e0a02b7591cdb8633d38f0c7f3e
Signed-off-by: James Ye <jye836@gmail.com>
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39074
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-06 12:33:32 +00:00
Kevin Chiu 5b9c3ddaca mb/google/kukui: Add byte mode/single rank DRAM support for burnet/esche
ID#5: Hynix - H9HCNNNFAMMLXR-NEE (Byte mode)
ID#7: MICRON - MT53E1G32D2NP-046 WT:A (Single rank)

BUG=b:165768895
BRANCH=kukui
TEST=1. emerge-jacuzzi coreboot
     2. power on test ok

Change-Id: Iaa735c23889860218f6f6571cf0bc0b21b304b51
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-02-06 09:09:40 +00:00
V Sowmya 1b150cb000 mb/intel/shadowmountain: Add bootblock and verstage code
This patch includes the bootblock and verstage changes for
shadowmountain board.

BUG=b:175808146
TEST= Build and boot shadowmountain board till early romstage.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I5f805baf42203306ff10e91a258d9117dd986c4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2021-02-06 09:09:16 +00:00
Kevin Chiu 72463720a2 mb/google/zork: Adjust Dirinboz H1 I2C CLK
Adjust H1 I2C CLK:
404kHz -> 391 kHz

BUG=b:178656936
BRANCH=master
TEST=1. emerge-zork coreboot chromeos-bootimage
     2. power on proto board successfully
     3. measure i2c freq by scope is close to 400kHz

Change-Id: I9067db9fc7a4d6aa2ce33b86ba6a611dfd5d7838
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-02-06 09:08:44 +00:00
FrankChu 26b0bad671 mb/google/dedede/var/galtic: Configure I2C high and low time
Configure the I2C bus high and low time for all enabled I2C buses.

BUG=b:179100924
TEST=Measured the I2C bus frequency as 384 KHz, high time as 924 ns and
low time as 1680 ns.

Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I1525ecbf5baf9ae169afd7ce59079f395a2a45a8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-02-06 09:08:28 +00:00
Angel Pons b70ff52b83 intel: Define `RCBA_LENGTH` in Kconfig and use it
Change-Id: Ief81d49f04c1743b2a37633c4a35da9d6ddb0974
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50039
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-06 09:08:15 +00:00
Mathew King 6109c2cf83 mb/google/guybrush: First pass GPIO configuriation for Guybrush
BUG=b:175143925
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: Ia8211dbc3de09a61f264a0e5d44d1eac703b83c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50091
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-06 09:06:40 +00:00
Mathew King 10dd775ae3 mb/google/guybrush: Add stubs to configure GPIOs
BUG=b:175143925
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I5afd2df396ba41f7d25fa7ff6879b7c1f82f438c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-06 09:06:30 +00:00
Aamir Bohra 30cca6ca2a drivers/intel/fsp2_0: Add support for MP services2 PPI
Add support for MP services2 PPIs, which is slight modification
over MP services 1 PPIs. A new API StartupAllCPUs have been added
to allow running a task on BSP and all APs. Also the EFI_PEI_SERVICES
parameter has been removed from all MP PPI APIs.

This implementation also selects the respective MP services PPI version
supported for SoCs

BUG=b:169196864

Change-Id: Id74baf17fb90147d229c78be90268fdc3ec1badc
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-06 09:06:10 +00:00
Furquan Shaikh 5f262be24c intel: Rename config FSP_USES_MP_SERVICES_PPI to MP_SERVICES_PPI
This change renames config FSP_USES_MP_SERVICES_PPI to MP_SERVICES_PPI
in preparation to allow V1 and V2 versions of MP services PPI.

TEST=Verified that timeless build for brya, volteer, icelake_rvp,
elkhartlake_crb and waddledee shows no change in generated coreboot.rom

Change-Id: I04acf1bc3a3739b31d6e9d01b6aa97542378754f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50275
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-06 09:05:57 +00:00
Furquan Shaikh 1a5f25ea7f intel: Drop FSP_PEIM_TO_PEIM_INTERFACE
This change drops the config FSP_PEIM_TO_PEIM_INTERFACE.

FSP_PEIM_TO_PEIM_INTERFACE is used for:
* Auto-selecting FSP_USES_MP_SERVICES_PPI
* Including src/drivers/intel/fsp2_0/ppi/Kconfig
* Adding ppi to subdirs-y
* Setting USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI to y

and is selected by SoCs that want to enable MP PPI services.

Instead of using the indirect path of selecting MP PPI services, this
change allows SoC to select FSP_USES_MP_SERVICES_PPI directly. The
above uses are handled as follows:

* Auto-selecting FSP_USES_MP_SERVICES_PPI
  --> This is handled by SoC selection of FSP_USES_MP_SERVICES_PPI.
* Including src/drivers/intel/fsp2_0/ppi/Kconfig
  --> The guard isn't really required. The Kconfig options in this
  file don't present user prompts and don't really need to be guarded.
* Adding ppi to subdirs-y
  --> Makefile under ppi/ already has conditional inclusion of files
  and does not require a top-level conditional.
* Setting USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI to y
  --> This is set to y if FSP_USES_MP_SERVICES_PPI is selected by SoC.

TEST=Verified that timeless build for brya, volteer, icelake_rvp,
elkhartlake_crb and waddledee shows no change in generated coreboot.rom

Change-Id: I0664f09d85f5be372d19925d47034c76aeeef2ae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50274
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-06 09:05:42 +00:00
Kyösti Mälkki 0f30063abf soc/intel/broadwell: Conditionally skip PRE_GRAPHICS_DELAY
It was commented that the need for the delay was mainly related
to external displays and only with VBIOS execution. Move the
delay such that it is done only when we actually need to execute
the VBIOS aka option rom.

A delay is currently only defined for librem/purism_bdw in
its Kconfig. As the description of the issue sounds like it
would equally happen on other platforms when VBIOS is involved,
promote the Kconfig visible option to global scope.

Change-Id: I4503158576f35057373f003586bbf76af4d59b3d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-06 07:33:51 +00:00
Kyösti Mälkki 021c621eb0 soc/amd/stoneyridge: Create chipset_power_state in romstage
Move chipset_power_state initialisation from early ramstage
to romstage cbmem hook, like everyone else does.

Change-Id: Ib9189a70996ac6cf4515a0d504eb687941a6b5e0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-06 07:17:05 +00:00
Kyösti Mälkki 8fee9951d3 sb,soc/intel: Add wake source fields in GNVS
For the moment, these are most not used but become a necessity
for a unified <soc/nvs.h> approach.

They would be required for the implementation of _SWS method
for OSPM to determine the reason for system waking up. The related
hardware registers are present with these platforms.

It's expected that ACPI power-management related GNVS entries are
grouped together to form a single struct in later works.

Change-Id: I6d31d39ac1017cd6fdf0ac66b418d1fbb1edf8e0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50193
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-06 07:16:16 +00:00
Chris Wang 68d68f1d7c soc/amd/picasso: add UPD for RV2 USB3 phy setting adjust
add UPD for RV2 USB3 phy setting adjust.

Note: it only for RV2 silicon and not available for RV/PCO.

Usb 3.1 PHY Parameters:
1. RX_EQ_DELTA_IQ_OVRD_VAL
	-Override value for rx_eq_delta_iq. Range 0-0xF
2. RX_EQ_DELTA_IQ_OVRD_EN
	-Enable override value for rx_eq_delta_iq. Range 0-0x1
3. Override value for rx_vref_ctrl. Range 0 - 0x1F
4. Enable override value for rx_vref_ctrl. Range 0 - 0x1
5. Override value for tx_vboost_lvl: 0 - 0x7.
6. Enable override value for tx_vboost_lvl. Range: 0 - 0x1
7. Override value for rx_vref_ctrl. Range 0 - 0x1F
8. Enable override value for rx_vref_ctrl. Range 0 - 0x1
9. Override value for tx_vboost_lvl: 0 - 0x7.
10. Enable override value for tx_vboost_lvl. Range: 0 - 0x1

BUG=b:175192931
TEST=Build/verify the valule will been apply on dirinboz

Change-Id: I1d5f69e840952cc5171af1ce8597628d1bede5cb
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50240
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-05 23:36:25 +00:00
Felix Held 4cecca4925 soc/amd/cezanne/iomap: move MMIO range comment above MMIO ranges
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib7e47e3ba29d171266792fc1ffa8f18e314dc770
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50289
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-05 22:06:19 +00:00
Felix Held 7e703d77b2 soc/amd/cezanne/fch: add ACPI I/O port setup
The offsets of ACPI_CPU_CONTROL and ACPI_GPE0_BLK match the ones from
the reference code, but not the PPR. I've submitted a change request for
the PPR, so this mismatch might go away in the future. The case for
HAVE_SMI_HANDLER will be implemented in a future patch. If that one ends
up being identical to the function in soc/amd/picasso, I'll move it to
the common AMD SoC code.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If80b841df12d351d5a0c1e0d2e7bf1e31b03447f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-05 22:05:59 +00:00
Felix Held 757d645cb0 soc/amd/picasso: remove PICASSO_ACPI_IO_BASE Kconfig option
This was the only I/O base address in Kconfig, no board changed it and
if a board changed it, it needs to make sure that it won't overlap with
other I/O resources, so just use the same value as constant in the
define instead of the value from Kconfig. Also remove the PICASSO_
prefix from ACPI_IO_BASE.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7ea62f1101ddefa8785da92de5ba2aaf7945694a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-05 22:03:34 +00:00
Kyösti Mälkki 74bc46c4db soc/intel/broadwell: Convert some CONFIG(CHROMEOS) preprocessor
Change-Id: Ie3feee0448175db2b6ed4e8e37d92de3af9be371
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-05 21:00:53 +00:00
Angel Pons 35b601cd71 mb/gigabyte/ga-h61m-series: Drop broken thermal.asl
Was copy-pasted from another board and causes ACPI errors on Linux.

Change-Id: I9d62462fb7ddc788d08489bf82b110aeae6a1ffc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-05 17:46:54 +00:00
Felix Held c86acf4216 soc/amd/cezanne: populate some FSP-M UPDs
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I81a812662f921d0bf8d436238d338b6a1fa6a9ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-05 15:44:02 +00:00
Kyösti Mälkki 0589e3ce7f soc/amd/common: Refactor single GPIO programming
Make it clearer all the GPIO bank register programming
parameters originate from the same soc_amd_gpio entry.

Change-Id: I7aa6bd6996fd14dde4b1abcccbd2ae6ef933c87b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42691
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-05 15:33:00 +00:00
Kyösti Mälkki ff730feacc soc/amd/common: Separate single GPIO programming
Do this to reduce indentation a bit. Also it may be desireable
to group GPIO configuration such that some GPIOs are handled
outside program_gpios() call and would not be included in
gpio_list array.

Change-Id: I46cbe33f4d85cd9c7d70f96df82ee9b8ffe50a00
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42807
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-05 15:30:23 +00:00
Yu-Ping Wu 7aa5b5ece9 soc/mediatek/mt8192: Use LZ4 compression for MCUs
For MT8192 MCUs, replace LZMA compression with LZ4 to speed up boot
process. The loading (plus decompression) time of mcupm.bin and sspm.bin
is consistently reduced by 8ms, respectively.

BUG=b:177389446
TEST=emerge-asurada coreboot
TEST=Hayato booted up
BRANCH=none

Change-Id: Ida35e7f6e0572ad43082e53bcc69bc708cf7da44
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-02-05 09:42:58 +00:00
Frans Hendriks 739c080eef device/device.c: Print done at end of assign_resources()
First and last printk() log the same string.
Add done at end of function.

BUG = N/A
TEST = Build and boot faceboot FBG1701

Change-Id: I66a64c7473a65206c3a4c4396c8c8ecba1eb1a57
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-05 09:42:35 +00:00
Frans Hendriks a9caa50e8a device: correct code style
Revise the following aspects to follow coreboot's coding style:
 - Drop braces for single-statement condition and loop bodies.
 - Use `__func__` to print the current function's name.
 - Reflow pointer dereferences to fit in a single line.
 - Adjust the `*` position in pointer variable declarations.
 - Drop unnecessary `else` statements.

BUG = N/A
TEST = Build Compulab Intense-PC with secure oprom enabled

Change-Id: I780251d946d5bea97658476d61d25555ec768dfc
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-05 09:42:19 +00:00
Tim Chu 3d6d1075b2 soc/intel/xeon_sp/cpx: Override SMBIOS type 4 max speed
Override SMBIOS type 4 max speed. This field should be maximum speed
supported by the system. 3900MHz is expected for Cooper Lake.

Tested=Execute "dmidecode -t 4" to check max speed is correct.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I67edf657a2fe66b38e08056d558e1b360c4b8adc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-05 09:41:56 +00:00
Tim Chu 40d45996d8 arch/x86/smbios: Correct SMBIOS type 4 max speed
Now smbios type 4 max speed field will use the maximum speed of
processor itself if CPUID value can be accessed. However, this field
should be the maximum processor speed supported by the system. Here
we use smbios_cpu_get_max_speed_mhz only to get correct value.

Tested=Execute "dmidecode -t 4" to check max speed is correct.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: Iae8e01a5e455709a57d60a840f279685c8aab80f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48636
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-05 09:41:21 +00:00
Kane Chen 9853e42a8e mb/google/zork: update telemetry settings for Woomax
Improve performance and meet stardust test requirement.
PcdSet32(PcdTelemetry_VddcrVddfull_Scale_Current,102586)
PcdSet32(PcdTelemetry_VddcrVddOffset, 0)
PcdSet32(PcdTelemetry_VddcrSocfull_Scale_Current,24674)
PcdSet32(PcdTelemetry_VddcrSocOffset, 0)

BUG=b:176156237
BRANCH=zork
TEST=emerge-zork coreboot

Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I81dbfafffe7625c3d0d80419466240508f9b041b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50256
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-05 09:41:09 +00:00
Elyes HAOUAS 3be5565d5d soc/intel/skylake/acpi/irqlinks.asl: Fix typo in comment
Change-Id: Ifbe012a9867a6814f64abcfe336e5edca19df879
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50269
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-05 09:40:53 +00:00
Tim Wawrzynczak ee25a6fb0e mb/google/brya: Add support for Hynix H9HCNNNBKMMLXR-NEE LP4x DRAM
BUG=b:178681161
TEST=abuild

Change-Id: Icccfa3d1659e6c74c14a7372ea39c749a5921c64
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-05 09:40:28 +00:00
Evgeny Zinoviev 262a18ceb2 mb/apple/macbookair4_2: Add ACPI support for EC
Add ACPI support for battery, AC and lid.

I don't have MacBook Air 4,2 to test, but:

- I tested it on 5,2;
- I found decompiled DSDT for 4,2 and compared registers and bits,
  they are the same as on 5,2.

So it should work.

Change-Id: I592cb4501c878fe46684a524e729d32fb1d7920c
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-05 09:40:17 +00:00
Eric Lai 5b302b2ed2 soc/intel/alderlake: Refactor PCIE port config
Refactor PCIE port config structure. Make it easier to map from
schematic. We don't have to convert the PCIE ports RP number and
CLK source in devicetree. All the convert will be done by SoC level.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-05 09:39:58 +00:00
Angel Pons 6fb87c2b77 soc/intel/broadwell/pch/lpc.c: Program GEN_PMCON_3 in one write
This is what Lynxpoint does. It is equivalent, but simpler.

Change-Id: Ifdbb291a6cea0bb29b4e46c7a33c5abe61dbe86b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47045
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-05 09:39:50 +00:00
Evgeny Zinoviev ab5eb89a6f ec/apple: Add ACPI code for Apple MacBooks
- Move ACPI code for Apple MacBooks to a separate directory to avoid
  its duplication in mainboards
- Add AC and lid implementations for newer generations
- Rewrite old code using the new ASL syntax

Tested on MBA 5,2, MBP 8,1 and MBP 10,1.

Change-Id: I3d4585aac8e3ebbfed6ce4d4e39fbc33ac983069
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-05 09:39:31 +00:00
Angel Pons 6e732d34a0 intel: Turn `DEFAULT_RCBA` into a Kconfig symbol
Create `FIXED_RCBA_MMIO_BASE` and use it everywhere, except in cases
where a pointer cast would be necessary. Instances in Sandy Bridge MRC
code were left as-is intentionally, so as not to collide with another
cleanup patch train.

Tested with BUILD_TIMELESS=1, these boards remain identical:
- Asus P8Z77-V LX2
- Packard Bell MS2290

Change-Id: I642958fbd6f02dbf54812d6a75d6bc3087acc77a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50036
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-05 09:39:08 +00:00
Tony Huang 6e0ca68c82 mb/google/dedede: Create kracko variant
Create the kracko variant of the waddledee reference board by
copying the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0).

BUG=b:178092096
BRANCH=dedede
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_KRACKO

Change-Id: I7f8c7a4d4967e99896166ec9dd6b7381b7f6e5ed
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-02-05 09:38:49 +00:00
Felix Held 4fbae5c559 soc/amd/common/block/acpi/pm_state: add missing include
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I22862c2d29f130c741b4817dac00287ecfc71fa2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-02-04 21:13:59 +00:00
Felix Held da5553cae4 soc/amd/picasso/fch: add missing iomap.h include
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iea9666fe4f61fb503fee4060a90ec75e2d70c24f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-04 15:27:29 +00:00
John Su f37e8eaa77 mb/google/zork/variants/vilboz: Enable BayHub lv2 driver
Enable this driver along with power saving.

BUG=b:177955523
BRANCH=zork
TEST=boot and see this message:
BayHub LV2: Power-saving enabled 110102

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Icd87ea585dfaa2185abf1f7bf803e9c9a6e63972
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-04 10:34:12 +00:00
John Su 8fff297ea9 drivers/generic/bayhub_lv2: Add driver for BayHub lv2
Add a driver which puts the device into power-saving mode.

BUG=b:177955523
BRANCH=zork
TEST=boot and see this message:
BayHub LV2: Power-saving enabled 110102

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Idc1340b1a6fe7063d16c8ea16488d6e2b8b308cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-04 10:34:06 +00:00
Patrick Rudolph 27d4550430 vendorcode/intel/Makefile: Add x86_64 support
This allows to compile FSP related tools (like the FSP loader) in
x86_64 mode, but it doesn't add support for properly running x86_32
FSP on x86_64. This is handled in a separate patch.

Change-Id: I0e3099fae1b70bfe9ec0abbdddb4231ab5e2f388
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-04 10:21:49 +00:00
Patrick Rudolph 31218a4259 drivers/intel/fsp2_0: Fix running on x86_64
Add new Kconfig symbols to mark FSP binary as x86_32.
Fix the FSP headers and replace void pointers by fixed sized integers
depending on the used mode to compile the FSP.
This issue has been reported here:
https://github.com/intel/FSP/issues/59

This is necessary to run on x86_64, as pointers have different size.

Add preprocessor error to warn that x86_64 FSP isn't supported by the
current code.

Tested on Intel Skylake. FSP-M no longer returns the error "Invalid
Parameter".

Change-Id: I6015005c4ee3fc2f361985cf8cff896bcefd04fb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-04 10:21:42 +00:00
Angel Pons 37cae54034 nb/intel/x/bootblock.c Revert `include <arch/pci_io_cfg.h>`
This partially reverts:

- Commit 77d3b655ed
- Commit 487c1a24f5
- Commit 875c21f491
- Commit c4d1b47ad9
- Commit b96c358751
- Commit 9cbf26d18e

It is intentional to use <device/pci_ops.h> whenever one needs to use
PCI config access. The bootblock.c files needing I/O config do not need
to be an exception to this.

Change-Id: Ifba05717dad404a844618815c5347a05e07a3362
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-02-04 10:21:06 +00:00
Francois Toguo 522e0dbdaa acpi: Add support for reporting CrashLog in BERT table
Crash Data are collected and sent to the OS via the ACPI BERT.

BUG=None
TEST=Built, and BERT successfully generated in the crashLog flow.

Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com>
Change-Id: I00e390d735d61beac2e89a726e39119d9b06b3df
Signed-off-by: Nikunj A. Dadhania <nikunj.dadhania@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-04 10:21:02 +00:00
Nick Chen 5f30ae3714 mb/google/volteer: update thermal table for Eldrid
1. Add pl4 value
2. Change policies passive with sensor 0 and 1
3. Change granularity value with pl1 and pl2

BUG=b:178768749
TEST=make buildall

Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
Change-Id: I2f1fe9a6de4dbb587b79cb8758c5458a3ae5d768
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50111
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04 10:20:28 +00:00
Angel Pons 20ca7ebe31 mb/prodrive/hermes: Use some board settings from EEPROM
Cache the board settings in memory to avoid having to read them from the
EEPROM multiple times. For now, configure the following settings:

- DeepSx
- USB power in S5
- Power state after G3

Change-Id: Id88529a0b064c54fdf341de3856a8877109d4b14
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-04 10:19:33 +00:00
Angel Pons 7c7e9a2f16 mb/prodrive/hermes: Define board settings in EEPROM
Hermes has an EEPROM with firmware configuration data. Add definitions
to read and verify the `board settings` from the EEPROM. Subsequent
commits will hook up these EEPROM settings.

Change-Id: Id86632192ae53fd6b0e4df5b26b5a0a81e972818
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-04 10:19:26 +00:00
Sunway fe97ee33e8 mb/google/kukui: kakadu: update the initial code for BOE LCD
The latest initial code is from BOE, the vendor.

BUG=b:179206650
BRANCH=kukui
TEST=Run long time aging test and the BOE LCD shows normally.

Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com>
Change-Id: Ibc1bd5147dbda4e3b94023e7ba52ff6a18abba0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50215
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04 10:19:17 +00:00
Elyes HAOUAS 3b3d085338 src: Remove useless comments in "includes" lines
Change-Id: Ide5673dc99688422c5078c8c28ca5935fd39c854
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-04 10:18:49 +00:00
Angel Pons b3fcd5d57c soc/amd/picasso: Fix copy-paste error in macro definitions
The `_MASK` macros should be using the corresponding `_SHIFT` macros.

Change-Id: I78370e17d2396f77ab820771f93cf15957bcf674
Found-by: Coverity CID 1445928
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-04 09:55:33 +00:00
Elyes HAOUAS 7080856542 mb/clevo/cml-u/bootblock.c: Remove unused includes
Change-Id: I048e906306bf77a941b5f731ade15292fa944390
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-04 09:54:35 +00:00
Elyes HAOUAS c351e8c302 mb/amd/{parmer,thatcher}/bootblock.c: Remove unused includes
Change-Id: I4d5520649addc671527e75f9090ea45a83b5db9b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-04 09:54:18 +00:00
Mathew King 9a2b5e0ca3 mb/amd/majolica: add fmd for use when building chromeos
BUG=b:177909472
TEST=builds

Change-Id: I5eb3c60fe60e4029485fae642c88c5c013ffb3f6
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50208
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04 09:54:04 +00:00
John Zhao 21e2b5a0ce soc/intel/tigerlake: Drops 100ms delay in TBT PCIe root ports _PS0
A minimum of 100ms delay is required before sending a configuration
request to the downstream components. Since the kernel already adds
100ms, this change drops the extra 100ms delay in TBT PCIe root ports
_PS0 method in order to improve resume time.

BUG=b:177519081
TEST=Boot to kernel and validated various tests on Voxel.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ic392f9af6cd739507a80a4ca3fd126088b513304
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50086
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04 09:53:15 +00:00
Patrick Rudolph cfa02256a5 mb/emulation/qemu: Fix SMP boot
Fix booting with SMP enabled, when specifying more CPUs than supported
by the code.

Change-Id: Ib3d7c1a1a7a8633d4d434ccbd46cf92b0074b724
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-04 09:53:02 +00:00
Elyes HAOUAS 944da4828f src: Remove unused <bootstate.h>
Change-Id: I0d2ab4144970184f46e1d0e7a2464e94fa38aa63
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2021-02-04 09:51:10 +00:00
Elyes HAOUAS 865db966f8 src: Remove unused <cbfs.h>
Change-Id: Idc11f1e131df2e01864fedac864bda5e11f2d17b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-04 09:50:53 +00:00
Elyes HAOUAS 560384fe96 soc/qualcomm/sc7180/aop_load_reset.c: Add missing <program_loading.h>
Change-Id: Ibb4bf488d9398240bf54f12b5b90d0f2a5a9119b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50196
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04 09:50:41 +00:00
Elyes HAOUAS a11675c42b soc/mediatek/mt8192/spm.c: Add missing <string.h>
Change-Id: I56a4e0fb42c881026f4ee1abe30f9b356af6a68f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50168
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04 09:50:28 +00:00
Kyösti Mälkki 64120762f8 coreboot_table: Move VBOOT_VBNV support
The guard changes from (CHROMEOS && PC80_SYSTEM) to
VBOOT_VBNV_CMOS here.

Change-Id: I653285c04e864aa6a3494ba1400787fa184ba187
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-04 08:43:39 +00:00
Subrata Banik 3d93f045b2 vc/intel/fsp/fsp2_0/alderlake: Add required macros into MemInfoHob.h
The recent merge of Intel ADL FSP 2017.00 appears to have introduced a
new dependency within the file MemInfoHob.h. Adding required macros to
resolve the dependency.

BUG=b:178846328

Change-Id: I18370edca481bac5fdd483680cd7b05b216d10fc
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50254
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04 07:34:15 +00:00
Kyösti Mälkki 43881bb214 mb/google: Convert some CONFIG(CHROMEOS) preprocessor
Change-Id: Ica8691e3dc4feecbeb11ba3f5868932f926965b2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48785
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04 07:08:17 +00:00
Kyösti Mälkki 864be5bae5 mainboards: Remove default CHROMEOS=y
Even the boards with MAINBOARD_HAS_CHROMEOS need to be build-tested
with CHROMEOS=n.

Change-Id: I16fcf62a23dae1b21c77cee275c867f9c1de893b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-02-04 07:03:44 +00:00
Kyösti Mälkki dc15505795 vc/google/chromeos: Drop <acpi/vpd.asl>
This was used as a means to read the MAC address and dynamically
return it to the ethernet driver via ACPI. The kernel team ended
up going another direction so this became obsolete.

Change-Id: I7065bea4b288c689b41cc969989ec6fd87c75f1f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49902
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04 07:02:03 +00:00
Kyösti Mälkki 07bce4ba36 coreboot_table: Convert some CONFIG(CHROMEOS) preprocessor
Change-Id: I0c42720fdcc3b05337af692ed93a424575defd36
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48786
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04 07:00:32 +00:00
Kyösti Mälkki 563c860c0f coreboot_table: Drop <vboot/misc.h> include
Could have been removed with commit 63b9700b2c already.

Change-Id: Ie1083bce1794613c7dc683ae533e42fb5af39adf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50249
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04 06:59:54 +00:00
Kyösti Mälkki 368c9a1847 vc/../chromeos.asl: Drop CHROMEOS guard
coreboot proper now has a single include for this file
with the guard around it already.

Change-Id: Ice48a6af391170232a0319cc894bdb6c465c5143
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-04 06:58:51 +00:00
Felix Held 65fd33f95f vendorcode/amd/fsp/cezanne: add UPD structs from FSP build
There will be incompatible changes during the further development of the
coreboot+FSP support for Cezanne, but we do need the FSP-M UPD struct
size to match the one in the FSP header. See CB:50241 for details.

Signed-off-by: Justin Frodsham <justin.frodsham@protonmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icade1d7bcab7b85cdd25c4114590eb23b914edcd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50242
Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04 01:36:04 +00:00
Felix Held c0dbd4cb56 soc/amd/picasso: set GPE0_LIMIT to 32 and move definitions to registers
Picasso has 32 configurable GPEs, not only 28.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia156e64e7a69764776f3af7597b680b8ddd4e650
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-04 00:10:20 +00:00
Felix Held 404aea866c amd/common/block/acpi/pm_state: fix comparison in get_index_bit
In the case of passing 32 as limit the code returned -1, but should have
continued, since 32 is a valid value here.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6ca341841bad62abcb4ea26a350c539813a29de7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-04 00:10:02 +00:00
Wayne3_Wang 585f4d46cc mb/google/volteer/variants/drobit: Configure USB2 port for Type-C
USB2 ports assigned to type-C connector need to be configured properly
by the USB2_PORT_TYPE_C. and also modify the description of USB port.

BUG=b:177480902
BRANCH=firmware-volteer-13672.B
TEST=emerge-volteer coreboot chromeos-bootimage
     build Pass
     And check the typeC port function is normal by manual.

Signed-off-by: Wayne3_Wang <Wayne3_Wang@pegatron.corp-partner.google.com>
Change-Id: I9e962f8cd76e1986700821168594c50bc21553e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50217
Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-03 20:11:40 +00:00
Derek Huang ed6bda2818 soc/intel/tgl: Add configurable value for ConfigTdpLevel
According to Tigerlake TDP specifications (doc #575683, table 4-2),
TGL supports different TDP levels depends on CPU segement/package,
IA Cores and graphics configuration. For example, UP3 4-Core GT2
suppots base TDP=28W, Configurable TDP-Down_1=15W and Configurable
TDP-Down_2=12W. This configurable value can be used to select
suitable TDP level

Change-Id: I4242575807caac172b6cbe667839bf6c9241f3c5
Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-02-03 20:11:06 +00:00
David Wu e65e9dd6b1 mb/google/volteer/var/voema: Enable EEPROM for OV2740
Add ACPI entries for AT24 NVM device.

BUG=b:169551066
TEST=Build and run for basic camera functions.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ib8fb684166649f78713050d62445bf47189b06ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jim Lai <jim.lai@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-03 20:04:59 +00:00
Felix Held ee1fb0aa1a soc/amd: rename sb_init_acpi_ports to fch_init_acpi_ports
There's no dedicated south bridge any more and now we have integrated
FCHs in the SoCs.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I19126da09f034f51b134f8d6ae2006f57fac1b0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50209
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-03 20:00:48 +00:00
Felix Held 70f1af8934 soc/amd/cezanne: remove UART2/3 AOAC device offsets
UART2 and UART3 don't exist on Cezanne which now has been verified, so
remove the corresponding AOAC offsets.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I67755bd34df3a835cc39929bdc24f711d158b3a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-03 19:59:54 +00:00
Chris Wang 4c4a360018 soc/amd/picasso: clean up and re-sort UPD table
Clean up the unused UPD and re-sort the table, and also update
the new phy parameter in the soc code and overridetree.

remove:
	EDpPhySel
	EDpVersion
rename:
	DpPhyOverride -> edp_phy_override
	EDpPhySel -> edp_physel
	DpVsPemphLevel -> edp_dp_vs_pemph_level
	MarginDeemPh -> edp_margin_deemph
	Deemph6db4 -> edp_deemph_6db_4
	BoostAdj -> edp_boost_adj

eDP phy setting:
    DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00(0.4v 0db swing 0,pre-emphasis 0)
    COMMON_MAR_DEEMPH_NOM = 0x004b
    COMMON_SELDEEMPH60 = 0x0
    CMD_BUS_GLOBAL_FOR_TX_LANE0 = 0x80

BUG=b:171269338
BRANCH=zork
TEST=Build, verify the parameter pass to picasso-fsp

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I655af08e2f86398d088e30d330f49e71cf7e1275
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-02-03 17:27:30 +00:00
Zhuohao Lee 275440edf1 mb/google/volteer/variant/copano: support regular/numpad touchpad
Define the 25th bit of the fw_config for the regular touchpad
and numpad touchpad selection.

BUG=b:174027837
BRANCH=firmware-volteer-13672.B
TEST=build pass

Change-Id: Ic5d61f19fd385600cfdcdd045dab1e61b06e4663
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-03 17:23:05 +00:00
Subrata Banik c5cc741fe9 vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 2037
List of changes:
1. FSP-M Header:
- Adjust Reservedxx UPD Offset
2. FSP-S Header:
- Adjust UPD Offset for Reservedxx

Change-Id: I808cf619f43e629c6150726f2aa29e732e05fc33
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-03 15:50:10 +00:00
Zheng Bao b993cb2d6c amdfwtool:cezanne: Add entry of PSP_BOOTLOADER_AB (0x73)
Change-Id: Ie3577b403c1de7f20b6d5bcf9e1a5d47450266fe
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-03 13:48:51 +00:00
Pablo Stebler a5ce4d3e68 ec/hp/kbc1126: Wait a longer time after sending
This fixes the fan always running at full speed on ProBook 6360b,
EliteBook 8470p and ProBook 640 G1 (because the fan control command was
not sent).

On the ProBook 6360b, the EC needs about 30 ms to process the first
command on a cold boot, but other models such as the ProBook 640 G1 need
more time.

Change-Id: I8623af75c062d6aa69d4412e0627d426c69019fb
Signed-off-by: Pablo Stebler <pablo@stebler.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-03 11:52:44 +00:00
Nico Huber 19dd694401 pci_ids/intel: Add missing CFL-S GT1 IGD IDs
Change-Id: I372b6b2d602dfe116d5791bb6a6653454523b42b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Timofey Komarov <happycorsair@yandex.ru>
2021-02-03 08:58:39 +00:00
Nico Huber 1b5e855347 pci_ids/intel: Correct 0x3e96, it's a CFL-S part
Change-Id: Ibdddb3309f862f52c578e91ba3dc310dff8f70bc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Timofey Komarov <happycorsair@yandex.ru>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-03 08:58:33 +00:00
Elyes HAOUAS 39df11f104 src: Remove unused <boardid.h>
Change-Id: I960870fabde1dacfe52a8a35c253b0bd097d3e10
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-02-03 08:56:39 +00:00
Elyes HAOUAS 0322bc5ed8 src: Remove unused <cbmem.h>
Change-Id: I2279e2d7e6255a88953b2485c1f1a3b51a72c65e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-03 08:56:35 +00:00
Elyes HAOUAS a684d677fb soc/ti/am335x/header.c: Add missing include
Use of 'offsetof' needs <commonlib/bsd/helpers.h>.

Change-Id: Ie250b20f464909649b2bd038dbb757d5df637486
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44738
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-03 08:55:15 +00:00
Wayne3_Wang 49e1140879 mb/google/volteer/variants/drobit: Modify touchpad I2C sequence
Modify touchpad I2C sequence to meet requirement.

BUG=b:178512111
BRANCH=firmware-volteer-13672.B
TEST=emerge-volteer coreboot chromeos-bootimage
     build Pass
     And check the touchpad I2C5 sequence by EE.

Signed-off-by: Wayne3_Wang <Wayne3_Wang@pegatron.corp-partner.google.com>
Change-Id: Iebbeeec51b802c318ac014dcdd2603b600d931a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49958
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Hao Chou <hao_chou@pegatron.corp-partner.google.com>
Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-03 08:54:54 +00:00
Wayne3_Wang df7d4fc297 mb/google/volteer/variants/drobit: Add TBT PCIE rp setting for drobit
Add the TBT PCIE rp setting to on and also fixes system hang
in recovery screen after selected "Power off" item problem.

BUG=b:177963941
BRANCH=firmware-volteer-13672.B
TEST=emerge-volteer coreboot chromeos-bootimage
     build Pass
     And check the system can power off normally in recovery page

Cq-Depend: chrome-internal:3581043
Signed-off-by: Wayne3_Wang <Wayne3_Wang@pegatron.corp-partner.google.com>
Change-Id: Ic0a4756b4af839ea0a23febb991bd71af7733dcc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50103
Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
Reviewed-by: Ariel Chang <ariel_chang@pegatron.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-03 08:54:41 +00:00