Commit Graph

13425 Commits

Author SHA1 Message Date
Patrick Georgi b19425b46b google/veyron_speedy: remove extraneous file
veyron_speedy was deduplicated as sub-board into google/veyron, so the
addition of chromeos.fmd (identical btw) wasn't useful.

Change-Id: Ic4eb6f5fefb0812cae1b9c0475e3a296d7fa65b6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13646
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-10 15:04:47 +01:00
Patrick Georgi 6b881b24a3 google/chromeos: backup -> back up
See discussion on https://review.coreboot.org/13600 and
https://review.coreboot.org/13601

Change-Id: Ia8274b0b296d6b398f75c0d91a6fded4c5f57e10
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13643
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-10 15:04:23 +01:00
Julius Werner 3834520ba1 arch/arm64: Use correct SPSR.DAIF mask for BL31 and payload
The PSTATE mask bits for Debug exceptions, external Aborts, Interrupts
and Fast interrupts are usually best left unset: under normal
circumstances none of those exceptions should occur in firmware, and if
they do it's better to get a crash close to the code that caused it
(rather than much later when the kernel first unmasks them). For this
reason arm64_cpu_init unmasks them right after boot. However, the EL2
payload was still running with all mask bits set, which this patch
fixes.

BL31, on the other hand, explicitly wants to be entered with all masks
set (see calling convention in docs/firmware-design.md), which we had
previously not been doing. It doesn't seem to make a difference at the
moment, but since it's explicitly specified we should probably comply.

BRANCH=None
BUG=None
TEST=Booted Oak, confirmed with raw_read_daif() in payload that mask
bits are now cleared.

Change-Id: I04406da4c435ae7d44e2592c41f9807934bbc802
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6ba55bc23fbde962d91c87dc0f982437572a69a8
Original-Change-Id: Ic5fbdd4e1cd7933c8b0c7c5fe72eac2022c9553c
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/325056
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13596
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-10 09:39:36 +01:00
Julius Werner 372d0ff1d1 arch/arm64: mmu: Spot check TTB memory attributes
On ARM64, the memory type for accessing page table descriptors during
address translation is governed by the Translation Control Register
(TCR). When the MMU code accesses the same descriptors to change page
mappings, it uses the standard memory type rules (defined by the page
table descriptor for the page that contains that table, or 'device' if
the MMU is off).

Accessing the same memory with different memory types can lead to all
kinds of fun and hard to debug effects. In particular, if the TCR says
"cacheable" and the page tables say "uncacheable", page table walks will
pull stale entries into the cache and later mmu_config_range() calls
will write directly to memory, bypassing those cache lines. This means
the translations will not get updated even after a TLB flush, and later
cache flushes/evictions may write the stale entries back to memory.

Since page table configuration is currently always done from SoC code,
we can't generally ensure that the TTB is always mapped as cacheable.
We can however save developers of future SoCs a lot of headaches and
time by spot checking the attributes when the MMU gets enabled, as this
patch does.

BRANCH=None
BUG=None
TEST=Booted Oak. Manually tested get_pte() with a few addresses.

Change-Id: I3afd29dece848c4b5f759ce2f00ca2b7433374da
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f3947f4bb0abf4466006d5e3a962bbcb8919b12d
Original-Change-Id: I1008883e5ed4cc37d30cae5777a60287d3d01af0
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/323862
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13595
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-10 09:39:23 +01:00
Lee Leahy 89c61b5630 soc/intel/quark: Report CPU info
Decode the CPU variants and display the CPU info.

Testing on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file
   *  Add "select ADD_FSP_PDAT_FILE"
   *  Add "select ADD_FSP_RAW_BIN"
   *  Add "select ADD_RMU_FILE"
*  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
*  Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Successful if Quark X1000 is displayed

Change-Id: I7234a6d81a48cdd02708b80663147e2b09ba979e
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13605
Tested-by: build bot (Jenkins)
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2016-02-10 03:12:18 +01:00
Lee Leahy d4edacb2e4 soc/intel/quark: Call FSP SiliconInit
Optionally relocate FSP into DRAM and then call FSP SiliconInit.

Testing on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file
   *  Add "select ADD_FSP_PDAT_FILE"
   *  Add "select ADD_FSP_RAW_BIN"
   *  Add "select ADD_RMU_FILE"
   *  Add "select DISPLAY_FSP_ENTRY_POINTS"
   *  Add "select DISPLAY_HOBS"
   *  Optionally add "select RELOCATE_FSP_INTO_DRAM"
*  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
*  Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
*  Testing is successful if:
   *  FSP entry points are displayed and
   *  The message "FspSiliconInit returned 0x00000000" is displayed and
   *  The HOBs are displayed correctly and
   *  The message "ERROR - Missing one or more required FSP HOBs!" is
not displayed

Change-Id: I91e660ea373a8bb00fc97fe8b760347cbfa96b1e
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13631
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-10 03:12:10 +01:00
Lee Leahy 43cdff6b45 soc/intel/quark: MTRR support
Add the SoC specific routines to access the MTRR registers.  These
registers exist in the host bridge and are not accessible via the
rdmsr/wrmsr instructions.

Testing on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file
   *  Add "select ADD_FSP_PDAT_FILE"
   *  Add "select ADD_FSP_RAW_BIN"
   *  Add "select ADD_RMU_FILE"
   *  Add "select DISPLAY_MTRRS"
*  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
*  Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
*  Testing is successful if:
   *  The message "FSP TempRamInit successful" is displayed

Change-Id: I7c124145429ae1d1365a6222a68853edbef4ff69
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13530
Tested-by: build bot (Jenkins)
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2016-02-10 03:11:45 +01:00
Ben Gardner 3968653f25 soc/fsp_baytrail: Add support for FSP MR 005
Baytrail FSP MR 005 adds two new fields:
  AutoSelfRefreshEnable
  APTaskTimeoutCnt

Add the device tree definitions.

Change-Id: I12e2a8b0b5cbeb6b7289cf91f65b25e73007a8de
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/12973
Tested-by: build bot (Jenkins)
Reviewed-by: York Yang <york.yang@intel.com>
2016-02-10 02:45:56 +01:00
Lee Leahy 318ef96af3 soc/intel/quark: FSP MemoryInit Support
Add a dummy fill_power_state routine so that execution is able to reach
FSP MemoryInit.

Testing on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file
   *  Add "select ADD_FSP_PDAT_FILE"
   *  Add "select ADD_FSP_RAW_BIN"
   *  Add "select ADD_RMU_FILE"
   *  Add "select DISPLAY_HOBS"
   *  Add "select DISPLAY_UPD_DATA"
*  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
*  Place the pdat.bin files in the location specified by
    CONFIG_FSP_PDAT_FILE
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
*  Testing is successful if:
   *  MemoryInit returns 0 (success) and
   *  The the message "ERROR - Coreboot's requirements not met by FSP
binary!" is not displayed

Change-Id: I2a116e1e769ac09915638aa9e5d7c58a4aac3cce
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13447
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-10 02:42:21 +01:00
Vladimir Serbinenko c285b30b7d ASL: Remove unused modulo recipient.
Change-Id: I4b0a3073815ec8d98c2d23cd745f027517b6fa42
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13619
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09 22:56:00 +01:00
Vladimir Serbinenko 93fc60621c stout: Add native gfx init
Tested during FOSDEM.

Change-Id: Id095364d6e4735256e54a68ea9ae677355dd386a
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13532
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09 22:35:23 +01:00
Vladimir Serbinenko b2eea81992 sandybridge: Set all native gfx-related options in northbridge code.
In the same time remove few native gfx options which were improperly set
and only added dead code to the binary.

Change-Id: I4ed3fec03a1655ae0a779c3aa3845de273cb12e1
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13649
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2016-02-09 22:35:09 +01:00
Patrick Georgi 42636a7a0c rockchip/rk3288: UART uses 32bit wide registers
Change-Id: I084eb4694a2aa8f66afc1f3148480608ac3ff02b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13635
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-09 21:53:22 +01:00
Patrick Georgi eda794d2cc vboot2: Store depthcharge graphic assets only in RO
These files aren't updated (or updatable), and as such don't need to be
copied to the RW sections.

Change-Id: Ie78936792ad651fbf8500fc7e34f0899e33a904c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13633
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-09 21:52:05 +01:00
Vladimir Serbinenko 609bd9445e ivy: Add a possiblity for mainboard early init.
This is needed for stout EC init.

Change-Id: I5c73499c17763229840152a473a2d820802ee2f6
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13535
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09 20:35:40 +01:00
Paul Menzel bf725b48f7 superio/nuvoton/nct5572d: Add PS/2 presence detect
On certain Super I/O devices, when a PS/2 mouse is not present on the
auxiliary channel both channels will cease to function if the
auxiliary channel is probed while the primary channel is active.
Therefore, knowledge of mouse presence must be gathered by coreboot
during early boot, and used to enable or disable the auxiliary PS/2
port before control is passed to the operating system.

This is added in commit 448e3863 (drivers/pc80: Add PS/2 mouse
presence detect).

Update the Nuvoton NCT5572D driver to flag the auxiliary channel as
disabled if no device was detected. The code is copied from the Winbond
W83667HG-A driver.

Note, the ACPI changes are not part of this commit.

TEST=Currently, on the ASRock E350M1, PS/2 does not work. With this
change, a PS/2 keyboard works fine in SeaBIOS, GRUB in MBR, and Debian
GNU/Linux Sid/unstable with Linux 3.19.

```
[    1.185195] i8042: PNP: No PS/2 controller found. Probing ports directly.
[    1.189110] serio: i8042 KBD port at 0x60,0x64 irq 1
[    1.189133] serio: i8042 AUX port at 0x60,0x64 irq 12
[    1.189970] mousedev: PS/2 mouse device common for all mice
```

Change-Id: I7f9be348d295e70437bef089d4c2173169f38459
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/13618
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09 20:34:15 +01:00
Martin Roth 21c0650fdd Kconfig: Move payloads section to payloads/Kconfig
Move the payloads section of the kconfig tree out of the top level
kconfig file and into a separate Kconfig just for payloads before
it starts to get added to.

Change-Id: I4f52818f862bf1aeba538c1c6ed93211a78b9853
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13608
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-09 20:31:52 +01:00
Patrick Georgi c3686b3d02 chromebooks: Configure Chrome EC board names
For devices with Chrome EC, state the "board" name(s), so they're built
as part of the image.

A number of EC boards aren't supported in the Chrome EC master branch,
they're brought along but commented out, waiting for a port to master
in the Chrome EC code base.

Change-Id: Ic6ab821de55cf9b4e8b48fe5ebc603adeb8bb28b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13548
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-09 20:06:15 +01:00
Nico Huber 2dc15e9ea8 Revert "northbridge/intel/peg: Disable unused ports"
This reverts commit 0e06f5bd70.

It breaks gm45 and also does some magic without being asked too. It
disables bridge devices permanently if no device was found on the se-
condary bus. In a simple notebook world this might be ok, but it breaks
hot-plugging and late detection (if a secondary bus device comes up too
slow for the firmware to detect and the OS has to enumerate it).

Change-Id: Ia2010640d7c55b0bdd44164b81c75dd4be50410b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/13609
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2016-02-09 20:02:36 +01:00
Vladimir Serbinenko b27c24f69b Workaround for unused variable warning.
Change-Id: I0a0c925509027f98f724d0a4347146f21ac06c02
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13624
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09 19:58:14 +01:00
Vladimir Serbinenko bb7dbcdf30 ASL: Use temporary variable when storing register into itself.
Otherwise it triggers a IASL warning with new IASL.

Change-Id: I090ee18df78ea779137ee6797c55b96ea27e6d27
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13623
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09 19:57:57 +01:00
Vladimir Serbinenko 01586063ab ASL: Fix HPBA shadowing.
Store (HPBA, HPBA) had no effect. Rename one of HPBA to avoid shadowing.

Change-Id: I54bfa7bcb3e05c28fe8a257825af56527dbf663e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13622
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09 19:57:41 +01:00
Vladimir Serbinenko 764bd9789d rx886ex: Fix PBIF reference.
PBIF is package and so a scalar can't be stored instead of it.
What was meant is probably Index(PBIF, 0)

Change-Id: Iddd18e1f165e0f48fd91124200aba5c6b4a5b4bd
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13621
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09 19:57:17 +01:00
Vladimir Serbinenko ec730396cc ASL: Remove unused local variables.
Change-Id: Ifcbb6916b718d41fb9cda537ffdc3e652e13cbbf
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13620
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09 19:56:59 +01:00
Vladimir Serbinenko d200e0e7fb stout: Fix ASL warnings
Change-Id: I1ddf37aa61fe95ad632c35d8041aed02fb1e8c01
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13533
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09 19:54:53 +01:00
Christopher Spinrath 2bb16a5218 mainboard/lenovo: Add support for the Lenovo ThinkPad X220i
The ThinkPad X220i is essentially identical to the ThinkPad X220 but it
has a Sandybridge i3 (instead of a Sandybridge i5/i7) CPU and the
VGA_BIOS_ID differs. Thus, support is added by using the X220 mainboard
directory and setting the VGA_BIOS_ID in Kconfig.

Change-Id: I33345a099c617e8c87a1de64b7254b7e7716ca90
Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
Reviewed-on: https://review.coreboot.org/13594
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-02-09 19:47:17 +01:00
Pratik Prajapati 03be2383e7 intel/kunimitsu: Clean up GPIOs.
Some of the pins are not connected/used on kunimitsu board,
this patch will make them "Not connected".

Un-used PINS will controlled by GPIO controller (PMODE = GPIO) and
GPIO TX/RX will be disabled.

BRANCH=none
BUG=none
TEST=Build and booted in kunimitsu.

Change-Id: Iaf0d4806836648808fb91cfc7807c4c1595a5167
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a7c25ad8ee0d189178124cff20569152b1053488
Original-Change-Id: I3add625b2bf01223cd389c6a5585827ac62dd0c0
Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/316700
Original-Commit-Ready: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Tested-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/13629
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09 19:45:06 +01:00
david 4852dec1ab intel/skylake: Add gpio macro for unused GPIO pins
Unused PINS will be controlled by GPIO controller (PMODE = GPIO) and
GPIO TX/RX will be disabled.

BUG=none
BRANCH=none
TEST=Build and boot lars

Change-Id: I3a6fcd2f3462e8e0d1273aa80b1599b76b160825
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 889bfd66dbc918e9fb0ba1b95b63fd7a3bf180d9
Original-Change-Id: I3bf4aa8599255e5382d99810b4c83b4c97c648b6
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/319964
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/13628
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09 19:44:57 +01:00
Patrick Georgi e995dad2e1 build system: Build Chrome EC firmware on request
With the Chrome EC's "board" name set in Kconfig, the build system will
build and add the EC firmware, too. Available for the EC and the USB
PD controller.

Change-Id: I017d3a44d6ab8a540fcd198b4b09c35e4b98a8cf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13547
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09 18:34:28 +01:00
Damien Zammit 08ec1ae2c2 mb/intel/d510mo: Explicitly select NIC on PCI in devicetree
While the board configuration still works without this,
It's nicer to have the device statically defined since
the NIC is hardwired to the board.

Change-Id: Ic6682865dd17672c3782bfba9511cd120d1657c1
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13455
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09 18:22:33 +01:00
Lee Leahy f2ad50feda console: Disable SQUELCH_EARLY_SMP if SMP is not selected
Add a "depends on SMP" to the value SQUELCH_EARLY_SMP Kconfig value to
disable its selection when SMP is not enabled.

TEST=Build for Galileo

Change-Id: Ia3aa1d2169ed793e1bb26538b74b12347453d5af
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13639
Tested-by: build bot (Jenkins)
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09 17:14:50 +01:00
Lee Leahy 87df8d08d6 soc/intel/quark: Enable Serial Port
Add the code to enable debug serial output using HSUART1:

*  Enable the code using Kconfig value ENABLE_BUILTIN_HSUART1
*  Note that the BIST value is always zero as validated in
   esram_init.inc
*  The initial TSC value is currently not saved!

Testing on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file
   *  Add "select ADD_FSP_PDAT_FILE"
   *  Add "select ADD_FSP_RAW_BIN"
   *  Add "select ADD_RMU_FILE"
*  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
*  Place the pdat.bin files in the location specified by
   CONFIG_FSP_PDAT_FILE
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
*  Testing is successful if serial output is present on HSUART1 at
   115200 baud, 8-bit, no parity

Change-Id: I7e6181e8b9bc901c3ab236f0b56534850bb6bfd0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13445
Tested-by: build bot (Jenkins)
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2016-02-09 16:20:38 +01:00
david 5d7df71cfe google/lars: Set I2C[4] port voltage to 1.8v
As the audio card needs 1.8V I2C operation. This patch adds
entry into devicetree.cb to set I2C port 4 operate at 1.8V.

TEST=Built & booted lars board. Verified that I2C
port 4 is operating at 1.8V level

Change-Id: Ia77841a26d024785d53251ca4b17afcf77f36a5b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e431e7acd85f6d7bf9d47f54ed41c48b8276071c
Original-Change-Id: Iccc85a5e3bbf2b5362665036e1294a6635e38fbe
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/321000
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13627
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09 14:07:21 +01:00
Duncan Laurie 825f937b81 skylake mainboards: Enable backing up VBNV from CMOS to flash
Enable the option to back up Vboot non-volatile data from CMOS
to flash as these boards have the necessary nvram fmap region
and are using vboot2 which does not backup to the TPM.

BUG=chrome-os-partner:47915
BRANCH=glados
TEST=manually tested on chell

Change-Id: I7bfe88f2cb7826f3315987aaf56f77df708896ce
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 35df03c5ef24406129cba920ee9af6d55458cd45
Original-Change-Id: Ia7c014fe2768c55941a65ec5605ef4fbc986151c
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/324123
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13601
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09 14:03:23 +01:00
Duncan Laurie fe97013454 chromeos: Add option to back up VBNV CMOS into flash
This adds a new kconfig option that will back up the VBNV data
from CMOS to flash, and restore it if the CMOS data is invalid
during boot.

This allows special flags to not get lost when power is lost,
RTC reset is triggered, or CMOS is corrupted.

BUG=chrome-os-partner:47915
BRANCH=glados
TEST=manually tested on chell:
1-boot and run "enable_dev_usb_boot"
2-reboot and check that it is enabled with crossystem
3-run "mosys nvram clear"
4-reboot and check that it is still enabled

Change-Id: I38103d100117da34471734a6dd31eb7058735c12
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8a356e616c6885d5ae3b776691929675d48a28f9
Original-Change-Id: I06e7ddff7b272e579c704914a0cf8cc14d6994e8
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/324122
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13600
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09 14:03:12 +01:00
Alexandru M Stan 70cada2de0 google/veyron_rialto: Remove developer mode switch
The developer mode gpio switch on rialto is always hardcoded (through a
resistor) as developer mode. We need to ignore it to allow transitions to
verified mode with the virtual developer mode stuff.

TEST=We can now exit dev mode on rialto

Change-Id: I94a949f0973132de5fd008224af79cf612151193
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e78bb8f81eaa9c082e47ad818b64843c2565d00b
Original-Change-Id: If11d752d58a5f26fc270ef01b529dad18b4cce46
Original-Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/325861
Original-Commit-Ready: Alexandru Stan <amstan@chromium.org>
Original-Tested-by: Alexandru Stan <amstan@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13626
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09 13:39:52 +01:00
Aaron Durbin d87cc3f24e google/chromeos/vboot2: defer clearing rec mode switch
Certain platforms query the recovery mode switch more than just within
vboot during the boot flow. Therefore, it's important that the first call to
get_recovery_mode_switch() is consistent through memory training because
certain platforms use the recovery mode switch to take different action
for memory training. Therefore, defer the clearing of the rec mode
switch to a place when it's known that memory is up and online.

BUG=chrome-os-partner:44827
BRANCH=glados
TEST=Three finger salute is honored on chell by retraining memory.

Change-Id: I26ea51de7ffa2fe75b9ef1401fe92f9aec2b4567
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6b0de9369242e50c7ff3b164cf1ced0642c7b087
Original-Change-Id: Ia7709c7346d1222e314bf3ac7e4335a63e9a5144
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/325120
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13604
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09 13:22:59 +01:00
Fang, Yang A 8a0d274444 intel/kunimitisu: set oem_id oem_table_id fields of acpi_header_t
kunimitisu platform updated these two fields if maxim codec
is detected.

BUG=chrome-os-partner:49570
BRANCH=glados
TEST=Build & Booted kunimitsu board. Verified that kernel
can read new strings.

Change-Id: Icbe0d87f0b46da794db36191b0e12948fe6a2fe6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f3d07ef07c382a2df140b457273feb3899228e10
Original-Change-Id: Ia6a111d15b851ae3fa918816e13b54ace215a09a
Original-Signed-off-by: Fang, Yang A <yang.a.fang@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/324631
Original-Commit-Ready: Yang Fang <yang.a.fang@intel.com>
Original-Tested-by: Yang Fang <yang.a.fang@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13603
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09 13:21:57 +01:00
Fang, Yang A 16ff85971f nhlt: add api to override oem_id and oem_table_id of acpi_header_t
This patch added nhlt_soc_serialize_oem_overrides and
nhlt_serilalize_oem_overrides to be able to override oem_id and
oem_table_id.board file can pass specific string by calling
nhlt_soc_serialize_oem_overrides

kernel use these two fields to construct a topology binary name
if the designate file is not found a default dfw_sst.bin will be used
it is optional.

BUG=chrome-os-partner:49570
BRANCH=glados
TEST=Build & Booted kunimitsu board. Verified that kernel
can read new strings.

Change-Id: I00b64fb8bb63de601d3116e0b8941057c1efa230
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 374ce08b2d8a2f4e5dd7f51eacb505dbb77fd171
Original-Change-Id: I03623c8ac81efb5a5ea3ec9c6cd604d2e9294022
Original-Signed-off-by: Fang, Yang A <yang.a.fang@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/322860
Original-Commit-Ready: Yang Fang <yang.a.fang@intel.com>
Original-Tested-by: Yang Fang <yang.a.fang@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13602
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09 13:21:39 +01:00
Duncan Laurie 0165038561 chromeos: Make vbnv_flash driver safe for CAR usage
This modifies the vbnv_flash driver to make it safe for use
in cache-as-ram by handling the global variables safely.

To make this cleaner all of the variables were moved into
one structure and referenced from there.

BUG=chrome-os-partner:47915
BRANCH=glados
TEST=build and boot on chell using following patches to
test backup and restore of vbnv_cmos into flash

Change-Id: I3a17fa51cfd754455502ac2e5f181dae35967f2a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 48876561fa4fb61e1ec8f92596c5610d97135201
Original-Change-Id: Id9fda8467edcc55e5ed760ddab197ab97d1f3d25
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/324121
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13599
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09 13:20:41 +01:00
Duncan Laurie 3cbf8d955f chromeos: Remove CONFIG_VBNV_SIZE variable
The VBNV region size is determined by vboot and is not really
configurable.  Only the CMOS implementation defined this config
variable so switch it to use VBNV_BLOCK_SIZE defined by vboot
in vbnv_layout.h instead.

This requires updating the broadwell/skylake cmos reset functions
to use the right constant.

BUG=chrome-os-partner:47915
BRANCH=glados
TEST=manually tested on chell

Change-Id: I45e3efc2a22efcb1470bbbefbdae4eda33fc6c96
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e2b803ff3ac30ab22d65d1e62aca623730999a1d
Original-Change-Id: I4896a1a5b7889d77ad00c4c8f285d184c4218e17
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/324520
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13598
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09 13:19:48 +01:00
Duncan Laurie 88b28ada69 chromeos: Add vbnv wrapper for the different backends
Add a wrapper around the vbnv implementations and call into the different
backend functions from there.  Also move some of the common functions to
the common code and simplify the backend drivers.  This will allow some
of the code to be re-used so the CMOS backend can backup the data into
the flash backend.

One side effect of this is that the cache of VBNV was removed from CMOS
and EC backends and moved into the VBNV wrapper, but the flash backend
also still has a separate cache because it has more state and complexity
in the implementation.  The wrapper cached data is not used for normal
vbnv_read/vbnv_write because some callers need the ability to force a
write if the backend storage is cleared (i.e. CMOS clear).

BUG=chrome-os-partner:47915
BRANCH=glados
TEST=build and boot on chell

Change-Id: I4d2e0e99af7e8a44aec77ad9991507401babcca6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c30f60434a64f6c0eb9ede45d48ddafff19dd24f
Original-Change-Id: Ia97f6607c5ad837b9aa10b45211137221ccb93a0
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/324120
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13597
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09 13:19:36 +01:00
Lee Leahy a7ba56e3ce soc/intel/quark: Add TempRamInit support
Successfully invoke TempRamInit from the FSP binary:
*  Don't relocate the FSP binary image
*  Copy the FSP binary into ESRAM
*  Specify Kconfig values to easily debug ESRAM and TempRamInit code
*  Specify the FSP binary file location
*  Specify the FSP binary image ID
*  Specify where in the flash image the FSP image must reside
*  Specify the FSP data file location
*  Specify where to place the FSP data file in the flash image
*  Specify where in the ESRAM the FSP image must reside

Test 1 on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file
   *  Add "select ADD_FSP_PDAT_FILE"
   *  Add "select ADD_FSP_RAW_BIN"
   *  Add "select ADD_RMU_FILE"
   *  Add "select ENABLE_DEBUG_LED_FINDFSP"
*  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
*  Testing is successful if the SD LED is on indicating that the FSP.bin
file was properly located,  The test fails if the SD LED is flashing.

Test 2 on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file
   *  Remove "select ENABLE_DEBUG_LED_FINDFSP"
   *  Add "select ENABLE_DEBUG_LED_TEMPRAMINIT"
*  Testing is successful if the SD LED is on indicating that the FSP.bin
   file was properly located,  The test fails if the SD LED is flashing.

Change-Id: I1e2e413a8573f750c611b0f9df101b2c869a789e
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13443
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-02-08 20:36:15 +01:00
Lee Leahy 9fd0895cb4 soc/intel/quark: Enable ESRAM
The Quark SoC uses ESRAM instead of cache-as-RAM.  This code requires
that utils/xcompile/xcompile change the machine architecture from i686
to i586 to ensure that the Quark does not attempt to execute unsupported
instructions:

*  Adjust Makefile.inc to add the RMU to the coreboot image
*  Add code to enable the ESRAM

Directly use the QuarkSocPkg/QuarkNorthCluster/Include/QuarkNcSocId.h
file from the EDK2 tree (https://github.com/tianocore/edk2.git) to
enable
easy differences and correct issues in coreboot that were found in EDK2.

Testing on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file
   *  Add "select ADD_RMU_FILE"
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
*  Remove power from the board
*  Apply power to the board
*  Testing is successful if the SD LED is on indicating that the end of
   esram_init.inc was reached

Change-Id: I91d919da144bb72a5d4c4a8050ffab256632a395
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13440
Tested-by: build bot (Jenkins)
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-08 20:15:05 +01:00
Lee Leahy cff5f09e93 drivers/intel/fsp1_1: Make fsp_run_silicon_init public
Remove the "static" declaration from fsp_run_silicon_init and declare
the routine in ramstage.h.  This routine can be called directly when FSP
is already in RAM.

TEST=Build and run on Galileo

Change-Id: Iddb32d00c5d4447eab5c95b0ad5c40309afa293e
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13630
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-08 18:53:45 +01:00
Lee Leahy c71a3db33f mainboard/intel/galileo: Add board_info.txt
Add missing file to fix complaints by git commit script.

TEST=None

Change-Id: I4aac63821a7208fb86fa6c0dda16b7537e49a69a
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13610
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-05 23:02:57 +01:00
Timothy Pearson b251a50714 mainboard/asus/kcma-d8: Add initial ASUS KCMA-D8 support
Change-Id: Idefa304a27823c741fab72ff5c2f20fed1aa5a39
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13523
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-05 22:30:57 +01:00
Timothy Pearson 4551b68c83 mainboard/asus/kcma-d8: Copy ASUS KGPE-D16 for initial support work
Also updated KGPE-D16 strings to KCMA-D8 throughout the copy to work
around Jenkins failures caused by an unmodified clone.

Change-Id: I943e81c8c2987a8333fc2a1cdb3675abf2d90cf1
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13521
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-05 22:28:38 +01:00
Timothy Pearson f098a7310a mainboard/asus/kgpe-d16: Add CPB control CMOS option
Change-Id: I28ad2298ad4dfb428dcd41a4f00db88c5e817cd7
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13173
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2016-02-05 22:27:56 +01:00
Timothy Pearson 4e543d3915 cpu/amd/fam10h-fam15h: Honor CMOS option to disable CPB (core boost)
On certain systems and CPUs Core Performance Boost (CPB) may cause
sporadic system lockups.  This issue is also somewhat known on the
various proprietary BIOSes, therefore it seems to be a hardware
incompatibility when present.

Allow the user to disable CBP if needed.

Change-Id: Id6395d067d48963f6c084ad0bf79e23419af24d8
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13172
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2016-02-05 22:27:31 +01:00
Timothy Pearson fec8872c9d nb/amd/mct_ddr3: Fix RDIMM training failure on Fam15h
Certain registered DIMMs failed training due to an error
likely introduced during historical rebase.  Ensure that
the SubMemclkRegDly bit is set according to BKDG
recommendations on Family 15 processors.

Change-Id: I24c95265dada9eabf4df280b6f2b4a1eb9cecaf1
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13148
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-05 22:26:54 +01:00
Timothy Pearson 31682364ba nb/amd/mct_ddr3: Work around RDIMM training failure
Under certain conditions, not elucidated in the BKDG,
an extra memclock of CAS write latency is required.

The only reliable way I have found to detect when this
is required is to try training without the delay, and
if DQS position training fails, adding the delay and
retraining.

This is probably related in some form or another to
the badly broken DQS Write Early algorithm given
in the BKDG.

Change-Id: Idfaca1b3da3f45793d210980e952ccdfc9ba1410
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13531
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-05 22:26:31 +01:00
Timothy Pearson 606b6ec686 cpu/amd/fam10h-15h: Set PowerStepUp/PowerStepDown on Fam15h
Multilink Family 15h processors were being configured with an
incorrect PowerStepUp/PowerStepDown value.  Set the value
according to the BKDG, and clean up the terrible formatting
of the power_up_down() function that led to the incorrect
values being overlooked until now.

Also change u32 declarations to uint32_t in modified functions.

Change-Id: I16e1f5205d6b5f349a3e7167dea04c9eefda4684
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13174
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-05 22:24:38 +01:00
Timothy Pearson 7acb56fa97 mainboard/asus/kgpe-d16: Update power LED handling
- Stop blinking when coming out of standby.
- Remove code to set blink when going into S3. This never
worked correctly.

Change-Id: I958990f3203d3cbe7ae64833800d631c1034327f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13171
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-05 22:24:23 +01:00
Lee Leahy 93dd5f78ff mainboard/intel/galileo: Add Intel Galileo Gen 2 Support
Add the files to build soc/intel/quark and mainboard/intel/galileo for a
minimal coreboot image.  Please note that this configuration does not
run.  Include HTML documentation for the Galileo Gen 2 board.

Testing is successful if build completes successfully.

TEST=Build for Galileo

Change-Id: Idd3fda1b8ed9460fa8c92e6dcaa601c3c9f63a36
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13507
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-04 19:20:06 +01:00
Archana Patni 4af905ac95 skylake boards: disable ACPI PM Timer
These devicetree patches set the ACPI PM Disabled variable to 1.
This will disable the ACPI PM timer and remove from FADT table.

BRANCH=none
BUG=chrome-os-partner:48646
TEST=Build for skylake board with the PmTimerDisabled policy in
devicetree set to 1.
iotools mmio_read32 0xfe0000fc should return 0x2.
cat /sys/devices/system/clocksource/clocksource0/available_clocksource
should list only "tsc hpet". acpi_pm should be removed from this list.

Change-Id: Ia66f37e13f0f2f527651418b8b5c337b56c25c7f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: db3e8130495038850c7034b89701b4a5fcf88dce
Original-Change-Id: Ib1b876cfa361b8cbdde2f9e212e3da4fd724e498
Original-Signed-off-by: Archana Patni <archana.patni@intel.com>
Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/319362
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13589
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04 17:44:50 +01:00
Archana Patni 6c1bf27dae intel/skylake: disable ACPI PM Timer to enable XTAL OSC shutdown
Keeping ACPI PM timer alive prevents XTAL OSC shutdown in S0ix
which has a power impact.

Based on a DT variable, this patch disables the ACPI PM timer
late in the boot sequence - disabling earlier will lead to a hang
since the FSP boot flow needs this timer. This also hides the ACPI PM
timer from the OS by removing from FADT table. Once the ACPI PM timer
is disabled, TCO gets switched off as well.

BRANCH=none
BUG=chrome-os-partner:48646
TEST=Build for skylake board with the PmTimerDisabled policy in
devicetree set to 1.
iotools mmio_read32 0xfe0000fc should return 0x2.
cat /sys/devices/system/clocksource/clocksource0/available_clocksource
should list only "tsc hpet". acpi_pm should be removed from this list.

Change-Id: Icfdc51bc33b5190a55196d67e18afdaaa2f9b310
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 18bcb8a434b029295e1f1cc925e2b47e79254583
Original-Change-Id: Ifebe8bb5a7978339e07e4e12e174b9b978135467
Original-Signed-off-by: Archana Patni <archana.patni@intel.com>
Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/319361
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13588
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04 17:44:28 +01:00
Aaron Durbin 50c3ba24d4 intel/skylake: unconditionally set SPI controller BAR
The setting of the SPI controller BAR was conditional
on the nominal frequency being set. Therefore, that doesn't
mean the SPI BAR is set on all boots. Move the setting of
the BAR in the southbridge_bootblock_init() which is called
prioer to cpu_bootblock_init().

BUG=chrome-os-partner:44827
BRANCH=None
TEST=Confirmed spibar is always set on glados.

Change-Id: Ia58447d70f5e39a4336d4d08593f143332de833a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 56fff7c25c2eb0ccd90e08f71c064b83c66640f8
Original-Change-Id: I1e0cff783f4b072b80589a3a84703a262b86be3a
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/319461
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13587
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04 17:43:49 +01:00
Aaron Durbin 4121f9e555 google/chromeos/vboot2: honor boot region device size
Vboot keeps track of the size of the hashed region in each
RW slot. While that size was being used to calculate the hash
it wasn't being honored in restricting the access within the
FMAP region for that RW slot. To alleviate that create a sub
region that covers the hashed data for the region in which
we boot from while performing CBFS accesses.

BUG=chrome-os-partner:49764
BUG=chromium:445938
BRANCH=glados
TEST=Built and booted chell with cbfstool and dev-util patches.

Change-Id: I1a4f45573a6eb8d53a63bc4b2453592664c4f78b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4ac9e84af5b632e5735736d505bb2ca6dba4ce28
Original-Change-Id: Idca946926f5cfd2c87c4a740ad2108010b6b6973
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/324093
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13586
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04 17:42:54 +01:00
Aaron Durbin f52fb2f750 google/lars: perform early init for CAR *stage
In order to support both separate verstage and a verified boot after
romstage one needs to ensure the proper GPIO and EC configuration
been complete. Therefore, move that logic to
car_mainboard_post_console_init() in car.c file which gets called
in the early flow of a CAR stage (either verstage or romstage).

BUG=chrome-os-partner:44827
BRANCH=glados
TEST=None

Change-Id: I331f25ad4764cab972af7198f6154f604d2dbeae
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2c1cb04645cbf34696e6adf48acec9d396e87ca9
Original-Change-Id: I8d14ea16b2d07bbf04c5c33e4205a85d9f21847b
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/324075
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13585
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04 17:42:20 +01:00
Aaron Durbin 0f9d5c454b intel/kunimitsu: perform early init for CAR *stage
In order to support both separate verstage and a verified boot after
romstage one needs to ensure the proper GPIO and EC configuration
been complete. Therefore, move that logic to
car_mainboard_post_console_init() in car.c file which gets called
in the early flow of a CAR stage (either verstage or romstage).

BUG=chrome-os-partner:44827
BRANCH=glados
TEST=Built kunimitsu w/ separate verstage.

Change-Id: If34cae5516a6df7f72f1f57cab495db70787177e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 543155665e1b05efe82c7440c124a5c83c656aa6
Original-Change-Id: I7281c4373fcbaaf0beedaa63dcf0dedb5316349f
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/324074
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13584
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04 17:41:16 +01:00
Aaron Durbin 586a517dfd google/glados: perform early init for CAR *stage
In order to support both separate verstage and a verified boot after
romstage one needs to ensure the proper GPIO and EC configuration
been complete. Therefore, move that logic to
car_mainboard_post_console_init() in car.c file which gets called
in the early flow of a CAR stage (either verstage or romstage).

BUG=chrome-os-partner:44827
BRANCH=glados
TEST=Built glados w/ separate verstage and booted.

Change-Id: I626a500c183d21f94d976e24f09af15a242fba9c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b564514a8b93f53a919fcdac3589e30dbac82124
Original-Change-Id: Icc989ec5700b3f1a144a6b41198b7dd2c2aac6f7
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/324073
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13583
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04 17:40:59 +01:00
Aaron Durbin 849e4f5e78 google/chell: perform early init for CAR *stage
In order to support both separate verstage and a verified boot after
romstage one needs to ensure the proper GPIO and EC configuration
been complete. Therefore, move that logic to
car_mainboard_post_console_init() in car.c file which gets called
in the early flow of a CAR stage (either verstage or romstage).

BUG=chrome-os-partner:44827
BRANCH=glados
TEST=Built chell w/ separate verstage and booted.

Change-Id: Ic728c2904006376fdc2b27b512f72173a2260be3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 42d190af8996fea894305ebe686afbfda5f2b8a5
Original-Change-Id: I95aeb97737d0ddfa6c53269c9d14db16ed5e47cc
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/324072
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13582
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04 17:40:44 +01:00
Aaron Durbin 5e29106ee4 google/chromeos: guard cbmem_find() in verstage and bootblock
When vboot_handoff_flag() is called in the bootblock or a separate
verstage there's no memory nor the possibility of dram coming online.
Therefore, don't bother to attempt call cbmem_find().

BUG=chrome-os-partner:44827
BRANCH=glados
TEST=Built chell with separate verstage which pulls in vboot_common.c
     dependency. No more linking errors w/ cbmem_find() not being
     around.

Change-Id: I494c93adc1c00459fdfaa8ce535c6b4c884ed0fb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 414ce6aeaff657dc90289b25e5c883562189b154
Original-Change-Id: I8a5f2d154026ce794a70e7ec38883fa3c28fb6e7
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/324070
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13580
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-04 17:40:29 +01:00
Aaron Durbin 7bc39a0983 lib: add bootmode.c to verstage
Some of the functions within bootmode.c may be required
by boards in verstage. Therefore, allow this file to be built
in verstage.

BUG=chrome-os-partner:44827
BRANCH=glados
TEST=Built chell w/ bootmode.c dependencies in separate verstage.

Change-Id: Id291c1b5cc6594c3ee16c7c3385e682addc0efb6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 084b620e12e7f948087786c0e34d5999a73137a5
Original-Change-Id: I2207819ec1490767cb1cf4b92e34e714783c1c22
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/324071
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13581
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04 17:36:07 +01:00
Aaron Durbin cbc3c378dc intel/skylake: implement vboot_platform_prepare_reboot()
In order to not reboot loop in the face of failed vboot verification
on resume set the PM1 control register to indicate S5. After the
subsequent cold reset the PM1 control register will indicate S5
as it should.

BUG=chrome-os-partner:46049
BRANCH=glados
TEST=On chell injected failed vboot verification. Ensured a reboot
     loop doesn't ensue.

Change-Id: Ie5e9e3f6441a217a5e02b4d78aaf21f8249b8a43
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a63b57d7bc59bcaf5518f7cc4afccd3d5da6df1c
Original-Change-Id: I5e467854bf065a138bd46e476a7e7088f51454ca
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/323504
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13579
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04 17:35:28 +01:00
Aaron Durbin a1faa4cfc7 intel/skylake: implement vboot_platform_is_resuming()
To allow skylake platforms to run with verified memory init
code the chipset needs to implement vboot_platform_is_resuming()
so that the vboot code can make proper decisions.

BUG=chrome-os-partner:46049
BRANCH=glados
TEST=Suspended and resumed on chell. Also, tested with an EC build
     which returns a bad hash to ensure that is properly caught.

Change-Id: I508a339c07dcc9e7c56a0df4201660827b3ae07a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a3e11789339bcd8fc8fc99b704c6a1110acf5302
Original-Change-Id: I40264019eb28e85795258112c720056a6a3fc523
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/323503
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13578
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04 17:35:16 +01:00
Aaron Durbin 49b2383ddb google/chromeec: implement vboot_(save|retrieve)_hash API
For x86 systems which resume through the reset vector one needs to
ensure the the RW slot taken at resume time matches the one at
boot time. To that end, allow Chrome OS EC to supply the plumbing
to vboot for storing and retrieving the RW slots' hash digest
using the vstore backend.

BUG=chrome-os-partner:46049
BRANCH=glados
TEST=Suspended and resumed on chell. Also, tested with an EC build
     which returns a bad hash to ensure that is properly caught.

Change-Id: Ib056f7e6b3386447ed1ff95c740ef5b4544f9049
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9c78546b1d6298a4c397a587c564df6d9d097e75
Original-Change-Id: I86c96a4092deab2dfa51b3043b9dba16b6a4c201
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/323502
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13577
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04 17:34:58 +01:00
Aaron Durbin 5dbefd9ff6 chromeos/vboot: allow platform to hook into vboot_reboot()
Sometimes it's necessary for the platform to perform clean up
tasks prior to reboot when employing vboot. For example, x86 systems
that resume and do vboot verification may need to clear their
sleep control register prior to doing a cold reset so that the
next boot doesn't appear to be a resume. Allow that hook by
introducing vboot_platform_prepare_reboot().

BUG=chrome-os-partner:46049
BRANCH=glados
TEST=Ensure vboot_platform_prepare_reboot() called from vboot_reboot().

Change-Id: I622c9181d9fa3048204e3df3223d5dd4b458abca
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f31ffc40bde002dec398fd4dd9d2ee9d65df0d7b
Original-Change-Id: I97318cec34494a7fc4b1ecf2cb22715d20e730ff
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/323501
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13575
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04 17:34:15 +01:00
Aaron Durbin 87c9faeb4c chromeos/vboot: provide support for x86 memory init verification
For x86 systems which resume through the reset vector one needs to
ensure the the RW slot taken at resume time matches the one at
boot time. The reason is that any assets pulled out of the boot
media need to match how the platform previously booted. To do
that one needs obtain the hash digest of the chosen slot, and it
needs to be saved in a secure place on the normal boot path. On
resume one needs to retrieve the hash digest back to compare it
with the chosen slot. If they don't match resuming won't be
possible.

BUG=chrome-os-partner:46049
BRANCH=glados
TEST=Suspended and resumed on chell. Also, tested with an EC build
     which returns a bad hash to ensure that is properly caught.
CQ-DEPEND=CL:323460

Change-Id: I90ce26813b67f46913aa4026b42d9490a564bb6c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 01a42c0ecfc6d60d1d2e5e36a86781d91d5c47a9
Original-Change-Id: I6c6bdce7e06712bc06cc620a3d7a6a6250c59c95
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/323500
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13574
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04 17:34:00 +01:00
Dhaval Sharma 9dca83c762 intel/skylake: Display ME firmware status before os boot
Display ME firmware status before os boot. Specifically this
patch reads out the ME hfsts1 and hfsts2 status registers that provide
information about overall ME health before device gets disabled.
This change reused most of the code from bdw me_status implementation.

BUG=chrome-os-partner:47384
BRANCH=glados
TEST=Builds and Boots on FAB4 SKU2/3. Can observe me status table

Change-Id: Ia511c4f336d33a6f3b49a344bfbaea6ed227ffeb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a9d0fb411c3921654f0fdcea2a3d4ee601987af2
Original-Change-Id: Ied7e2dcd9a1298a38dfe1eda9296b9ca8eccf6b1
Original-Credits-to: Duncan Laurie <dlaurie@chromium.org>
Original-Signed-off-by: Dhaval Sharma <dhaval.v.sharma@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/323260
Original-Commit-Ready: dhaval v sharma <dhaval.v.sharma@intel.com>
Original-Tested-by: dhaval v sharma <dhaval.v.sharma@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13573
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04 17:30:11 +01:00
Duncan Laurie e2cea4f458 google/chromeec: Add temporary storage interface
Add support functions for the Chrome EC temporary storage interface.

BUG=chrome-os-partner:46049
BRANCH=none
TEST=tested on glados with modified coreboot

Change-Id: Id2bc46df9cb2d82b15e3309e78d07407a622b6f0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a7e6f693666b162e11eb0611715f10a8f465ad88
Original-Change-Id: Ieefabfc5bcb9d8a5064f0da967c46d0f377ca320
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/315217
Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13572
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04 17:21:04 +01:00
Duncan Laurie eb31685bbb google/chromeec: Update EC command header
Update to the latest EC command header.

BUG=chrome-os-partner:46049
BRANCH=none
TEST=emerge-glados coreboot

Change-Id: I132f91b31931ed40c20c0f5dbbf4449663768418
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5e6d9d51cfe99fe7c3806d1f74ea67b2d2ed5e7e
Original-Change-Id: I3c2e268689d64683f4a138e20f518e6eda49a138
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/315216
Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13571
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04 17:13:43 +01:00
Lee Leahy 2ed7eb795c soc/intel/quark: Add minimal Quark SoC X1000 files
Add the files for minimal Quark X1000 SoC support:

*  Declare pei_data structure
*  Declare sleep states and chipset_power_state structure
*  Specify top of memory
*  Empty FspUpdVpd.h file

TEST=None

Change-Id: If741f84904394780e1f29bd6ddbd81514c3e21c9
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13439
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-04 15:27:27 +01:00
Ruilin Hao de4defbaaf soc/marvell/armada38x: Add i2c driver for armada38x
Port i2c driver from uboot to coreboot

BUG=chrome-os-partner:47462
TEST=emerge-cyclone coreboot
BRANCH=tot

Change-Id: I8ce2a965acaed68ad0f0518648490ec471c6810b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4c2e9592662787ebed1d0aa8cafaa00fd12c2e9c
Original-Change-Id: If791228edf29405fa4b2f959a21510bd7da9865b
Original-Signed-off-by: Ruilin Hao <rlhao@marvell.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313342
Original-Commit-Ready: Kan Yan <kyan@google.com>
Original-Tested-by: Kan Yan <kyan@google.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/13113
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04 11:31:45 +01:00
Ruilin Hao c1b9e7934c soc/marvell/armada38x: Add gpio driver for armada38x
Port gpio driver from uboot to coreboot

BUG=chrome-os-partner:47462
TEST=None
BRANCH=tot

Change-Id: Ib6cfbb6e44cb642c7af937778076a51d405ff4a2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5cf94502faad96147d4a4adb42eb13edb64a6439
Original-Change-Id: Ia2e081a85347e2fc8bb365ca527ee2ee32af86f1
Original-Signed-off-by: Ruilin Hao <rlhao@marvell.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313341
Original-Commit-Ready: Kan Yan <kyan@google.com>
Original-Tested-by: Kan Yan <kyan@google.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Kan Yan <kyan@google.com>
Original-Reviewed-by: Yuji Sasaki <sasakiy@chromium.org>
Reviewed-on: https://review.coreboot.org/13112
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04 11:31:25 +01:00
Ruilin Hao 5b429ac2b2 soc/marvell/armada38x: Add spi driver for armada38x
Port spi driver from uboot to coreboot

BUG=chrome-os-partner:47462
TEST=None
BRANCH=tot

Change-Id: I747be7001f4cfb8eec33e8e5bdef3fe5bb0eb2ca
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9fbc5c2feb6ffacb54ed94e5c7b94b38be2b2ded
Original-Change-Id: Ibea9a050ac8bdab6ce4eeb07accde53aeadade5f
Original-Signed-off-by: Ruilin Hao <rlhao@marvell.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313340
Original-Commit-Ready: Kan Yan <kyan@google.com>
Original-Tested-by: Kan Yan <kyan@google.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Kan Yan <kyan@google.com>
Original-Reviewed-by: Yuji Sasaki <sasakiy@chromium.org>
Reviewed-on: https://review.coreboot.org/13111
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04 11:30:21 +01:00
Ruilin Hao 2c8b0b1373 soc/marvell/armada38x: Add generic support for armada38x
Skeleton for soc armada38x

BUG=chrome-os-partner:47462
TEST=None
BRANCH=tot

Change-Id: I76f631ee6cdfc90c44727cb20aa960796bc785a5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e91cc19468325f005c6ac920bbe27a174c409727
Original-Change-Id: Iac5fc34df1ba18b4515029aa2fcff8f78a5df191
Original-Signed-off-by: Ruilin Hao <rlhao@marvell.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313179
Original-Commit-Ready: Kan Yan <kyan@google.com>
Original-Tested-by: Kan Yan <kyan@google.com>
Original-Reviewed-by: Kan Yan <kyan@google.com>
Reviewed-on: https://review.coreboot.org/13110
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04 11:28:41 +01:00
Patrick Rudolph 0e06f5bd70 northbridge/intel/peg: Disable unused ports
Walk the bus and try to find enabled devices.
Disable the PEG port if no devices are attached.

Change-Id: I67fcc831fd78ecc6dba83f4e0662ec7549cc2591
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/12894
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-04 01:44:40 +01:00
Patrick Rudolph a1c3beddbb nb/intel/sandybridge/raminit: Fix two dimms per channel
Issue observed:
The system boots with 4G in channel 0 and 4G in channel 1.
The system doesn't boot with any combination of 4G + 1G in
channel 0 and 4G in channel 1.
In both cases DIMM1 failed, while DIMM0 showed no issues.

Problem description:
The CLK to CMD/CTL was off by a half clock cycle.
The find the issue I X-Y plotted timC vs timB for every
lane on the failing rank.
You can see an offset by 32 units for timB, that is not present on
other ranks.
It turns out that the XOVER CMD/XOVER CTL enable bit for DIMM1 was
missing in program_timings(), which caused the clock offset.

Problem solution:
Add two functions to calculate XOVER CMD and XOVER CTL and use both
to set XOVER in program_timings() and dram_xover().

Final testing result:
The system boots with 4G + 1G in channel 0 and 4G in channel 1.

Test system:
 * Intel IvyBridge
 * Gigabyte GA-B75M-D3H

Change-Id: I88694c86054ade77e9d8bb2f1fdaf7bc559c1218
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13415
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-04 01:44:10 +01:00
Lee Leahy a9ffa9e7f2 lib: Support UNCOMPRESSED_RAMSTAGE
Selecting UNCOMPRESSED_RAMSTAGE prevents lzma.c from being compiled for
romstage.  Adjust the logic in rmodule.c to prevent calls to the ulzma
routine when UNCOMPRESSED_RAMSTAGE is selected.

TEST=Build and run on Galileo

Change-Id: I7409e082baab3c2a086c57ad5aa9844ba788c7cd
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13591
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-02-03 22:17:07 +01:00
Patrick Georgi 71ea717f72 chromeos: Sign FW_MAIN_A and FW_MAIN_B
This requires payload integration somewhere to be useful, because
without that, adding it will (hopefully) break the signature.

Change-Id: I67b8267e5040e26353df02d258e92a0610e19a52
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13560
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-02-03 20:16:33 +01:00
Patrick Georgi 5ea87ff861 chromeos: Add Kconfig options for GBB flags
Use the flags to preset the GBB flags field. The Kconfig defaults are
chosen for a "developer" configuration.

Change-Id: Ifcc05aab10b92a2fc201b663df5ea47f92439a3f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13559
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-03 18:54:21 +01:00
Patrick Georgi 0db0e61f64 chromeos: Create GBB at build time
The GBB contains hardware-specific data plus some configuration. The
latter isn't supported by this change yet and will come later.

The fields that are supported (hardware ID, bmpfv, vboot keys) are
configurable through Kconfig and point to Chrome OS-style default (eg.
developer keys).

While adding vboot keys, the two keys used to sign RW regions are also
added to Kconfig, even if not yet used.

Change-Id: Icfba6061ca83182df560cd36052fbb257826d4b0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13558
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-03 18:53:53 +01:00
Martin Roth b09a5696a6 build_system: Extend site-local
- Add a target at the end of the build that can be used to run additional
scripts or additional targets after coreboot.rom is built.
- Source a site-local Kconfig file to allow site-specific configuration.

This eliminates the need to add a hook for a script at the end of the
build because you can add one yourself in site-local.

Example site-local/Makefile.inc:

build_complete::
ifeq ($(CONFIG_SITE_LOCAL),y)
	echo "Running additional steps in site-local"
	# run some script here to make my build unreproducible.
endif

.phony: build_complete

Example site-local/Kconfig:

menu "site-local"

config SITE_LOCAL
	bool "site-local enabled"
	help
	  Enable my site-local configuration to do stuff.

endmenu

Change-Id: Id4d1e727c69b5cdb05e7d52731bbb1d1e201864a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13413
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2016-02-03 15:45:14 +01:00
Edward O'Callaghan e3f47eada3 vendorcode/amd/agesa/f1{4,2,0} Sync Include directory
Sync and merge useless differences.

Change-Id: I4eea66c35af66d473dd56db9ccf105c878266f22
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: https://review.coreboot.org/7513
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-03 03:50:05 +01:00
Edward O'Callaghan c389635f6e vendorcode/amd/agesa/f15?tn: Strip false/redudant AMD ver tag
Strip out the AMD internal version tag, e.g.
 * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
which are false/inconsistent and serve no real meaning or purpose now.

Change-Id: I4cca0899eba66a1c361ba784c5ac0222b0ee1aa6
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: https://review.coreboot.org/7516
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-03 03:48:17 +01:00
Alexandru Gagniuc 420caafee8 include/device: Move inline functions from pci_def.h to pci.h
pci_def.h is supposed to only contain definitions, such that it may be
included in assembly files. Declaration of functions in said file
prevents that.

Change-Id: I0f90a74291c8a2ef7a1e1027d2d2182f896050fb
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: https://review.coreboot.org/13300
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-03 03:32:58 +01:00
Martin Roth 0cd9ff8987 xcompile: Add a way to specify -march=i586
Instead of instructing users to edit xcompile when they want to build
a quark platform, give the build a way to set -march=586 so that
the quark code will build correctly.  The Quark processor does not
support the instructions introduced with the Pentium 6 architecture.

Change-Id: I0ed69aadc515f86f76800180e0e33bcd75feac5a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13552
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2016-02-03 02:58:10 +01:00
Lee Leahy 9590992402 soc/intel/common: Use SoC specific routine to read/write MTRRs
The registers associated with the MTRRs for Quark are referenced through
a port on the host bridge.  Support the standard configurations by
providing a weak routines which just do a rdmsr/wrmsr.

Testing:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file
   *  Add "select DISPLAY_MTRRS"
   *  Add "select HAVE_FSP_PDAT_FILE"
   *  Add "select HAVE_FSP_RAW_BIN"
   *  Add "select HAVE_RMU_FILE"
*  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
*  Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
*  Testing is successful if:
   *  The MTRRs are displayed and
   *  The message "FspTempRamExit returned successfully" is displayed

TEST=Build and run on Galileo

Change-Id: If2fea66d4b054be4555f5f172ea5945620648325
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13529
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-02-02 19:00:35 +01:00
Martin Roth 2f91403303 src: Fix various spelling and whitespace issues.
This fixes some spelling and whitespace issues that I came across
while working on various things in the tree.

There are no functional changes.

Change-Id: I33bc77282f2f94a1fc5f1bc713e44f72db20c1ab
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13016
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-02 14:37:09 +01:00
Stefan Reinauer f76ceea705 commonlib: move uefi includes out of commonlib includes
... and move them into the code using them, instead.

Change-Id: I2391234797ad00da8038dda198eadf0b0fcaedb2
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13526
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-02 14:27:03 +01:00
Loic 0d473512c7 asus/f2a85-m: Configure Hudson to be legacy-free
Change-Id: I67271f2a209fc96eea6181f8875a5e69cf98d8c4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13511
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-02 14:25:20 +01:00
Loic 96a598b6c9 amd/agesa/family15tn: Add Richland CPU ID
Add the AMD A8-660K APU.

Change-Id: I210a8ba962529c26a535965689672a46b09e325f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13510
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-02 14:25:04 +01:00
Martin Roth cfc80c2211 arch/x86: Add second paragraph to license header
Change-Id: Ic1da46d2abc8d20987048e4ef1e7a776d0c685d6
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13555
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2016-02-02 14:23:44 +01:00
Martin Roth b00ddecd99 Kconfig: indent with tabs, not spaces.
Change-Id: I8996f8ab739a07014a4189738b5624485d752d9d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13540
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-02 01:44:56 +01:00
Martin Roth 1010868f87 src/: Fix Kcofig symbols missing CONFIG_ prefix
- Add CONFIG_ prefix to two symbols.
- Remove the use of the third symbol as it will never be matched.

Change-Id: Ifa7f6884001cb05fb8397f193c4b08a0161f498c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13539
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-02 01:44:12 +01:00
Jean Lucas 9ab9c33d7d lib/gcov-glue.c: Remove trailing number from COVERAGE_MAGIC macro
The COVERAGE_MAGIC macro has a trailing `4' on it, which makes it a
64-bit large integer, as opposed to a 32-bit unsigned integer, as
originally designated in `util/cbmem/cbmem.c'. Remove this number so
building with CODE_COVERAGE will succeed.

Change-Id: Ib5d7f2704a4c092c3eca6f62e219edb30950d793
Signed-off-by: Jean Lucas <jean@4ray.co>
Reviewed-on: https://review.coreboot.org/13520
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-02 01:39:28 +01:00
Timothy Pearson 21724934d5 cpu/amd/fam10h-15h: Add workaround for AMD Erratum 600
Change-Id: Ie175b5b490f77cc380536ebd737da8618d4b448b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13170
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-02-01 23:00:51 +01:00
Timothy Pearson bd8ab8890f mainboard/asus/kgpe-d16: Wait for all APs to stop before MCT setup
Under certain conditions when the APs are still executing during
MCT setup the system can hang.  This was the root cause of most
of the S3 resume failures on this platform; waiting for AP stop
before MCT setup allows for reliable S3 resume.

Change-Id: I329eea9a8912d7b57efe6aae327d24fd6c3fd782
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13169
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-01 22:57:55 +01:00
Timothy Pearson cb1dec57dc cpu/amd/fam10h-fam15h: Add new wait_ap_stopped function
Under certain conditions, such as when microcode updates are
being performed, it is important to make sure all APs have
finished updates and are halted before continuing with the
boot process.

Add a new wait_ap_stopped() function to allow for this
functionality to be added to the appropriate mainboard
romstage source files.

Change-Id: Ib455c937888a58b283bd3f8fda1b486eea41b0a7
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13168
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-01 22:57:08 +01:00
Timothy Pearson b410d267e3 nb/amd/amdmct/mct_ddr3: Save and restore SkewMemClk for S3 resume
Change-Id: Ib331bd330530d4d6be5eb7351d9f9b15c135dd63
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13167
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-01 22:56:33 +01:00
Timothy Pearson e79cb5e19d mainboard/asus/kgpe-d16: Use W83667HG-A specific PS/2 ASL file
Change-Id: I5a4e223b2e247decd30d8fb2a083be4cff6500a4
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13166
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-01 22:56:20 +01:00
Timothy Pearson b8d746fd13 mainboard/asus/kgpe-d16: Update DSDT with new devices and bump version
Change-Id: I15fedb067f1911799f7528b60b8754f2984b38ec
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13161
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-02-01 22:42:49 +01:00
Timothy Pearson 448e386309 drivers/pc80: Add PS/2 mouse presence detect
On certain Winbond SuperIO devices, when a PS/2 mouse is not
present on the auxiliary channel both channels will cease to
function if the auxiliary channel is probed while the primary
channel is active.  Therefore, knowledge of mouse presence
must be gathered by coreboot during early boot, and used to
enable or disable the auxiliary PS/2 port before control is
passed to the operating system.

Add auxiliary channel PS/2 device presence detect, and update
the Winbond W83667HG-A driver to flag the auxiliary channel as
disabled if no device was detected.

Change-Id: I76274493dacc9016ac6d0dff8548d1dc931c6266
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13165
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-01 22:10:46 +01:00
Timothy Pearson c2ed40b48a mainboard/asus/kgpe-d16: Add support for lifted BSP APIC IDs
Change-Id: Ic4b68a032068208d56b2a04150f7fc7d61b38eba
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13164
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-01 22:10:28 +01:00
Timothy Pearson c04f894f6b mainboard/asus/kgpe-d16: Add missing IRQ route to mptable
The IOMMU/HT device was not routed correctly; add the proper APIC
mappting to the mptable generation code.  Also clarify comments
surrounding the pin mappings.

Change-Id: I72ceb0f22dabdfa71a1f6231ccb841face08ff7a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13163
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-01 22:10:15 +01:00
Timothy Pearson cb93c130cf mainboard/asus/kgpe-d16: Clean up legacy PIRQ table code
Change-Id: Ib4f46944f076f1e696cf16a1e532eb8635b603c9
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13162
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-01 22:09:59 +01:00
Timothy Pearson 51c31696f2 southbridge/amd/sb700: Enable extended APIC ID when Kconfig option set
Change-Id: I52fc2c2294edead3b5dacf397c0a1ab2e08b1e3f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13160
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-01 22:04:24 +01:00
Timothy Pearson 919c459c17 southbridge/amd/sb700: Set HPET min tick value to RPR recommendation
Change-Id: I766eca6369b60a79a6823bc744934e3f1fbc17b2
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13159
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-01 22:04:12 +01:00
Timothy Pearson 0df7046ad0 cpu/amd/fam10h-15h: Fix Family 15h boot hang when BSP lift enabled
The existing code did not allow for the second core of the BSP to
reside on an APIC ID other than 1, leading to a boot hang on Family
15h processors when APIC_ID_OFFSET was set to anything other than 0.
Furthermore, insufficient AP stack space was allocated for AP start.

Change-Id: I4ded3cfb3736149e2265848014352d7622d5042a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13158
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-01 22:03:53 +01:00
Timothy Pearson 3679d7f909 mainboard/asus/kgpe-d16: Use W83667HG-A SuperIO instead of NCT5572D
Change-Id: If67999098fbe2831eeb30cb8b362c558db5d2688
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13157
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2016-02-01 22:03:35 +01:00
Stefan Reinauer eaa014676e vendorcode/intel: remove unused apple specific assembler macros
Since this code is pulled in through commonlib, it will break compilation
of cbfstool on OSX.

Change-Id: I342bfa7e755aa540c4563bb5cd8cccacee39d188
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13525
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-31 22:37:06 +01:00
Lee Leahy e0918bbc68 drivers/intel/fsp1_1: Fix spelling error in API and copyright
Change granluarity to granularity.
Change wacbmem_entryanty to warranty.
Update copyright dates.

TEST=None

Change-Id: Ib7775cb33616751760919a5850777dc6f77a6be9
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13528
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-31 20:51:29 +01:00
Vladimir Serbinenko 2387220c1b h8/battery: Fix ASL warning.
Change-Id: Idf74e400efa3fea8eb74f372e4f261ab6567db8a
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13513
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-01-31 14:41:01 +01:00
Vladimir Serbinenko 8b73cee9e5 stout: Fix VGA PCIIDs.
Change-Id: I7dcde170d0f59ea9886342c0d2c09b70b9d0d84d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13537
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-01-31 14:39:06 +01:00
Alexandru Gagniuc 7e86cd4bb2 soc/intel: Add skeleton infrastructure for Apollolake SOC
This is the very very minimum needed to compile the code.

Change-Id: I7f9e5f564181071591a4640019f59f91a4c456c6
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/13297
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-01-30 03:12:16 +01:00
Alexandru Gagniuc 6be6c8f282 arch/x86: Implement minimal bootblock for C_ENVIRONMENT_BOTOBLOCK
Some newer x86 systems can boot from non-memory-mapped boot media
(e.g. EMMC). The bootblock may be backed by small amounts of SRAM, or
other memory, similar to how most ARM chipsets work. In such cases, we
may not have enough code space for romstage very early on. This means
that CAR setup and early boot media (e.g. SPI, EMMC) drivers need to
be implemented within the limited amount memory of storage available.
Since the reset vector has to be contained in this early code memory,
the bootblock is the best place to implement loading of other stages.

Implement a bootblock which does the minimal initialization, up to,
and including switch to protected mode. This then transfers control
to platform-specific code. No stack is needed, and control is
transferred via a "jmp" such that no stack operations are involved.

Change-Id: I009b42b9a707cf11a74493bd4d8c189dc09b8ace
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: https://review.coreboot.org/13485
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-01-30 03:11:46 +01:00
Alexandru Gagniuc f8e491339f arch/x86: Rename bootblock.S to bootblock_romcc.S
bootblock.S was used strictly for setting up the system so that the
assembly generated by ROMCC could be executed. Since the
infrastructure now exists to run a bootblock wihtout ROMCC, rename
this file accordingly. this is done to prevent any future confusion.

Change-Id: Icbf5804b66b9517f9ceb352bed86978dcf92228f
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: https://review.coreboot.org/11784
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-01-30 03:11:12 +01:00
Vladimir Serbinenko 3141eac900 Revert "northbridge/intel/sandybridge: Fix random raminit failures"
It break x230 access to channel 1.

This reverts commit 9f1fbb9a30.

Change-Id: I8a3b13d17729f25cea3460ac2f87bca3c193d388
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13512
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2016-01-29 20:45:09 +01:00
Timothy Pearson 40e1fac56a southbridge/amd/sb700: Add CMOS option to disable legacy USB support
Change-Id: I136c259136ce66a0c319a965ae0ee27f66dce1b3
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13155
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-29 17:04:32 +01:00
Iru Cai e10d07e336 mainboard/cubieboard: use bootblock_mainboard_early_init
since commit f1e321001d, the UART init
should be in bootblock_mainboard_early_init() which runs before
console init. (see src/lib/bootblock.c)

Change-Id: Ib00afdd6e81e7689fbd743c8a5f547d424896d71
Reviewed-on: https://review.coreboot.org/13448
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-29 17:03:52 +01:00
Jean Lucas 6d2ca02101 google/peppy/Kconfig: Move select MAINBOARD_DO_NATIVE_VGA_INIT
Move the default select of "Use native graphics initialization" for
Peppy to the ChromeOS section as SeaBIOS (default payload) requires a
vBIOS and takes twice as long to load with this option enabled. For the
same reasons, this option shouldn't be enabled by default (def_bool y).

Change-Id: I1f2163e0a1e4bf8e5041dad150bdf7de804fb4db
Signed-off-by: Jean Lucas <jean@4ray.co>
Reviewed-on: https://review.coreboot.org/13493
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-29 17:02:26 +01:00
Hannah Williams 5166827c57 soc/braswell: Fix Global NVS base address
TEST=Boot to OS
Signed-off-by: Hannah Williams <hannah.williams@intel.com>

Change-Id: I9b43eb4f6f7af62a8a0bbe7bfa08feee1eaca24e
Reviewed-on: https://review.coreboot.org/13506
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-29 16:58:19 +01:00
Martin Roth 3e3d969e6f src/: Chmod 644 all .c, .h, .asl, .inc, .cb, .hex, & Kconfig files
Some trivial cleanup.

Change-Id: I866efc4939b5e036ef02d1acb7b8bb8335671914
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13427
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-29 16:57:11 +01:00
Subrata Banik fbdc719414 intel/skylake: Implement native Cache-as-RAM (CAR)
Now coreboot should do BIOS CAR setup along with NEM
mode setup.

This patch also provides a mechanism to use 16MB code caching
benefit although LLC still limited to 1M/1.5M based
on SOC LLC limit.
Here with unlimited cache line gets replaced. Now we could use
unlimited cache size along with well defined data size

[pg: updated to current upstream #defines]

BUG=chrome-os-partner:48412
BRANCH=glados
TEST=Builds and Boots on FAB4 SKU2/3.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: pchandri <preetham.chandrian@intel.com>
Signed-off-by: Dhaval Sharma <dhaval.v.sharma@intel.com>

Change-Id: I96a9cf3a6e41cae9619c683dca28ad31dcaa2536
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2ec51f15c874ad2f1f4fad52fa8deced7b27a24b
Original-Change-Id: Id62c15799d98bc27b5e558adfa7c7b3468aa153a
Original-Reviewed-on: https://chromium-review.googlesource.com/320855
Original-Commit-Ready: Subrata Banik <subrata.banik@intel.com>
Original-Tested-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13138
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-29 16:56:01 +01:00
Patrick Georgi dcc3ecc940 arch/arm64: Override bl31 timestamp with coreboot build timestamp
If coreboot's build process is reproducible (eg. using the latest git
timestamp as source), bl31 is, too.

This requires an arm-trusted-firmware side merge first (in progress) and
an update of our reference commit for the submodule, but it also doesn't
hurt anything because it merely sets a variable that currently goes
unused.

Change-Id: If139538a2fab5b3a70c67f4625aa2596532308f7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13497
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-01-29 16:37:02 +01:00
Timothy Pearson 988ee17fd2 superio/winbond/w83667hg-a: Add support for W83667HG-A
The KGPE-D16 and KCMA-D8 use a Winbond W83667HG-A SuperIO.  While
the Nuvoton NCT5572D is effectively the same core, and a close
enough match to get things working initially, the W83667HG-A
has a different LDN mapping and several extra features that
require a separate support driver.

Clone the Nuvoton NCT5572D and modify according to the W83667HG-A
datasheet, version 1.4.

Change-Id: I707ba2e40a22d41cd813003d84a82cb20304f55b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13156
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2016-01-29 00:49:29 +01:00
Timothy Pearson 8274accde8 southbridge/amd/sb700: Add missing DMA setup step from AMD RRG
Change-Id: I412a0e5f2e0686b10a295dd7c0e9b537dc1a0940
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13154
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-01-29 00:43:43 +01:00
Timothy Pearson 2ba84cd7de mainboard/asus/kgpe-d16: Use stock PS/2 ACPI ASL file
Change-Id: Iad724e9e1d3e64e2af3f74fed9dec30aa34e2af5
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13153
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-01-29 00:43:20 +01:00
Timothy Pearson cfea0bb44e mainboard/asus/kgpe-d16: Enable ASUS MIO audio option
The KGPE-D16 supports an optional MIO audio card, which connects
to the on-board HDA interface of the SP5100.

Enable the HDA interface for use with the MIO card.

Change-Id: Idfe069f4bce7b94a7460bc7fcdd378eb57e51fda
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13152
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-01-29 00:43:08 +01:00
Timothy Pearson 4c9c2f0d0d mainboard/asus/kgpe-d16: Move memory test before IMD setup
Change-Id: Ic6fbf6688e4c2adc85e4eb9fa17e79d29dda58c0
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13151
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-29 00:42:42 +01:00
Timothy Pearson 8e9106db20 nb/amdmct/mct_ddr3: Enable mainboard voltage set
The existing code used an incorrect macro name to check for mainboard
DRAM voltage set support, and as a result no voltages were actually
set.  Furthermore, the existing code did not contain a centralized
voltage assumption for boards that did not have a DIMM voltage set
implementation.

Use the correct macro name to test for boards with voltage set
implementation, and provide a basic fallback to 1.5V operation
for boards without a voltage set implementation.

Change-Id: I638c65fe013a8e600694d8cbedf6a10b33b0ef95
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13150
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-29 00:42:30 +01:00
Timothy Pearson 71f864191f cpu/amd/fam10h-fam15h: Correctly create APIC ID on single node systems
The existing code generated an incorrect boot APIC ID from node and
core number for single node packages, leading to a boot failure when
the second node was installed.

Properly generate the boot APIC ID from node and core number.

Change-Id: I7a00e216a6841c527b0a016fa07befb42162414a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13149
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-29 00:42:21 +01:00
Damien Zammit 9253ce60c4 mb/gigabyte/ga-g41m-es2l: Remove PMBASE settings and commented code.
Fixed incorrect comment regarding port 80 LPC route.

Change-Id: Ifbb73753d5a0737418b869085f2329a02504e5dc
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13466
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2016-01-29 00:29:30 +01:00
Damien Zammit c70966cd26 mb/gigabyte/ga-g41m-es2l: Remove copy-pasted cstates
Change-Id: I5b6edbd97d4e6ed8b03f2f319a338022647e26ea
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13465
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2016-01-29 00:28:34 +01:00
Damien Zammit c4d317f107 mb/gigabyte/ga-g41m-es2l: Move MMCONF base address to 0xe0000000
Change-Id: I3873d92069cc1d113a8092d609d1768ff45cbd45
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13129
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2016-01-29 00:28:02 +01:00
Damien Zammit 5680fafb4d nb/intel/x4x: Move to early cbmem
Previously with errors in the ram init, early cbmem was disabled.
Now that the ram is working correctly, set as early cbmem platform
and update all (1) boards to use it.

Tested on GA-G41M-ES2L

Change-Id: I5925c28821537f0e326b4f5a2ac39778e4724a3c
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13131
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-29 00:27:09 +01:00
Damien Zammit 216fc50411 nb/intel/x4x: Cleanup gma.c
Tidy up the code and move vga_textmode_init() later

Change-Id: I49967e7197416c955ae6c8775eac7d1a60c92d1c
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13128
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-29 00:25:59 +01:00
Damien Zammit d63115daa8 nb/intel/x4x: Tidy up raminit and fix msbpos() function
- Fix bug with msbpos, it was not returning the correct result
  due to typo in logic, and unsigned value needed to be negative.
- Add reclaim above 4GiB
- Fix to ME related registers near the end of raminit

Change-Id: I04acd0593a457437ee4a42e14b287b2b17a160af
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13127
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2016-01-29 00:22:48 +01:00
Damien Zammit fe9876a763 nb/intel/x4x: Tidy up northbridge
- Add device enable macros
- Set the PMBASE correctly through southbridge device

Change-Id: I1b8cc3de96b1ecaf01e31bad8fba1fada8671c2d
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13126
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-29 00:18:58 +01:00
Damien Zammit 9fb08f55a8 nb/intel/x4x: Fix memory hole with both channels populated
Previously, 0xa0000000 to 0xc0000000 needed to be reserved as
a non-usable memory hole because it would hang on memory i/o.

Memtest86+ now passes with no errors on both channels populated.
Tested on GA-G41M-ES2L with 2x2GiB sticks of ram.

Change-Id: Ib52a63a80f5f69c16841f10ddb896ab3c7d30462
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13125
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-01-29 00:17:38 +01:00
Martin Roth 43f16f8dd8 src/: give scripts a .sh extension for easy identification
Just rename the two scripts that are in the src/ tree to give them
a .sh extension.  Since we generally expect files in the src directory
to be source files, this allows to identify these as scripts easily.

Change-Id: I0ab20a083880370164488d37a752ba2d5a192fdc
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13432
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-28 23:26:42 +01:00
Patrick Georgi 23cc9b09c7 via/cx700: Use zeroptr over 0
This eliminates all "ud2" instances from romstage disassembly.

Change-Id: I3b0c8322a4ca4a851b0cce8f3941425d9cb30383
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: https://review.coreboot.org/13488
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28 23:26:07 +01:00
Patrick Georgi ff8076d75a Provide a gcc-safe zero pointer
zeroptr is a linker object pointing at 0 that can be used to thwart
GCC's (and other compilers') "dereferencing NULL is undefined"
optimization strategy when it gets in the way.

Change-Id: I6aa6f28283281ebae73d6349811e290bf1b99483
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: https://review.coreboot.org/12294
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28 23:25:53 +01:00
shkim cc728f0284 soc/braswell: Add interface to program USB2_COMPBG register
Add interface to program USB2_COMPBG register to set
HS_DISC_BG and HS_SQ reference voltage for each project.

TEST=Get build success and do EFT test

Original-Reviewed-on: https://chromium-review.googlesource.com/300846
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Original-Tested-by: shkim <sh_.kim@samsung.com>
Change-Id: If2201829e1a16b4f9916547f08c24e9291358325
Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Signed-off-by: shkim <sh_.kim@samsung.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/12739
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28 20:46:23 +01:00
Freddy Paul e8cc52fab0 ec/google/chromeec/acpi :Enable DPTF charger/TSR1/TSR2 participant.
TEST=Plug/Unplug AC Adapter multiple times and make sure device is
     charging  properly.

Original-Reviewed-on: https://chromium-review.googlesource.com/303990
Original-Reviewed-by: Jenny Tc <jenny.tc@intel.com>
Original-Reviewed-by: T.H. Lin <T.H_Lin@quantatw.com>
Original-Tested-by: T.H. Lin <T.H_Lin@quantatw.com>
Original-Tested-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Original-Reviewed-by: Divya Jyothi <divya.jyothi@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Signed-off-by: Freddy Paul <freddy.paul@intel.com>

Change-Id: I188e80e6688d0bac5bed6dd64cd2d0feefa30d3f
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Signed-off-by: Freddy Paul <freddy.paul@intel.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/12748
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28 20:45:46 +01:00
Jenny TC 01be52eca9 soc/braswell/acpi/DPTF: Write TCHG state on AC connect.
DPTF should update the charger cooling device state during
boot time and every 3 seconds after boot. But 3 seconds polling
doesn't seems to be working with current version of DPTF.
This impacts charging since DPTF writes states 4 when charger
is not connected at boot time. On connecting the charger,
DPTF doesn't write 0 to enable charging. This issue is addressed
by calling the PPPC function to read cooling device state  and passing
the value to SPPC to set cooling device state. This doesn't
compromise safety since DPTF can override this value
later based on the platform thermal condition. Also this provides
additional safety measure in the unlikely event that DPTF crashes
and is not re-spawned by OS. With this patch even after DPTF crashes,
if the power adapter is plugged it would still allow the system to
charge correctly.

Original-Reviewed-on: https://chromium-review.googlesource.com/288460
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Jenny Tc <jenny.tc@intel.com>

Change-Id: I50c7666b86e45d5ab537a9d4149e6c71eba04e50
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/12729
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28 20:45:28 +01:00
Divagar Mohandass 060bc7941f intel/strago: Update DPTF parameters to higher temperature.
Fish bowl HTML5 graphics benchmark with 250 fish
is not reaching 60 FPS. This change will update
the DPTF parameters to accommodate this test.

TEST=Run fish bowl benchmark with 250 fish
and check for 60 FPS.

Change-Id: I6b6827199cb0f5ab44c354abc477ea73e4de9ec5
Original-Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/302208
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13484
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28 20:45:11 +01:00
Hannah Williams ba6dfe4cc5 soc/braswell/acpi: Fix CID1 offset in comment
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Change-Id: I9fd2ebba985362fe8068c10390bb014cf9015ac5
Reviewed-on: https://review.coreboot.org/13483
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28 20:44:50 +01:00
Hannah Williams 73600e3199 soc/braswell: Fix for auto wake from S5
Disabling S5 wake from touch panel and trackpad

TEST=Build and boot the platform.
TEST=Poweroff platform -> enter PG3 -> remove AC -> close Lid
     Plug AC in -> EC boots up and AP will shutdown the platform
     and open Lid -> platform boots to OS.

Change-Id: I7b661a9f1327b97d904bac40e78612648f353e39
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/288970
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Divagar Mohandass <divagar.mohandass@intel.com>
Original-Tested-by: Divagar Mohandass <divagar.mohandass@intel.com>
Reviewed-on: https://review.coreboot.org/13425
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28 20:44:34 +01:00
Kumar, Gomathi 2b9696239f intel/strago: Fix for Crossystem "wpsw_cur" status
The GPIO mapping was incorrect for wpsw_cur. The GPIOs for East 
community are in two ranges - 0: INT33FF:02 GPIOS [373 - 384] 
PINS [0 - 11]  and 12: INT33FF:02 GPIOS [385 - 396] PINS [15 - 26]
The discontinuity was not accounted for, hence the error.Original 
offset was 0x16 whereas it should be 0x13

TEST=Run crossystem and test wpsw_cur entry. If screw is present,
it should be 1 and if not present, it should be 0

Change-Id: I29e19589b3a358a42818afbc6d017d6cbc6a9c4c
Original-Signed-off-by: Kumar, Gomathi <gomathi.kumar@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/291572
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Icarus W Sparry <icarus.w.sparry@intel.com>
Reviewed-on: https://review.coreboot.org/13424
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28 20:44:15 +01:00
Ravi Sarawadi d077b58c61 soc/braswell: Fix issues found during static code analysis
TEST=Build, boot to OS

Original-Reviewed-on: https://chromium-review.googlesource.com/299483
Original-Reviewed-by: Aaron Durbin <adurbin@google.com>

Change-Id: I738003b8dfff6a5255085d39e378e18d6ad36bcf
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/12738
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28 20:43:22 +01:00
Hannah Williams 9657f3bb09 intel/strago: Get Boot Flash Write Protect status
Read GPIO to get the status

Change-Id: Id2d56ce4b47c4cccba2de3f113afaee6c49885c9
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/13186
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28 20:41:28 +01:00
Kenji Chen b1e4bd0d28 Braswell: Separate L1 Sub State init procedure for boards.
Original-Reviewed-on: https://chromium-review.googlesource.com/312743
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com>

Change-Id: Ib0a891f229477cf359bff6cd02f305606468f07f
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Reviewed-on: https://review.coreboot.org/12750
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28 20:41:14 +01:00
Shobhit Srivastava c4153c1b15 Strago: Enable CA Mirror
Configuring UPD PcdCaMirrorEn. This is a board specific parameter.
CA mirror is the Command Address mirroring option that is enabled
on this board

CQ-DEPEND=CL:13038

Original-Reviewed-on: https://chromium-review.googlesource.com/309190
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

Change-Id: I05174e18d650332d838e5036c713e91c4840ee75
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/12749
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28 20:40:48 +01:00
Hannah Williams 731e463495 intel/cyan: Disable SD Card Detect Simulation in FSP
CQ-DEPEND=CL:12742

Change-Id: Ifc95809e342d87f863dd60967f5b3a6ca5c0f7b3
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/13036
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28 20:40:01 +01:00
Hannah Williams 79445c72b2 Strago: Disable SD Card Detect Simulation in FSP
CQ-DEPEND=CL:12742

Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Change-Id: I6c39ffebe407a4ef8555b2f050a96d33709dc624
Reviewed-on: https://review.coreboot.org/13035
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28 20:39:46 +01:00
Divya Sasidharan 89a6685ede soc/braswell: Disable SD card detect simulation in FSP
CQ-DEPEND=CL:13038

Debounce for SD card detect takes a long time and thus affects boot time.
Disabling SD card detect simulation in FSP through UPD

Original-Reviewed-on: https://chromium-review.googlesource.com/311850
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Tested-by: Hannah Williams <hannah.williams@intel.com>

Change-Id: Iab0794ec058460df94f6bbed5c9b0911e57e3a71
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-on: https://review.coreboot.org/12742
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28 20:39:21 +01:00
Hannah Williams b0eb594b34 soc/braswell: Set max frequency to be turbo frequency
In set_max_freq, instead of using ratio from IA_CORE_RATIOS, using
ratio from MSR_IACORE_TURBO_RATIOS
Also, punit_init needs to be called before enabling this frequency.

Original-Reviewed-on: https://chromium-review.googlesource.com/295268
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Hannah Williams <hannah.williams@intel.com>

Change-Id: Iabdab9ec45f8eef0a105a5a05dbcdb997b6764b0
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/12736
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28 20:38:57 +01:00
Hannah Williams 103f00daab intel/strago: Remove support for older rev boards
Cleaning up code to remove support for early revs of Strago board

Change-Id: Ic0647a17d78164fd7dfadc731c9395a8ba08c235
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/13434
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28 20:36:35 +01:00
Hannah Williams 26f64069d2 soc/braswell: Configure Boot Flash Write Protect status GPIO
Set up the GPIO(MF_ISH_GPIO_4) to read WP status.

TEST=Use crossystem to read the WP status
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Change-Id: I17cbcba013e2a11c2527731df985aa1243065eff
Original-Reviewed-on: https://chromium-review.googlesource.com/302424
Original-Tested-by: John Zhao <john.zhao@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Hannah Williams <hannah.williams@intel.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/13185
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28 20:35:59 +01:00
Jagadish Krishnamoorthy c681638116 intel/strago: Enable native mode on sd card cd line
Configuring Native Mode enables the card present bit in
sd card controller register.

TEST=Sd Card Plug/Unplug should work in OS and DepthCharge.

Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

Change-Id: I2f017bdd7125f324fb58a88485cd83110851fbc5
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/12741
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28 20:35:35 +01:00
Jagadish Krishnamoorthy 1d03f36887 intel/strago: Disable unused lines on Gpio North Bank
The unused lines leads to spurious interrupts
on few of the systems.

TEST=run suspend_stress test and make
sure that kbd is working.

Change-Id: Ie539e1debc15dd1fd8707f8866c65714fc43e44b
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313417
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/13176
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28 20:35:13 +01:00
fdurairx aff502e87a soc/braswell: Fix DSP clock
The codec clock frequency was incorrectly set to 25MHz.
The only available frequency is 19.2MHz through external clock and PLL.

Original-Reviewed-on: https://chromium-review.googlesource.com/295768
Original-Tested-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I9bef334a5a3aaee28fcc4937180896ff49969bc5
Signed-off-by: Felix Durairaj <felixx.durairaj@intel.com>
Reviewed-on: https://review.coreboot.org/12732
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28 20:34:06 +01:00
Damien Zammit 63eb917275 mb/intel/d510mo: Use SATA AHCI by default
Change-Id: I6f9772c5bcf9a50dfbc3d1cfaeb79f4454d1fb27
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13454
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-01-28 17:57:25 +01:00
Damien Zammit 761c2942ef mb/intel/d510mo: Use native gfx initialization
Change-Id: Ic4de7a762e90b379be3814afc61467e1cd099215
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13034
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-28 17:56:32 +01:00
Damien Zammit 301999f4b8 mb/intel/d510mo: Add CPU, SMI-trap and PIC to DSDT
Change-Id: I80853cadb4762d9bb34926e31d65d248c5683417
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13453
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2016-01-28 17:56:14 +01:00
Damien Zammit 7102d005b9 mb/intel/d510mo: Add missing GPIO and GPEN
Change-Id: I56c0a55d57d8beabcb33cf1984b037556a71a8b9
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13452
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-28 17:53:57 +01:00
Damien Zammit 51fdb9256a nb/intel/pineview: Native VGA init (CRT)
VGA grub console works but display wobbles left/right

drm/i915 driver reports one error:
- [drm:i915_irq_handler] *ERROR* pipe A underrun
- Monitor does not display 1920x1080 after modeset
- Other resolutions look out of sync

Cause: suspect single bug in raminit (chipset init)

Change-Id: I2dcf59f8f30efe98f17a937bf98f5ab7221fc3ac
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/12921
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28 17:53:47 +01:00
Lee Leahy b092c9e9c1 drivers/intel/fsp1_1: Remove extra include references
Remove include references to the soc include directory which are not
required to build the FSP driver.  Remove "duplicate" include file
definitions from file that include fsp/romstage.h.  Move the definition
of fill_power_state into soc/pm.h to ensure it is still available.

TEST=Build and run on Galileo

Change-Id: Ie519b3a8da8c36b47da512d3811796eab62ce208
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13436
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-01-28 17:12:22 +01:00
Nico Huber 98fc426a98 Move object files to $(obj)/<class>/
Instead of tagging object files with .<class>, move them to a <class>
directory below $(obj)/. This way we can keep a 1:1 mapping between
source- and object-file names.

The 1:1 mapping is a prerequisite for Ada, where the compiler refuses
any other object-file name.

Tested by verifying that the resulting coreboot.rom files didn't change
for all of Jenkins' abuild configurations.

Change-Id: Idb7a8abec4ea0a37021d9fc24cc8583c4d3bf67c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/13181
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-01-28 00:31:32 +01:00
Nico Huber 81b09f4008 Makefile: Make full use of src-to-obj macro
There were several spots in the tree where the path to a per class
object file was hardcoded. To make use of the src-to-obj macro for
this, it had to be moved before the inclusion of subdirs. Which is
fine, as it doesn't have dependencies beside $(obj).

Tested by verifying that the resulting coreboot.rom files didn't change
for all of Jenkins' abuild configurations.

Change-Id: I2eb1beeb8ae55872edfd95f750d7d5a1cee474c4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/13180
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-28 00:31:00 +01:00
Kane Chen 116d67323b intel/strago: Set LPC_CLKRUNB to PU_20K to solve leakage issue.
LPC_CLKRUNB pin needs to be set to PU_20K to prevent leakage

TEST=Test on Strago and make sure the leakage is gone

Signed-off-by: Kane Chen <kane.chen@intel.com>
Change-Id: Id2bf7511806cdc52b505bb469238a9465b356352
Original-Reviewed-on: https://chromium-review.googlesource.com/317020
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Tested-by: Kane Chen <kane.chen@intel.com>
Original-Commit-Queue: Kane Chen <kane.chen@intel.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/13175
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28 00:04:19 +01:00
Divagar Mohandass 2abcffcc40 intel/strago: EC_IN_RW gpio input configuration.
Configure EC_IN_RW signal as gpio input.

TEST=Boot to Chrome OS in normal mode and enter recovery mode
use ctrl-d to switch to Dev mode.

Change-Id: I835a1c70d89ef2ab75c35233f889124b60bb64a3
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/304040
Original-Tested-by: Divagar Mohandass <divagar.mohandass@intel.com>
Original-Reviewed-by: Gomathi Kumar <gomathi.kumar@intel.com>
Original-Reviewed-by: Shobhit Srivastava <shobhit.srivastava@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Shobhit Srivastava <shobhit.srivastava@intel.com>
Reviewed-on: https://review.coreboot.org/13124
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28 00:03:12 +01:00
Divagar Mohandass 39f84fa662 intel/strago: Clean up DDR configuration.
This change includes following changes:
- Clean up the DDR configuration and flow.
- Removing support for non LPDDR3 boards.
- Supporting only LPDDR3 and PMIC config.

TEST=Build/flash CB and boot the platform to OS.

Change-Id: I8369443da728a4c07e0c1a82040d94034c3542da
Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/297941
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Jenny Tc <jenny.tc@intel.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/13122
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28 00:02:15 +01:00
Divagar Mohandass 4f4c6e88be intel/strago: Disable unused devices.
This change will disable unused devices in
device tree to improve boot performance.

TEST=Build/Flash CB and boot to OS.
verify Touch screen, Audio, WIFI and Track pad functionality.

Change-Id: Ib5ae31c96d75f9a5b0f8d8b72d058e18fe7d7e67
Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/300943
Original-Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Gomathi Kumar <gomathi.kumar@intel.com>
Reviewed-on: https://review.coreboot.org/13423
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28 00:00:32 +01:00
Shobhit Srivastava 97f09c3f19 soc/braswell: Fix leakage on V1P8S rail
Tristate MMC1_RCLK pin to fix leakage on V1P8S rail.

Original-Reviewed-on: https://chromium-review.googlesource.com/292043
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Divagar Mohandass <divagar.mohandass@intel.com>

Change-Id: I76cc9211ba93b2596d3c0d772d99f8934656e01c
Signed-off-by: Shobhit Srivastava <shobhit.srivastava@intel.com>
Reviewed-on: https://review.coreboot.org/12730
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2016-01-27 23:59:39 +01:00
Hannah Williams fc5489fc5e soc/braswell: Add macro NATIVE_INT_PU20K
Change-Id: I04db02d37a76f0643a73ae4d67b839e5cd61f7e3
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/13054
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2016-01-27 23:59:03 +01:00
Hannah Williams d4b26b2923 intel/strago: Fix GPIO config
Fix GPIO config for this board:
- SD card detect to GPI
- SATA GPI to not used
- GPIO_SUS1 and GPIO_SUS11 to GPI with pull up (1K and 20K)termination
- I2C4 SDA and SCL from not used to Native

Change-Id: Iecb23df465a540a71f7268c5aac48617dc74ebf2
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/13431
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-27 23:58:11 +01:00
Hannah Williams b11591064b soc/braswell: Update FspUpdVpd.h for PcdSdDetectChk and PcdCaMirrorEn
Change-Id: I42200feafed613136f23e37d4ab4c90931698821
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/13038
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-27 23:56:50 +01:00
Lee Leahy a608969ebb drivers/intel/fsp1_1: Enable builds without MRC cache
Properly use the CONFIG_CACHE_MRC_SETTINGS value to determine when to
cache the MRC settings.

TEST=Build and run on Galileo

Change-Id: Ibc76b20b9603b1e436a68b71d44ca1ca04db7168
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13437
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-27 21:33:18 +01:00
Martin Roth 4b7a00867a intel/sklrvp: Remove mainboard
The Intel Skylake RVP3 mainboard is not building, and according
to Intel, there is no plan to continue working on it for coreboot.

The intel/kunimitsu board is the Skylake reference design for
coreboot.org.

Change-Id: Icb4e42fdb560cc3188ca29c465674f5e0b11569b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13469
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-01-27 17:36:10 +01:00
Julius Werner ffc2260d74 chromeos: vpd: Avoid reading uninitialized VPDs
This patch adds a check to the VPD parsing code to avoid reading the
whole thing if the first byte ('type' of the first VPD entry) is 0x00
or 0xff. These values match the TERMINATOR and IMPLICIT_TERMINATOR types
which should never occur as the first entry, so this usually means that
the VPD FMAP section has simply never been initialized correctly. This
early abort avoids wasting time to read the whole section from SPI flash
(which we'd otherwise have to since we're not going to find a Google VPD
2.0 header either).

BRANCH=None
BUG=None
TEST=Booted Oak, confirmed that VPD read times dropped from 100ms to
1.5ms.

Change-Id: I9fc473e06440aef4e1023238fb9e53d45097ee9d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 20a726237e03941ad626a6146700170a45ee7720
Original-Change-Id: I09bfec3c24d24214fa4e9180878b58d00454f399
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/322897
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/13467
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-27 16:27:27 +01:00
Julius Werner 4f7a3614cd chromeos: Add timestamps to measure VPD read times
This patch adds three timestamps to coreboot and the cbmem utility that
track the time required to read in the Chrome OS Vital Product Data
(VPD) blocks (RO and RW). It's useful to account for these like all
other large flash accesses, since their size is variable.

BRANCH=None
BUG=None
TEST=Booted Oak, found my weird 100ms gap at the start of ramstage
properly accounted for.

Change-Id: I2024ed4f7d5e5ae81df9ab5293547cb5a10ff5e0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b97288b5ac67ada56e2ee7b181b28341d54b7234
Original-Change-Id: Ie69c1a4ddb6bd3f1094b3880201d53f1b5373aef
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/322831
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/13139
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-27 16:27:18 +01:00
Stefan Reinauer 7ee6cd5901 arch/x86: Drop arch/pciconf.h
It's unused, so get rid of it.

Change-Id: I28c6dc0208686edc3aabaf624773ea70350c1c8f
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13177
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-26 20:22:44 +01:00
Subrata Banik ed7275f2c3 Braswell: Implement Gpio library functions to read RAMID
Added GPIO library code to allow all BSW board specific code
to use memory configuration GPIOs in GPIO Input mode and read
them to determine which memory type is on the board.

Also added other GPIO related APIs to support GPIO access
in BSW.

Original-Reviewed-on: https://chromium-review.googlesource.com/294893
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Idd65136c0449f0cdebfae12a510985e29889fa2b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/12735
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-26 05:12:02 +01:00
Damien Zammit 2cfab90baa nb/intel/pineview: Increase MMCONF decoding to 256 busses
Linux kernel detects 256 busses but previously only 64 were
allocated.  Removes warning in OS.

Change-Id: Id83c85e60025a04acbe6a53dfea6878222d8791f
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13033
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-26 04:51:38 +01:00
Martin Roth 4af5886ab1 src/arch: Update license headers missing paragraph 2
For the coreboot license header, we want to use two paragraphs.
See the section 'Common License Header' in the coreboot wiki
for more details.

Change-Id: I4a43f3573364a17b5d7f63b1f83b8ae424981b18
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13118
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-26 04:44:20 +01:00
Martin Roth 345f2b7d6b ga-g41m-es2l: Instead of forcing native VGA, make it selectable
This allows the native VGA to be disabled for debug, or if someone wants
to use the vbios.

Change-Id: I59a94fa0d02bfe254c8a598e15d3d9d73ecfe650
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12848
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Damien Zammit <damien@zamaudio.com>
2016-01-26 04:43:22 +01:00
Damien Zammit 2950cd2de1 mainboard/intel/d510mo: Licence fixes and azalia verb table
Azalia verb table replicated from vendor bios.
Licence headers added where appropriate.

Change-Id: I29e4fe433dee6c5f30fe36055fc9a8bf2062fef5
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/12621
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2016-01-26 04:42:09 +01:00
Patrick Georgi 546f29dbf1 arch/x86: move SetCodeSelector to .text segment
It ended up in .data, and that doesn't seem to be actually necessary.

Change-Id: Ib17d6f9870379d1b7ad7bbd3f16a0839b28f72c8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13134
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-01-26 04:40:44 +01:00
Werner Zeh 2bb574e52c mc_tcu3: Enable auto generated attributes in cbfs
Use CBFS_AUTOGEN_ATTRIBUTES for mc_tcu3 to enable position
and alignment attributes in cbfs.

Change-Id: I6c39bb02ab641d7e22e20e77a72a577f159549dd
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/13123
Tested-by: build bot (Jenkins)
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2016-01-25 13:58:17 +01:00
Timothy Pearson db84a99011 nb/amd/mct_ddr3: Properly set MR0 WR value
The existing code accidentally truncated the MSB from the MR0
WR value.  While this probably had a minimal effect in reality,
it should be configured correctly for maximal system stability.

Change-Id: Ifb8a39c6ca47b32b44d33735e5c6c39f1dc5a44e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13147
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-01-24 23:26:59 +01:00
Timothy Pearson ad9a2bb0de nb/amd/mct_ddr3: Add additional verbose-level debug statements
Change-Id: Ie91c990d9c2bcab8292a75d87523a46d5694a34a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13146
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-24 23:26:13 +01:00
Timothy Pearson 2d500ba598 nb/amd/mct_ddr3: Update drive strength configuration
The existing drive strength calibration code did not strictly
follow the BKDG-defined setup process.  Bring the calibration
code in line with the BKDG recommendations.

Change-Id: I122eeb93958d88de59d0c3b2979f607afa2c52c3
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13145
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-24 23:25:18 +01:00
Timothy Pearson a2df081d44 northbridge/amd/amdmct/mct_ddr3: Enable fast refresh on ETR devices
When an Extended Temperature Range DIMM is installed on a channel
the refresh rate should be increased per the BKDG recommendations
to allow correct operation at higher temperature ranges.

Set fast refresh on a channel if an ETR DIMM is installed on that
channel.

Change-Id: I7a085d34efc78f3f0794a5cb33b88f27a5e6d54e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13144
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-24 23:24:33 +01:00
Timothy Pearson ba2af2e21d cpu/amd/family_10h-family_15h: Move CBMEM storage out of CC6 save region
The existing CBMEM TOM calculations did not account for the CC6 save region
(when enabled); this resulted in CBMEM storage being placed on top of the
CC6 save region, which resulted in corrupt CBMEM data and a boot hang.

Change-Id: I32399da0438d7b16e05192449be625f9aa675b18
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13143
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-24 23:23:23 +01:00
Timothy Pearson 39495bae5f cpu/amd/family_10h-family_15h: Set LDT tristate correctly on C32 sockets
The existing code unconditionally cleared the LDT tristate enable bit,
which was incorrect for C32 sockets.  Update the code to be in line
with the BKDG recommendations.

Change-Id: I8095931973ea10f1467a6621092e88c6c494565a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13142
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-24 23:22:34 +01:00
Timothy Pearson 6aa6eab98b northbridge/amd/amdmct: Add termination and timing values for C32 sockets
The existing MCT initialization code was largely missing C32 socket-
specific configuration data.  Add C32 socket-specific timing and ODT
values as specified in the BKDG.

Change-Id: I8eef8d5c8581f03d269663a338d5542744c5cdd7
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13141
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-24 23:20:31 +01:00
Timothy Pearson 19ce16ae69 northbridge/amd/amdfam10: Update DRAM speed limits for C32 sockets
The existing code applied G34-specific speed limits to all socket
types.  Update G34 and C32 specific speed limits to be in line with
BKDG recommendations.

Change-Id: I958ad333c47948ae741a56de5866af3e636fd24d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13140
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-24 23:20:02 +01:00
Martin Roth a39e6d1cf9 purism/librem13: Fix select of EC_PURISM_LIBREM
This was misspelled as EC_PURISM_LIBEM, causing the EC to not
get included in the build.

Change-Id: Iffbfb504926e1b90070c2dbf61c0c44ca8fb46bc
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13178
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-24 17:04:17 +01:00
Aaron Durbin eb907b3c90 arch/x86: link bootblock like other stages for C_ENVIRONMENT_BOOTBLOCK
When C_ENVIRONMENT_BOOTBLOCK is selected link bootblock using the
memlayout.ld scripts and infrastructure. This allows bootblock on
x86 to utilize all the other coreboot infrastructure without
relying romcc.

Change-Id: Ie3e077d553360853bf33f30cf8a347ba1df1e389
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13069
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-01-23 18:25:48 +01:00
Aaron Durbin 1b915b8904 lib/memrange: allow stack allocated free list
Instead of solely relying on malloc for building up an address space
for the range_entry objects allow one to supply a list of free entries
to memranges_init_empty(). Doing this and only calling malloc() in
ramstage allows a memranges oboject to be used in a malloc()-free
environment.

Change-Id: I96c0f744fc04031a7ec228620a690b20bad36804
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13020
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2016-01-23 18:25:26 +01:00
Patrick Georgi 4a30ab9096 cpu/amd: remove .intel_syntax
Replace with the more familiar AT&T syntax.
Tested by sha1sum(1)ing the object files, and checking the objdump that
the code in question was actually compiled.

Change-Id: Ibdc024ad90c178c4846d82c5308a146dd1405165
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13133
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-23 17:01:53 +01:00
Patrick Georgi 0302b060b6 arch/x86: remove .intel_syntax
Replace with the more familiar AT&T syntax.
Tested by sha1sum(1)ing the object files, and checking the objdump that
the code in question was actually compiled.

Change-Id: Ie85b8ee5dad1794864c18683427e32f055745221
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13132
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-23 17:01:44 +01:00
Yidi Lin b9b2c6fef2 google/oak: Configurate SD card detection pin
BRANCH=none
BUG=chrome-os-partner:47609
TEST=remove servo board connection and insert/remove an empty SD card
     in recovery mode.

Change-Id: I89a1cb6914d634f07ff71b9793eb29b711381524
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d21bf091a576574cb9e976447ee2b9a69748d2b6
Original-Change-Id: I2083605c9ad88841885dfaad48dcd27e6fb5161d
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313073
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13099
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-22 22:15:51 +01:00
CC Ma e3413cce3c mediatek/mt8173: revise cbmem_top
Support memory range querying to above/below 4GiB.
Enable PRERAM_CBMEM_CONSOLE.

BRANCH=none
BUG=none
TEST=build and verified pass on oak board

Change-Id: If12ab2e9b8a129e2c82dd97b0493d9abdd6985a9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 139a3163ca867ec5676c6cb81fdec724c99a4a99
Original-Change-Id: Ie190f86f49ae88671f0738e2d6ceafdad58a93cc
Original-Signed-off-by: CC Ma <cc.ma@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292559
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13098
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-22 22:15:38 +01:00
Yidi Lin 767b45fe96 mediatek/mt8173: move rtc_boot() to romstage
BRANCH=none
BUG=none
TEST=boot to kernel

Change-Id: I0630d7c172e97f81abb1722afe028542e9e7f106
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 608c66df0543c76be7e811b06718464776631b55
Original-Change-Id: I03426085121bfa44c99c351d63db28f567d0ee1d
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313969
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13097
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-22 22:15:22 +01:00
Patrick Georgi 82d9a31d9e lib: compile mdelay for romstage
Mimicking change I7037308d2, always compile mdelay for romstage.
The boards that #included delay.c in the romstage now rely on the linker
instead, which is a desirable cleanup.

Change-Id: I7e5169ec94e5417536e967194e8eab67381e7c98
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13115
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-22 22:15:09 +01:00
Ben Lok a737940240 google/oak: setup usb and configure I2C level shift pin
BRANCH=none
BUG=none
TEST=build pass and verified on rev3

Change-Id: I3849342e59c2b022db723ef0281cdd5153ae27cb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 495e978cd7381bd393099315ac6d60fe4446dd9f
Original-Change-Id: I9626d06746e5d0bf6698a9b8e7594c58e7ff213a
Original-Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292689
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13096
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22 20:07:04 +01:00
Chunfeng Yun f764d1458d mediatek/mt8173: Add usb phy driver
BRANCH=none
BUG=none
TEST=build pass and test it ok on oak

Change-Id: Ib3d3f420dd576a63d7504dd0949040a3d430c675
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b17b03ed40b562a520185fa243bc4458daed6f23
Original-Change-Id: Ib9346f7913433ca82e8123feaf34fd0d6c071047
Original-Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292687
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13095
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22 20:06:53 +01:00
Chunfeng Yun cc248bcce3 mediatek/mt8173: pll: Add API for enabling USB 3.0 phy reference clock
BRANCH=none
BUG=none
TEST=test it ok on oak-rev3

Change-Id: I05233c5b9aa237dce1e6667ed09fe6d56f8e6350
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: eb3efe8d0d1199ab836af01dc012cc97257b4fd4
Original-Change-Id: Ie1ab9421052dbd6aea8fbd762143cec0ce0d88f5
Original-Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/297942
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13094
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22 20:06:34 +01:00
YH Huang 1fcee36ad7 google/oak: Configure backlight control pins
Since backlight is controlled in depthcharge, we only configure
control pins as output pin and set them power-off in the coreboot
stage.

BRANCH=none
BUG=none
TEST=Saw DEV screen during boot process.

Change-Id: I3ed95e133417194ec8e774f42770bc61d879295f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e9628781801943903ba99ba1071aa374c6fc0754
Original-Change-Id: Ifd101f3e08698561d8516d83bc7d502d210e3b66
Original-Signed-off-by: YH Huang <yh.huang@mediatek.com>
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292686
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13093
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22 19:37:54 +01:00
Koro Chen 9733ba5bd0 google/oak: configure audio
BRANCH=none
BUG=none
TEST=build and verified pass on oak board

Change-Id: I01eb059a3525bbbc5d17335cf43bc01be4355142
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bc2bb9f5b461ec848df8aba07940b895401004f8
Original-Change-Id: I848468cec04a36659fbb4b898dff9368305d72ac
Original-Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292683
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13092
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22 19:37:40 +01:00
Koro Chen 64a6b9229a mediatek/mt8173: configure audio
BRANCH=none
BUG=none
TEST=build and verified pass on oak board

Change-Id: I2680f6b87614362dffb27490bdeedf7125006c3f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bc2bb9f5b461ec848df8aba07940b895401004f8
Original-Change-Id: I848468cec04a36659fbb4b898dff9368305d72ac
Original-Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292683
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13091
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22 19:37:33 +01:00
Koro Chen 5d7c38ffa9 mediatek/mt8173: add APLL clock setting
Add a new function mt_pll_set_aud_div() to set APLL for audio I2S.
The function is called by mainboard's configure_audio().

BRANCH=chromeos-2015.07
BUG=chrome-os-partner:41507
TEST=build and verified pass on oak board

Change-Id: Ia3c2f250627028422a7427b93d78d49545eb7a75
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bb18943f5e74af7723bd4e01d4da96c0b153a0f6
Original-Change-Id: I7996a8048f2e54ab09093cca3c8bc7447b61170f
Original-Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/297225
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13090
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22 19:37:15 +01:00
CC Ma 0c22084ec0 mediatek/mt8173: Add mtcmos power-on control for audio and display
BRANCH=none
BUG=none
TEST=none

Change-Id: Ic046c66c8e314bd61f96c2edbc5d832260590afe
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 84de3a6f1a726938e2318814d6faaf6a7dd29ac0
Original-Change-Id: If29f28a092617532dd73e71e0dbe24fd930c3bf8
Original-Signed-off-by: CC Ma <cc.ma@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292677
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12617
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2016-01-22 19:37:05 +01:00
Tianping Fang 11f4a297c0 mediatek/mt8173: Add RTC driver
BUG=none
TEST=emerge-oak coreboot
BRANCH=none

Change-Id: I03740ce1afeb8607891fff61110a40dd98b80bdc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9b0cc22cb9e2010e28e854d9984c11149a71ae0b
Original-Change-Id: I6d6482a75cc40ed6183ee115d5d866257afa24af
Original-Signed-off-by: Tianping Fang <tianping.fang@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292676
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12616
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2016-01-22 19:36:46 +01:00
Liguo Zhang d95a463e49 google/oak: Disable vboot mock data, now that I2C is functional
BUG=none
TEST=emerge-oak coreboot
BRANCH=none

[pg: split into multiple commits]

Change-Id: I7a635c57ba271c8f568bd3334929acdf6a058ce8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2a3d867fd1e547cadc6c947f38082fddc2265d32
Original-Change-Id: I4f3a9b403b949d8ae8e3c393cc9441fb66ea5f1d
Original-Signed-off-by: liguo.zhang <liguo.zhang@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292667
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13078
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22 19:34:42 +01:00
Liguo Zhang 5a899e92f1 mediatek/mt8173: Add I2C driver
BUG=none
TEST=emerge-oak coreboot
BRANCH=none

[pg: split into multiple commits]

Change-Id: If2cac5aecc5675048e0e2d28897b1a82e099de7d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2a3d867fd1e547cadc6c947f38082fddc2265d32
Original-Change-Id: I4f3a9b403b949d8ae8e3c393cc9441fb66ea5f1d
Original-Signed-off-by: liguo.zhang <liguo.zhang@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292667
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12615
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22 19:33:58 +01:00
Jimmy Huang 7119222cfa google/oak: Enable MMU support
BRANCH=none
BUG=none
TEST=build pass

[pg: split into multiple commits]

Change-Id: I6e165cfa6a8345de3d8d5461a75d5ed626ece4ef
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3ee2a20ec56359e917bb8f4825846c54d4f6276a
Original-Change-Id: Iedc81a85569b00524620e9ba128e7d77f17b0405
Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292666
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13077
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22 19:33:03 +01:00
Jimmy Huang 13eada654c mediatek/mt8173: Add MMU support
BRANCH=none
BUG=none
TEST=build pass

[pg: split into multiple commits]

Change-Id: Ib46b243102969e2860479070e19640fb6cb9bdd6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3ee2a20ec56359e917bb8f4825846c54d4f6276a
Original-Change-Id: Iedc81a85569b00524620e9ba128e7d77f17b0405
Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292666
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12614
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22 19:32:49 +01:00
Yidi Lin 8e76f34bf4 mediatek/mt8173: Add gen-bl-img.py for mt8173 bootblock code
The mt8173 boot rom expects the bootblock to be in a certain format.
gen-bl-img wraps our bootblock appropriately.

BUG=none
TEST=emerge-oak coreboot
BRANCH=none

Change-Id: I7486e548d356c5bd27261851f1f1bed620715e91
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fbcd7959e0fda595de91899ace7236037ac833d3
Original-Change-Id: Ib9df440bfa95cf06e8041491ecdb34c357047acd
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292664
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12613
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22 19:32:07 +01:00
Itamar 369ae53ef4 google/oak: Add support for verstage
Add support for verstage

[pg: split original commit into multiple commits]

Change-Id: I8c9fe02f26bf8fa8381a7502a778bed300684986
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2827aa08ff8712c0245a22378f3ddb0ca054255d
Original-Change-Id: I94a9ee2c00e25a37a92133f813d0cd11a3503656
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292662
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13052
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22 19:31:25 +01:00
Itamar 49cb61b41a mediatek/mt8173: Add support for verstage
Add support for verstage
[pg: split original commit into multiple commits]

Change-Id: Ia43bc72a1fb36c6fad5be5654abee5fc19fc4093
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2827aa08ff8712c0245a22378f3ddb0ca054255d
Original-Change-Id: I94a9ee2c00e25a37a92133f813d0cd11a3503656
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292662
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13051
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22 19:31:17 +01:00
Itamar f585af395d mediatek/mt8173: add watchdog driver
[pg: split original commit into multiple commits]

Change-Id: I0dc8d9855c98c077d4a47227de0c504c3a846953
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2827aa08ff8712c0245a22378f3ddb0ca054255d
Original-Change-Id: I94a9ee2c00e25a37a92133f813d0cd11a3503656
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292662
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13050
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-22 19:31:06 +01:00
Itamar ab0df6d5a4 arch/arm64: Extend verstage
Add more code to verstage

[pg: split downstream commit into multiple commits]

Change-Id: I578a69a1e43aad8c90c3914efd09d556920f728e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2827aa08ff8712c0245a22378f3ddb0ca054255d
Original-Change-Id: I94a9ee2c00e25a37a92133f813d0cd11a3503656
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292662
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12612
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22 19:30:56 +01:00
Leilk Liu 261059479a google/oak: Enable SPI support
BUG=none
TEST=emerge-oak coreboot
BRANCH=none

[pg: split into multiple commits]

Change-Id: I19f970db40fb8563ef1b782a9606ca3766ef2ac5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 41acc14e9fe54924d20e4e5a2d1519251f0e1c87
Original-Change-Id: I2559be4191da9af523944563729171bd92a86cd0
Original-Signed-off-by: Leilk Liu <leilk.liu@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292661
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13076
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22 19:29:13 +01:00
Leilk Liu 1dda32bb13 mediatek/mt8173: Add SPI support
BUG=none
TEST=emerge-oak coreboot
BRANCH=none

[pg: split into multiple commits]

Change-Id: I82d982b40dd0bfaa7770a6b08c70b20337a46955
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 41acc14e9fe54924d20e4e5a2d1519251f0e1c87
Original-Change-Id: I2559be4191da9af523944563729171bd92a86cd0
Original-Signed-off-by: Leilk Liu <leilk.liu@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292661
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12611
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22 19:27:36 +01:00
T.H.Lin e91e70cb92 Cyan: Update DPTF parameters for higher temperature
TEST=Run DPTF
CQ-DEPEND=CL:12729

Original-Reviewed-on: https://chromium-review.googlesource.com/295478
Original-Tested-by: T.H. Lin <T.H_Lin@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Ifa58ad72105d377c00df577f0e16ff1148b70119
Signed-off-by: T.H. Lin <T.H_Lin@quantatw.com>
Reviewed-on: https://review.coreboot.org/12747
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-22 19:22:48 +01:00
Martin Roth 5942e065f8 Kconfig: Recommend not enabling UPDATE_IMAGE option
We just had a user who spent a fair amount of time debugging a
failing build due to this option being enabled.  Add a little
guidance that it probably shouldn't be enabled in the help text.

Change-Id: I9339e442876c1fcd18ea564041c6cc1201c18ae5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13066
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-22 19:22:07 +01:00
Werner Zeh c0fb361be8 build system: Add option for auto generated cbfs attributes
Add a new Kconfig variable to enable the generation of
position and alignment attributes for cbfs files which
has constraints on this parameters.
In addition,  modify Makefile.inc to support that option.

Change-Id: Ibd725fe69a4de35964bdb2dde106d9a7c37ffb47
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/12968
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-01-22 19:15:08 +01:00
Duncan Laurie 27807c66ee purism/librem13: Add support for Purism Librem 13 mainboard
This adds support for booting the Purism Librem 13 mainboard
with coreboot, using binaries extracted from the original BIOS
and from a Broadwell Chromebook.

The following features have been tested on Ubuntu 15.10:
- Input: Keyboard and Trackpad
- SATA: Internal HDD and M.2 NGFF
- Network: WiFi and Ethernet
- USB: Bluetooth, Camera, SD Card, Ports (1xUSB2 and 1xUSB3)
- Video: Internal panel and HDMI port
- Internal speakers and microphone (headphones do not work)
- EC handling for battery, AC, lid, special keys

These binaries are extracted from the original BIOS:
- VGA BIOS
- Management Engine
- Intel Firmware Descriptor

These binaries are extracted from a Broadwell Chromebook BIOS:
- MemoryInit reference code binary
- SiliconInit reference code binary

This was developed and tested on an Librem 13 device.  For those
who may want to do more development you can use EHCI debug and the
right USB port to get coreboot output.

Change-Id: Ia72e2d7ddc8ba5eef63819e5677122a5a5c705d8
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/13026
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2016-01-22 19:13:14 +01:00
Felix Durairaj 5f92a5a295 lib: Implement framework for retrieving WiFi regulatory domain
Platforms that need to initialize WRDD package with the regulatory domain
information should implement function wifi_regulatory_domain.
A weak implementation is provided here.

Original-Reviewed-on: https://chromium-review.googlesource.com/314384
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Tested-by: Hannah Williams <hannah.williams@intel.com>

Change-Id: I84e2acd748856437b40bbf997bf23f158c711712
Signed-off-by: fdurairx <felixx.durairaj@intel.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/12744
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22 16:12:17 +01:00
Felix Durairaj 15184e081a soc/braswell: Add method for Wifi regulatory domain
Get the WRDD domain code from VPD and put it in global nvs.
WRDD method in wifi.asl returns this value from global nvs.
This wifi.asl should be included in dsdt.asl under the root port where wifi
module resides.

Original-Reviewed-on: https://chromium-review.googlesource.com/314373
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Commit-Queue: Hannah Williams <hannah.williams@intel.com>

Change-Id: I809d28f10e80681471a785e604df102fb943a983
Signed-off-by: fdurairx <felixx.durairaj@intel.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/12745
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-22 16:04:55 +01:00
Kane Chen 8ff4308243 intel/strago: Set POWER_SOURCE_CONFIG in devicetree.cb
SVID config set to  SVID_PMIC_CONFIG

BUG=none
BRANCH=none
TEST=build, boot to OS and check the register is set properly

Change-Id: If63b8112d4da0347c3a2c4c6d82b12a1f618291c
Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/308576
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13117
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22 14:16:23 +01:00
Hannah Williams 530e1f7455 google/cyan: Add Wifi regulatory method
WRDD method in wifi.asl returns the regulatory domain code. This value 
is read from VPD in wifi_regulatory_domain() and saved to global nvs if
CONFIG_HAVE_REGULATORY_DOMAIN is enabled. It returns default code if 
CONFIG_HAVE_REGULATORY_DOMAIN is not enabled.

Change-Id: I6e96bdf0fe93ae30a3afdcb63a0f89ce21023704
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/13055
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22 14:14:52 +01:00
Alexandru Gagniuc e223e895a8 lib/Makefile.inc: Link hexdump.c in the bootblock as well
Change-Id: Id58f252e238cc3eb3fe9632493642d2a37c2a772
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/12873
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-01-22 14:13:51 +01:00
Hannah Williams 822fb87737 intel/strago: Add method for Wifi regulatory domain
WRDD method in wifi.asl returns the regulatory domain code. This value 
is read from VPD in wifi_regulatory_domain() and saved to global nvs if
CONFIG_HAVE_REGULATORY_DOMAIN is enabled. It returns default code if 
CONFIG_HAVE_REGULATORY_DOMAIN is not enabled.

Original-Reviewed-on: https://chromium-review.googlesource.com/315131
Original-Tested-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I52e0a052d31f36c6dc04e6a0953456350e7d86c3
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/12746
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-22 14:12:37 +01:00
Alexandru Gagniuc dc6c43182e lib/hexdump: Refactor to skip lines with all ones as well
We already do this for lines with all zeroes, so it makes sense to
treat all ones the same, for symmetry.

Change-Id: I4b637b07a49e0c649331aa200995b474dd9a2682
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/12872
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-01-22 14:10:28 +01:00
Martin Roth 95f33f4e7e src/Kconfig: Indent with tabs instead of spaces
Change-Id: I47776d842b8d684fc11ac448b751892ee2bc5ecc
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13116
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-01-22 14:05:41 +01:00
Duncan Laurie 9cfb40adb7 skylake mainboards: Enable CONFIG_VBOOT_EC_SLOW_UPDATE
Updating EC+PD takes long enough to update that it is good to
show the "critical update" screen when doing an EC/PD update.

BUG=chrome-os-partner:49650
BRANCH=glados
TEST=Build and boot on chell in normal mode with an EC update payload
and ensure that it reboots to enable graphics, shows the "critical
update" screen, and then reboots to disable graphics init again.

Change-Id: I436b96b95595b68273e594bdcfe2db0789ee26b2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 08e45decd066f8f57ad103ff8b76cb7a916afa9e
Original-Change-Id: Ie250f4531437e4a0ce14b5aeb0fe564e9461fe4d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/322783
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13075
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22 13:05:46 +01:00
Duncan Laurie 1249f056c1 intel/fsp1_1: Fix for passing VBT when vboot requests it
In order to support vboot requesting graphics support in normal
mode the VBT needs to be passed to FSP when it is requested
outside of the usual developer/recovery path.

To make this integrate cleaner use the generic bootmode provided
display_init_required() function instead.  Also have it print a
message indicating when it does not pass VBT to GOP so it is
easier to see what happened in the console logs.

BUG=chrome-os-partner:49560
BRANCH=glados
TEST=Enable EC_SLOW_UPDATE on chell and test that when vboot
requests graphics support in normal mode FSP will get passed VBT
and bring up the panel.

Change-Id: I07bc54d37d687134b21baa60b5c278b5041241cf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 41efd322951b8f3a8a687944832bfd89fd3014ca
Original-Change-Id: I1b68760eabbf3af1d962cb2a3199e504a7852042
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/322782
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13074
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22 13:04:29 +01:00
Duncan Laurie 6324de17ab vboot2: Handle slow EC SW sync and graphics driver loading
Add flag handling for CONFIG_VBOOT_EC_SLOW_UPDATE to indicate
to vboot that it should show the "critical update" screen during
software sync for EC+PD.

In order to make this work on x86 where we do not run graphics
init in the normal path add handling for CONFIG_VBOOT_OPROM_MATTERS
and indicate to vboot when the option rom has been loaded.

BUG=chrome-os-partner:49560
BRANCH=glados
TEST=Build and boot on chell in normal mode with an EC update payload
and ensure that it reboots to enable graphics, shows the "critical
update" screen, and then reboots to disable graphics init again.

Change-Id: I5ca46457798a22e9b08aa2febfec05b01aa788f9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6a1bb8572c3485f64b9f3e759288321b44184e66
Original-Change-Id: I9f66caaac57bb9f05bc6c405814469ef7ddf4d0a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/322781
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13073
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22 13:03:27 +01:00
Naresh G Solanki a69d2f4268 intel/skylake: Fix klockwork violation
File: src/soc/intel/skylake/flash_controller.c
 Line: 192
	Variable 'ret' might be used uninitialized in this function.
	Hence initializing it with initial value of zero.

BRANCH=None
BUG=chrome-os-partner:48542
TEST=Built & booted Kunimitsu board.

Change-Id: I4e63612890057a2180f38b2e74419d98b02b70c1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b93ca876912d2336dae25b9b84e56ffb171b215b
Original-Change-Id: Ied8c909f5294d56daddb2806111d477246f98957
Original-Reviewed-on: https://chromium-review.googlesource.com/322082
Original-Commit-Ready: Naresh Solanki <naresh.solanki@intel.com>
Original-Tested-by: Naresh Solanki <naresh.solanki@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13072
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22 13:02:02 +01:00
pchandri f28929d393 intel/skylake: PL2 override changes
Override the default PL2 values with ones recommended by Intel.

BUG=chrome-os-partner:49292
BRANCH=glados
TEST=MMIO 0x59A0[14-0] to find PL1 value (0x78) / 8 Watts = 15W
MMIO 0x59A0[15] to find PL1 enable/disable = Disable
MMIO 0x59A0[46-32] to find PL2 Value (0xC8) / 8 Watts = 25W
Here PL2 is set to 25W and PL1 is disabled.
CQ-DEPEND=CL:321392

Change-Id: I338b1d4879ae1b5f760e3c1d16e379a2baa1c965
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fa6a115227385bef44abfacf58af306c16ed478a
Original-Change-Id: I3bfc50256c9bdd522c984b11faf2903d7c44c81f
Original-Signed-off-by: pchandri <preetham.chandrian@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/322454
Original-Commit-Ready: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Original-Tested-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Preetham Chandrian <preetham.chandrian@intel.com>
Original-Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/13071
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22 13:01:03 +01:00
pchandri f9495eae2c intel/skylake: Thermal Design Power PL1 and PL2 Config Changes
Override the default PL2 values with one recommended by
Intel. Disable PL1 configuration via MMIO register.

BUG=chrome-os-partner:49292
BRANCH=glados
TEST=MMIO 0x59A0[14-0] to find PL1 value (0x78) / 8 Watts = 15W
MMIO 0x59A0[15] to find PL1 enable/disable = Disable
MMIO 0x59A0[46-32] to find PL2 Value (0xC8) / 8 Watts = 25W
Here PL2 is set to 25W and PL1 is disabled.

Change-Id: I10742f91cc7179de1482d42392338976e8082afe
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1b7771ccb34bdff92ffa9870733bd641e4644cdf
Original-Change-Id: Iefa93912008c71b41f2b20465e8acfd42bb6c731
Original-Signed-off-by: pchandri <preetham.chandrian@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/321392
Original-Commit-Ready: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Original-Tested-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/13070
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22 12:59:59 +01:00
David Hendricks 2cd9c05dc1 google/veyron_*: Add dual-rank 2GB Hynix module to SDRAM configs
This is a follow-up to CL:320623 to make veyron DRAM configs
uniform (except for Rialto).

As discussed in chrome-os-partner:43626, the mr[3] value and ODT
are set diffently for Mickey, thus the .inc files for other boards
have mr[3] = 1 and ODT disabled.

BUG=none
BRANCH=veyron
TEST=compile tested for veyron

Change-Id: I61798cfef779b0a3a510fd354ab53ffc63ca6c95
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3b7cea6331bcec8aba09a204060e093d3dd732cb
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: Iacf821645a2dcceaed1c1c42e3e1b1c312b31eab
Original-Reviewed-on: https://chromium-review.googlesource.com/321870
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13109
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2016-01-22 12:59:11 +01:00
Patrick Georgi c8d4abd8ba vboot: Install files into FW_MAIN_A and FW_MAIN_B unless they're for RO
Setup an initial rule to make use of the updatable CBFS regions in fmap.

Change-Id: I1fe1c6e7574854b735760c85590da6e297f6e687
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13060
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-21 19:41:20 +01:00
Patrick Georgi 5d7ab39024 chromeos: import Chrome OS fmaps
These are generated from depthcharge's board/*/fmap.dts using the
dts-to-fmd.sh script.

One special case is google/veyron's chromeos.fmd, which is used for a
larger set of boards - no problem since the converted fmd was the same
for all of them.

Set aside 128K for the bootblock on non-x86 systems (where the COREBOOT
region ends up at the beginning of flash). This becomes necessary
because we're working without a real cbfs master header (exists for
transition only), which carved out the space for the offset.

Change-Id: Ieeb33702d3e58e07e958523533f83da97237ecf1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/12715
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-21 19:40:57 +01:00
Martin Roth a5a628e86b Kconfig: add comments for toolchain choices
- While we're working on fixing clang for coreboot, mark it as not
currently working so that it doesn't look like a reasonable choice.

- Add help on how to make the toolchains

Change-Id: Ib37093ca98d0328fad40dd7886c98d00f78bd58e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13053
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-21 16:50:58 +01:00
Felix Durairaj 5d935b3377 Chromeos: Implement wifi_regulatory_domain using "regions" key in VPD
Implement wifi_regulatory_domain function by getting country code from
VPD

Original-Reviewed-on: https://chromium-review.googlesource.com/314385
Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Hannah Williams <hannah.williams@intel.com>

Change-Id: Ia6a24df110a3860d404d345571007ae8965e9564
Signed-off-by: fdurairx <felixx.durairaj@intel.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/12743
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-21 16:47:11 +01:00
Martin Roth 6720394ffc intel/skylake: remove third paragraph of license header
We had another one that crept in while the linter was broken.

Change-Id: Ie690e2d7fc7ad31b3b674de1618723bb100ac961
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13056
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-21 12:30:00 +01:00
Julius Werner 757943c7d1 memlayout: Fix unified CBFS_CACHE macro
commit a8aef3ac (cbfs_spi: Initialize spi_flash when initializing
cbfs_cache) introduced a bug that makes the rarely-used unified
CBFS_CACHE() memlayout macro break when used in conjunction with
cbfs_spi.c (since that macro does not define a separate
postram_cbfs_cache region). This patch fixes the problem by making all
three region names always available for both the unified and split
macros in every stage (and adds code to ensure we don't reinitialize
the same buffer again in romstage, which might be a bad idea if
previous mappings are still in use).

BRANCH=None
BUG=None
TEST=Compiled for both kinds of macros, manually checked symbols in
disassembled stages.

Change-Id: I114933e93080c8eceab04bfdba3aabf0f75f8ef9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0f270f88e54b42afb8b5057b0773644c4ef357ef
Original-Change-Id: If172d9fa3d1fe587aa449bd4de7b5ca87d0f4915
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/318834
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12933
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-21 09:05:06 +01:00
Lang Zhang aaf2841ff7 google/veyron_mickey: Update Hynix memory configuration
Update Hynix memory configuration for mickey
so that it can boot on Hynix board.

BUG=chrome-os-partner:48637
BRANCH=master
TEST=Boot on mickey hynix board

Change-Id: Ibbf90cf76793005e23a720b97540b268ebf0864d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 071167b667685c26106641e6899984c7bd91e84b
Original-Change-Id: Id63d74cac36b9fd84bdb88969291982e14fa7d01
Original-Signed-off-by: Lang Zhang <kingsley_zhang@asus.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/320623
Original-Commit-Ready: lang zhang <kingsley_zhang@asus.com>
Original-Tested-by: lang zhang <kingsley_zhang@asus.com>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/13048
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-21 09:03:53 +01:00
Alexandru Gagniuc 4e153d6ee7 arch/x86: Add files needed for C environment bootblock on x86
This provides symbols needed by CBFS and FMAP APIs, and allows running
run_romstage() in an x86 bootblock. Note that console-related files
are not added in this patch, as they are not essential for the
functinality on an x86 environment bootbock.

Change-Id: I36558b672a926ab22bc9018cd51aee32213792c2
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: https://review.coreboot.org/12880
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-01-21 05:38:08 +01:00
Alexandru Gagniuc 66bbb3187e */Makefile.inc: Compile files needed by uart8250 in x86 bootblock
These files provide symbols needed by console and uart drivers. This
was not an issue in the past, as we were not setting up a C
environment this early in the boot process.

Change-Id: Ied5106ac30a68971c8330e8f8270ab060994a89d
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/12869
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-01-21 05:37:48 +01:00
Alexandru Gagniuc ee464b17ce console: Simplify bootblock console Kconfig selection logic
Instead of depending BOOTBLOCK_CONSOLE on a set of architectures,
allow the arch or platform to specify whether it can provide a C
environment. This simplifies the selection logic.

Change-Id: Ia3e41796d9aea197cee0a073acce63761823c3aa
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/12871
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-01-21 05:37:27 +01:00
Alexandru Gagniuc cc96624de4 arch/x86/include: Rename bootblock_common to bootblock_romcc.h
This header is only used for the bootblock compiled with ROMCC. As the
follow-on patches introduce a bootblock which does not make use of
ROMCC, rename this header to prevent confusion.

Change-Id: Id29c5bc6928c11cc7cb922fcfac71e5a3dcd113c
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: https://review.coreboot.org/12867
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-01-21 05:37:19 +01:00
Matt DeVillier 89683c0d26 google/tidus: initial upstream migration
Migrate google/tidus (Lenovo ThinkCentre Chromebox) from Chromium
tree to upstream, using google/guado as a baseline.

TEST=built and booted tidus with full functionality

Change-Id: I9d7a976345566bee63226d1a44ba7d5ec137a742
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/12801
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-21 02:47:29 +01:00
Duncan Laurie 5f4ee47c6c ec: Add support for EC used on Purism Librem laptops
This adds basic ACPI support for the EC used on Purism Librem laptops.
The EC firmware appears to use the topstar laptop interface that has
support in the linux kernel for handling the special keys.

Supported functions:
- Battery information
- AC presence
- Lid switch
- Special keys (after loading topstar-laptop driver in linux)
- EC events for turbo enable/disable when on AC power

Things it does not do:
- EC SMI handling
- Fan is left under EC control

This was developed and tested on a Librem 13 laptop, and has not
been directly tested on an Librem 15.

Change-Id: Ib85a24e4cc8ab09b14147060043cff372863c2d1
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/13025
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-21 02:31:34 +01:00
Duncan Laurie 8faea7d93d drivers/intel/wifi: Only compile if SMBIOS tables are generated
This driver adds an SMBIOS table for Intel WiFi, but if SMBIOS
table generation is disabled then it should not attempt to
compile or it will fail to find the "get_smbios_data" member
of the device_operations structure.

Tested by compiling and booting on purism/librem13 with
SMBIOS table generation disabled.

Change-Id: Iac6c265da7daae1be4d7585dab7b54561ff4e631
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/13046
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-21 02:26:26 +01:00
Duncan Laurie 576b7c7264 broadwell: gpio.asl: Make GWAK method serialized
This method creates named objects and must be serialized
to prevent a warning from IASL.

Tested by compiling purism/librem13 which includes this ASL.

Change-Id: Ic043ea479e681d2180421fcf8e0583b62e6fcd71
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/13045
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-21 02:25:30 +01:00
Patrick Georgi b0a2d3c298 lib: compile mdelay for bootblock
Mediatek's bootblock needs mdelay, which depends on a udelay
implementation. Compiling the file for bootblock poses no harm:
Either udelay exists (in which case mdelay is usable) or it doesn't in
which case we see exactly the same kind of build time error (just with
udelay instead of mdelay).

Change-Id: I7037308d2d79c5cb1b05bb2b57a0912ad11cd7a6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13049
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-20 21:47:52 +01:00
Damien Zammit 1533f13d43 sb/intel/i82801gx: Clean up sata.c
This tidies up the setting of the PCS register.
An assumption is made that bit 4 of this register is read-only,
which according to the ICH7 datasheet, it is.

Change-Id: Ia9b7d38a87e26236f6ebc951c169cae12b13139f
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13015
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
2016-01-20 19:16:40 +01:00
Martin Roth 19bb1391bf Kconfig: Remove selects that enable 'choice' symbols
Selecting Kconfig symbols that were created inside a 'choice' block
have no effect.  Remove these so people aren't confused by them.

Change-Id: I7de9131d8d8afb65f86648afb9728f09cb67e122
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12970
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-20 17:11:10 +01:00
Damien Zammit 02f4764bf3 nb/intel/pineview: Use macro names for memory base registers
Change-Id: I0b79ddcf9248c6a6964dd60e30a6ea18e27bc186
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13032
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-20 16:26:22 +01:00
Jacob Laska aad9b6a086 cpu: Fix typo that spelled "allocate" as "allocte."
The error informing the user that the CPU device cannot be
allocated has a typo incorrectly spelling "allocate" as
"allocte".

TEST=Compiled
Change-Id: I2a6bad56133e375e2fd6a670593791414bf0dc2c
Signed-off-by: Jacob Laska <jlaska91@gmail.com>
Reviewed-on: https://review.coreboot.org/13030
Tested-by: build bot (Jenkins)
Reviewed-by: Ben Frisch <bfrisch@xes-inc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-01-20 16:07:49 +01:00
Nico Huber 967881d0b6 lenovo/t400: Revise onboard IRQ routing
All southbridge interrupt pin and routing registers (D*IP and D*IR)
are left at their default values (see ICH9 datasheet) and this file
just has to reflect them.

Change-Id: I1e9732e178bb8422b284d80d9f3d34b72f2e2415
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/13040
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-19 21:42:27 +01:00
Martin Roth 6313bc7731 arch/x86/Makefile.inc: Add a comment to fix syntax highlighting
Trivial fix for syntax highlighting in editors.  Some get confused by
the double quote that doesn't have a close quote and stop highlighting
at that point.  This comment closes the quote and the paren pair so
that they can recover.

Change-Id: I2bdb7c953a86905fc302d77eb9ad1200958800b7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13017
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-19 18:07:23 +01:00
Kane Chen 54093e4fce Braswell: add code to support customization of I2C data hold time
The I2C data hold time can be vary on different boards/devices.
So, it needs to be customized by boards/devices

TEST=compile ok and check IC_SDA_HOLD is changed if the hold time
     is defined in onboard.h

Original-Reviewed-on: https://chromium-review.googlesource.com/308623
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I66c799de400670916cebbcb529d4f59d5b0f081b
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/12740
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19 17:41:20 +01:00
Naresh G Solanki a1b3547f0f intel/skylake: Fix issues found by klockwork
src/soc/intel/skylake/acpi.c
  Function cbmem_find may return NULL, check before using its result.

src/soc/intel/skylake/flash_controller.c
  Remove dead code: spi_claim_bus is a no-op, always returning 0.

src/soc/intel/skylake/gpio.c
  Check for NULL before using pointers.

src/soc/intel/skylake/igd.c
  Don't copy 0-termination of signature string.

src/soc/intel/skylake/lpc.c
  Don't check unsigned >= 0.

src/soc/intel/skylake/systemagent.c
  Explicitly cast result to 64bit.

BRANCH=None
BUG=chrome-os-partner:48542
TEST=Built & booted Kunimitsu board.

Change-Id: I6cbf4f78382383d3c8c3b15f66c5898ab5bf183a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d98a8cdd3d095a6943c0e104cd4938639a62bd14
Original-Change-Id: Id2a31402618f4c9f6f53525ebcf6b71fd67428db
Original-Signed-off-by: Naresh G Solanki <Naresh.Solanki@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/317522
Original-Commit-Ready: Naresh Solanki <naresh.solanki@intel.com>
Original-Tested-by: Naresh Solanki <naresh.solanki@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12991
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2016-01-19 17:23:42 +01:00
Yong Zhi bdab9f787c intel/kunimitsu: Add device properties for Nuvoton codec
This patch added default values for two SAR properies
introduced by updated nau8825 codec driver. Also updated
sar-threshold to improve button detection accuracy.

Bug=chrome-os-partner:49394
BRANCH=glados
TEST=Build for kunimitsu. Tested with 4-button headset

Change-Id: I4096c60be54819d0ab2bf4b72a1e403f88d96af0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4b747e9dffed1c51131f0028879d4c22283c8ec5
Original-Change-Id: I3e222ff58c1483e261acf1cea297164966bf8689
Original-Signed-off-by: Yong Zhi <yong.zhi@intel.com>
Original-Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/322241
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13014
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19 16:41:44 +01:00
Benson Leung b7090ee1d0 google/chell: Adjust nuvoton 8825 button thresholds, add properties
Set "nuvoton,sar-threshold" property to thresholds
based on tuning with the Android Wired Headphone
Compatibility Kit and Chell EVT.

Also set properties nuvoton,sar-compare-time and
nuvoton,sar-sampling-time.

The values of compare and sampling time align with
the ones from this CL:
https://chromium-review.googlesource.com/306372

Signed-off-by: Benson Leung <bleung@chromium.org>

BUG=chrome-os-partner:49333
BRANCH=none
TEST=Run evtest, selecting the input event for sklnau8825adi
Using the Nominal headphones from the kit, check that the
buttons for "KEY_VOLUMEDOWN", "KEY_VOLUMEUP", "KEY_MEDIA",
and code 582 (?) (should be voice search, but evtest doesn't understand)
All of these buttons should work properly.

Change-Id: I43dc1957f7d95744f41039a306d323806e66c56a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2bb545500afeb5b4fa0d1cd02dbf6453f19901ab
Original-Change-Id: I126aae1e5ed1b9e1a2429e8c94fe08b3ba3ca736
Original-Reviewed-on: https://chromium-review.googlesource.com/322243
Original-Commit-Ready: Benson Leung <bleung@chromium.org>
Original-Tested-by: Benson Leung <bleung@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13013
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19 16:39:47 +01:00
Mike M Hsieh bbef4bde2e google/chell: Modify DqsMap
Modify Dqs Byte Swizzling for channel 0 to honor chell's memory routing

BUG=chrome-os-partner:48986
BRANCH=glados
TEST=verified on chell system
Signed-off-by: Mike Hsieh <mike.m.hsieh@intel.com>

Change-Id: Ic0485526bc1378e329c5eb0eeb57ff67a9501e86
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b60241e63381974655f5df5afcd913e95c17682b
Original-Change-Id: I641502e8d303fa59e0f668d581745379e1ef4853
Original-Reviewed-on: https://chromium-review.googlesource.com/321524
Original-Commit-Ready: Duncan Laurie <dlaurie@chromium.org>
Original-Tested-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13012
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19 16:39:02 +01:00
Duncan Laurie 31fa749b4d google/chell: Add new memory part for DVT build
After comparing datasheets it appears to have the same geometry
and timings as the K4E6E304EE-EGCF part with just a new part number.

BUG=chrome-os-partner:49357
BRANCH=glados
TEST=build and boot on chell EVT (new part is not used until DVT)

Change-Id: Ia1e67080b1d79600e00c3ea8bee088ecafea2ab2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fb1488ca5ff780b5f1f937dbf0d23610c28204b2
Original-Change-Id: I09e1ce1a45a217afc88f422cf7db7924fad6b6f9
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/321956
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13011
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-01-19 16:35:24 +01:00
Naresh G Solanki 8c78d0a3c9 intel/kunimitsu: Set I2C[4] port voltage to 1.8v
As the audio card needs 1.8V I2C operation. This patch adds
entry into devicetree.cb to set I2C port 4 operate at 1.8V.

Branch=None
Bug=chrome-os-partner:47821
Test=Built & booted kunimitsu board. Verified that I2C
port 4 is operating at 1.8V level

CQ-DEPEND=CL:*242225, CL:*241206, CL:315167

Change-Id: Ida69b885737aef0cfcf6a6ca21b3650169e614d9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 990df9c1c65e75aae0a1329ead3790e78021b804
Original-Change-Id: Ifbb65e3d83561b52cc18e48b89d146c2f88f289b
Original-Signed-off-by: Naresh G Solanki <Naresh.Solanki@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/315168
Original-Commit-Ready: Naresh Solanki <naresh.solanki@intel.com>
Original-Tested-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13010
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19 16:34:43 +01:00
Duncan Laurie a0ee532af7 google/chell: Set FSP params for min assertion widths and serirq
- Enable serial irq configuration in FSP.
- Set minimum assertion width values for FSP to configure.
- Set I2C4 voltage to 1.8V.
- Enable SaGv feature to dynamically train memory frequency.

BUG=chrome-os-partner:47688
BRANCH=none
TEST=build and boot on chell EVT

Change-Id: If6955c9ee4f08d1ebc6e98e0ba0786073919856f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7403149299ec2c6c66c2066a5dd8294608e71409
Original-Change-Id: Ia182396ad4eb7a283e183fce7c50c98f6d2de57c
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/321212
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13009
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19 16:32:57 +01:00
Duncan Laurie ec19fccf76 google/glados: Set FSP params for min assertion widths and serirq
- Enable serial irq configuration in FSP.
- Set minimum assertion width values for FSP to configure.
- Set I2C4 voltage to 1.8V.
- Enable SaGv feature to dynamically train memory frequency.
- Disable Deep S3 to match chell so DeepSx story is consistent
on skylake-y boards.

BUG=chrome-os-partner:47688
BRANCH=none
TEST=emerge-glados coreboot (tested on chell board)

Change-Id: Ied6bda6a3f2108df7167e0970abe71977d8d2a5c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fbf353288edc9629ad03b17d0a582e3042d5a5e1
Original-Change-Id: I1619dd5316060793f38b74f8f0bcaf23d8ab2552
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/321211
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13008
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19 16:29:00 +01:00
Duncan Laurie 07651fa3fb google/chell: Reduce power-on keyboard backlight brightness to 25%
The keyboard backlight is very bright at 100% so be more
subtle when turning it on at boot time.

BUG=chrome-os-partner:40635
BRANCH=none
TEST=build and boot on chell EVT

Change-Id: I3925b94b4a455eb7d3bbb6eee414d21cf6d3bb93
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 52da1456527bfa6e0a3290c87c4886e2b3111e21
Original-Change-Id: Ia3412b4052c96f5de8e8aef59f69f6b346b9aca8
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/321210
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13007
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-19 16:28:30 +01:00
Naresh G Solanki f1eac38bda intel/skylake: Adding provision to set voltages to the I2C ports
This patch adds an UPD/VPD parameter to set voltages to the
I2C ports individually via devicetree.cb

BRANCH=None
BUG=chrome-os-partner:47821
TEST=Tesed by setting voltage via devicetree.cb
and verified voltage level using a DSO probe.

CQ-DEPEND=CL:*242225, CL:*241206

Change-Id: Iaeb1ab3f9724aa1139c876dc63250469661d8439
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fc73b98529ad1eb187f97a4177beda4224f473d1
Original-Change-Id: Ib477ad26667ef59cd298b5e20a68a8c68d85bd8d
Original-Signed-off-by: Naresh G Solanki <Naresh.Solanki@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/315167
Original-Commit-Ready: Naresh Solanki <naresh.solanki@intel.com>
Original-Tested-by: Naresh Solanki <naresh.solanki@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13006
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-19 16:26:43 +01:00
Subrata Banik c6950576af google/lars: Set Correct RCOMP Target for LARs EVT boards
Below are the correct RCOMP Target Values:

Samsung K4E6E304EB part = {100, 40, 40, 21, 40}

The rest of the DIMMs should have RCOMP set to
{100, 40, 40, 23, 40}

LARs EVT has new DIMM configurations, and the earlier RCOMP
settings are not correct for the newly added DIMM cards,
causing reboot issues.
With this patch all the DIMMs get the required values programmed.

BRANCH=None
BUG=None
TEST=Built for Lars EVT SKU1/2/3 and verified Boot to OS.
No Reboot after this change.

Change-Id: I5fa5ce47b4b47198b0ae8d0b57f7729cb57d23bf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d29cc8a4ad9bc2b7680e4df146ce281738e4a3c4
Original-Change-Id: I15195b748213553907ff22dbc74651d70f3c7bb6
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/320527
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13005
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-19 16:25:22 +01:00
david 3e5c12691f google/lars: Enable eMMC HS400 mode
Kingston eMMC can now run under HS400 mode.

BUG=chrome-os-partner:48017
BRANCH=none
TEST=run consecutive boot 100 times on Lars proto Kingston SKU, and
MMC errors didn't happen.

Change-Id: I3c16db6111273fbbabbfba1c315edc780fe23525
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ac474bd7bd33f11904a27691e9eb61bdaf212c6b
Original-Change-Id: I9e47b6ba64ac94acff7673fca86fa62bfb30edd9
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/320194
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/13004
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-19 16:24:51 +01:00
Ryan Lin 0691f25e53 google/chell: Enable eMMC HS400 mode
Hynix eMMC can now run under HS400 mode.

BUG=chrome-os-partner:47647
TEST=run consective boot 100 times on Chell EVT Hynix SKU, and
MMC errors didn't happen.
BRANCH=none

Change-Id: Icb6fc03d0510d2c5aeb5b08ed7189e954ab39a72
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9966c430a508a13cf1a617f485a48866bec161ca
Original-Change-Id: I6bec88f5c2813131a693ddba5523a9d43b2ebd45
Original-Signed-off-by: Ryan Lin <ryan.lin@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/319627
Original-Commit-Ready: Duncan Laurie <dlaurie@chromium.org>
Original-Tested-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13003
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-19 16:24:13 +01:00
david bc58a878cd google/lars: Enable SaGv feature
This change enables SaGv feature for skylake
platform. As a result of this patch the skylake
platform will train memory at both low & high
frequency points. This will be used to
dynamically scale the work point
(voltage/frequencies).

The value "3" here means enable. Following
is the table for same.

0=Disabled (SaGv disabled)
1=FixedLow (Fixed to low frequency)
2=FixedHigh (Fixed to High frequency)
3=Enabled( SaGv Enabled.Dynamically changes)

BRANCH=None
BUG=chrome-os-partner:48534
TEST=Build and boot lars

Change-Id: I82b1a428d2d3dce47f46de576f677cf2249b6b5d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8e252123cc73543d0f1b320af9d8873f99a45ab1
Original-Change-Id: I1a545ff2f38df23964378c0d833e29006b2c5557
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/320022
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-by: Haridhar Kalvala <haridhar.kalvala@intel.com>
Reviewed-on: https://review.coreboot.org/13002
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19 16:23:34 +01:00
haridhar 07e9e6f737 intel/skylake: do not save MRC data in recovery mode
If the system is in recovery don't bother saving MRC training data.

BRANCH=None
BUG=chrome-os-partner:48534
TEST=Built for kunimitsu.
Results show MRC data is not saved
in recovery mode.

Change-Id: I236b7fe1860ac86722562c9a749067496dfe98f8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: acca68bb5fece58549d762bfaef3e9f2eb0d3066
Original-Change-Id: Idb0cd7d7c789a58d05160968f6448cb59882056c
Original-Signed-off-by: haridhar <haridhar.kalvala@intel.com>
Original-Signed-off-by: Somayaji, Vishwanath <vishwanath.somayaji@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/319221
Original-Commit-Ready: Haridhar Kalvala <haridhar.kalvala@intel.com>
Original-Tested-by: Haridhar Kalvala <haridhar.kalvala@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-by: Haridhar Kalvala <haridhar.kalvala@intel.com>
Reviewed-on: https://review.coreboot.org/13001
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19 16:23:06 +01:00
Rizwan Qureshi fefce18533 intel/kunimitsu: Enable FspSkipMpInit token
MP init is already handled in coreboot, but it is also part of FSP
FSP has a implemented a provision to allow FSP to skip MP init and
let coreboot handle it.

BRANCH=none
BUG=chrome-os-partner:44805
TEST=Build and booted in kunimitsu with SkipMpInit enabled from CB.

CQ-DEPEND=CL:310192

Change-Id: Idd9b1424f23765ce227005a322ac72d9e9fc841a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5c52d0f0cc5d480c87fababc3316009e3ade6e45
Original-Change-Id: I9d92046d0237680b8d562814a9a605a36efb9516
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/312926
Original-Commit-Ready: Preetham Chandrian <preetham.chandrian@intel.com>
Original-Tested-by: Preetham Chandrian <preetham.chandrian@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12992
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19 16:22:06 +01:00
Barnali Sarkar 497ff3ce7c google/chell: Enable FspSkipMpInit token
MP init is already handled in coreboot, but it is also part of FSP
FSP has a implemented a provision to allow FSP to skip MP init and
let coreboot handle it.

BRANCH=none
BUG=chrome-os-partner:44805
TEST=none

CQ-DEPEND=CL:319353

Change-Id: I22c1add182b299e2ad9d413bc13c5a5acc6a3179
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ccf89c9d1fe18b74c385e7d12a6aef5b63d7b243
Original-Change-Id: I53b754fd10a140588ad67d9292d9bc04a6d43677
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/319194
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13000
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19 16:21:29 +01:00
Barnali Sarkar 8bd6bd26ed google/lars: Enable FspSkipMpInit token
MP init is already handled in coreboot, but it is also part of FSP
FSP has a implemented a provision to allow FSP to skip MP init and
let coreboot handle it.

BRANCH=none
BUG=chrome-os-partner:44805
TEST=Build and booted in Lars with SkipMpInit enabled from CB

CQ-DEPEND=CL:319353

Change-Id: Ib35d9072b883592d22466dfeb1fd45403c0479d4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 91cf59ea7865568eca2ce242d81c4c486076d5ac
Original-Change-Id: Ibb46fc6bc7e862c9ea8bc9f9b0d508c3707282a2
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/319257
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12999
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19 16:20:52 +01:00
haridhar 5535cead09 intel/skylake: Disable SaGv in recovery mode
This patch disables the SaGv feature in recovery mode. Since the memory
training happens at both low and high frequency points when SaGv is
enabled, recovery mode boot time increases by 5 seconds. To reduce this
5 second increase, the SaGv feature is disabled in recovery mode.

The value "0" here means SaGv disable.
Following is the table for same.

0=Disabled (SaGv disabled)
1=FixedLow (Fixed to low frequency)
2=FixedHigh (Fixed to High frequency)
3=Enabled (SaGv Enabled. Dynamically changes)

BRANCH=None
BUG=chrome-os-partner:48534
TEST=Built for kunimitsu.
Results show recovery mode boot time
is not affected (not increased).

Change-Id: I77412a73a183a5dbecf5564a22acc6e63865123e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: dc586079052acf9af573b68dff910386cd43484d
Original-Change-Id: Ice3e1a630e119d40d3df52e3a53ca984e999ab0b
Original-Signed-off-by: haridhar <haridhar.kalvala@intel.com>
Original-Signed-off-by: Somayaji, Vishwanath <vishwanath.somayaji@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/315759
Original-Commit-Ready: Haridhar Kalvala <haridhar.kalvala@intel.com>
Original-Tested-by: Haridhar Kalvala <haridhar.kalvala@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-by: Haridhar Kalvala <haridhar.kalvala@intel.com>
Reviewed-on: https://review.coreboot.org/12998
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-19 16:20:12 +01:00
haridhar f991bf071a intel/skylake: Enable SaGv feature
This change enables SaGv feature for skylake
platform.As a result of this patch the skylake
platform will train memory at both low & high
frequency points.This will be used to
dynamically scale the work point
(voltage/frequencies).

The value "3" here means enable. Following
is the table for same.

0=Disabled(SaGv disabled)
1=FixedLow(Fixed to low frequency)
2=FixedHigh(Fixed to High frequency)
3=Enabled(SaGv Enabled.Dynamically changes)

BRANCH=None
BUG=chrome-os-partner:48534
TEST=Built for kunimitsu.
Tested on D1 silicon.

Change-Id: I2892d631d64495e6aed453af4fd526f4bf5bed68
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8e09d1a22927f5fcddd6c0be3f9edf3dcb8729be
Original-Change-Id: I32a7a53805068a52b381affaf061d69062cd8651
Original-Signed-off-by: haridhar <haridhar.kalvala@intel.com>
Original-Signed-off-by: Somayaji, Vishwanath <vishwanath.somayaji@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/315806
Original-Commit-Ready: Haridhar Kalvala <haridhar.kalvala@intel.com>
Original-Tested-by: Haridhar Kalvala <haridhar.kalvala@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Haridhar Kalvala <haridhar.kalvala@intel.com>
Reviewed-on: https://review.coreboot.org/12997
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19 16:19:25 +01:00
david 425a466948 google/lars: SPD changes for EVT board
Update Memory IDs for EVT board

BUG=None
BRANCH=lars
TEST=Build and boot lars

Change-Id: I8c0c731fc3a8eec0cb558137e9db90170debf2c6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a95fbf063b2e41d551171228a1ea8cbcfdcaecc8
Original-Change-Id: I2be8a7db99f17ea2968d7e4c5de83cc3e4cbcd14
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/319622
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12996
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19 16:19:02 +01:00
Shaunak Saha d5fd2dddde soc/braswell: Remove the unneccessary functions from pcie.c
Functions in file pcie.c is not needed.

TEST=Boot and test wifi and video playback

Original-Reviewed-on: https://chromium-review.googlesource.com/298965
Original-Tested-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

Change-Id: I70337c0fc61c221330836ef17f6cefea8c5f0f11
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/12737
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19 04:29:59 +01:00
Sathya Prakash M R 1ed1659367 intel/skylake: Add support for IV feedback loop capture blob
SSM4567 smart speaker needs Current and Voltage sensing to be
captured and reported to the algorithm.
This needs 4 CH capture blob.

BUG=chrome-os-partner:48625
BRANCH=none
TEST=Built and booted. Verified CBFS locates
     the blob.
CQ-DEPEND=CL:*242635

Change-Id: Ie13622da9a9a8ce5930d32e52ddaf2e0d4862895
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 06f1a501dcb3fa6102eccdb3e24f9011b7869ab0
Original-Change-Id: I7b65b7582b619be53544ebbe4b3ea65398d32a34
Original-Signed-off-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/319020
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12995
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19 02:43:04 +01:00
Martin Roth e369010ab8 arch/x86: Indent using tabs not spaces
No functional changes - just whitespace fixes.
Signed-off-by: Martin Roth <martinroth@google.com>

Change-Id: I8ffa87240bcbd3d657ed9dc619b5e5bf9de734d7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12853
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-19 00:36:48 +01:00
Martin Roth a9e1a2235f device/oprom/yabel: Update BSD license headers
All of the yabel files are BSD licensed.

Change-Id: Ibe0b3bb67a96c57b5d693676f5e8f19b6bed90fa
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12972
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-18 18:23:52 +01:00
Damien Zammit f564606170 nb/intel/pineview: Fix decode_pciebar()
Fixes bug that decode_pciebar() function was bypassed due
to PCI_DEV(0,0,0) being detected as zero and function returning 0.

Change-Id: Ia79bcebbe3ba36f479cbb24dbbb163a031d9c099
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13031
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2016-01-18 15:08:33 +01:00
Barnali Sarkar a67526e61d google/glados: Enable FspSkipMpInit token
MP init is already handled in coreboot, but it is also part of FSP.
FSP has a implemented a provision to allow FSP to skip MP init and
let coreboot handle it.

BRANCH=none
BUG=chrome-os-partner:44805
TEST=none

CQ-DEPEND=CL:319353

Change-Id: I81c54582a3c980ecdcf329347bcd5982802d681c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e60ee81acaeb1062a31a3e78ed2ba4ccfe816ec5
Original-Change-Id: I71dd07559dffb7886e489274ffc8e71686ca730f
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/319370
Original-Commit-Ready: Preetham Chandrian <preetham.chandrian@intel.com>
Original-Tested-by: Preetham Chandrian <preetham.chandrian@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12994
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18 12:28:07 +01:00
Barnali Sarkar c019cec4c0 intel/skylake: Change in UPD name from SkipMpInit to FspSkipMpInit
Changing the UPD param name from "SkipMpInit" to "FspSkipMpInit"

BRANCH=none
BUG=none
TEST=Build and booted in kunimitsu with FspSkipMpInit token
enabled from Coreboot.

Change-Id: I5ebe7a1338ac77a62d5aa2e48e083b4fb906bf28
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cdaa95a82bc7e90637c6b90e33d88d040e085f58
Original-Change-Id: Ibdaa3d202f8f6f6f0ca6c6d4c6428f1616572f1d
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/319353
Original-Commit-Ready: Preetham Chandrian <preetham.chandrian@intel.com>
Original-Tested-by: Preetham Chandrian <preetham.chandrian@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12993
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-01-18 12:26:37 +01:00
david 8d66665637 google/lars: Enable ALS connected to EC
Lars has an ambient light sensor connected to the EC which
is presented to the OS as a standard ACPI0008 device.

BUG=none
BRANCH=none
TEST=emerge-lars coreboot

Change-Id: I406b634176dac3f4cf1894e6b386af3306d11ffa
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 37d96458a11c33899f210cc04d3bdab07ec18746
Original-Change-Id: I017aeed1a8684676557e483ffa895dc4bb125d26
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/319364
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12990
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18 12:21:23 +01:00
david 77e9f09937 google/lars: Add keyboard backlight support
BRANCH=lars
BUG=None
TEST=alt+f6, alt+f7

Change-Id: I20d44ae806facf7470ab50d7b9ca4f36404b6ea3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3bf8c26a11e632cc9f4112eace813478fb7ff8ca
Original-Change-Id: Iaa59818f5d2d17eb6759cefa9b6fbfba82bb2fca
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/319270
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12989
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18 12:19:23 +01:00
Rohit Ainapure 244cf2ecda intel/kunimitsu: Set BOOT_BEEP gpio to a default lo
The BOOT_BEEP gpio is used to activate the buffer which
isolates the I2S signals from PCH while doing a beep from depthcharge.
It needs to be lo to deactivate the buffer for audio playback from OS.

BUG=chrome-os-partner:47124
BRANCH=None
TEST=boot depthcharge & test beep with devbeep.
Boot OS and test audio playback.

Change-Id: I047513f6cbe9590820dfe3c369161a157864be97
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d0e04d6792a4511630b8111d0f4a64226042f3e6
Original-Change-Id: I0fa8f425ac413798740343823d026c6300c8eef1
Original-Signed-off-by: Rohit Ainapure <rohit.m.ainapure@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/319220
Original-Commit-Ready: Rohit M Ainapure <rohit.m.ainapure@intel.com>
Original-Tested-by: Michael Rang <michael.rang@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12988
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18 12:17:39 +01:00
Lee Leahy a5244c34b0 intel/fsp1_1: Fix enumeration timestamp and post code
The timestamps and post codes for the beginning of the FspNotify calls
are out of order.  Reverse these entries to fix this error.

BRANCH=none
BUG=None
TEST=Build and run on kunimitsu

Change-Id: Ibfa1ba4b07e31bf3823469ac2dc7deaa8c67deab
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3cd63c56c59337f0ff58fd11a78d08352cf6a04a
Original-Change-Id: I4627860d3ebf446523a5662dbbc8e59153441945
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/318903
Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12987
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18 12:15:40 +01:00
Duncan Laurie a7feb9fa2d intel/skylake: Remove unused devicetree configuration variables
The GPU panel configuration variables are unused on skylake
and are no longer needed in chip.h.

BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-chell coreboot

Change-Id: Ie6bfb676b5a32b4d4d39dda91b90fc7e973d38e0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f261d7ca9ec93aae1362975efde11ac9657b7ca6
Original-Change-Id: If64594455754e4dea1f53511861b74ddd880c5b5
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/318923
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12986
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18 12:14:49 +01:00
robbie zhang 758c171539 google/chell: Add VR config settings
Use the Kunimitsu settings as baseline, except Psi4Enable set to 0 due
to a known issue (not able to hit S0ix) on glados. The VR settings will
then need to be updated per the board VR design.

BRANCH=none
BUG=chrome-os-partner:48466
TEST=Build and booted chell

Change-Id: Ieb014e2a0cee1cb02a1c095da273b5ac1a19ef5d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fcd47a2fb2b369a93d2992fa1c17c2ce91c0e948
Original-Change-Id: Iac197314702fe5897359afc1ad1636bbcdafa204
Original-Signed-off-by: robbie zhang <robbie.zhang@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/317870
Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12985
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18 12:13:54 +01:00
robbie zhang a09aa5ae40 google/glados: Add VR config settings
Use the Kunimitsu settings as baseline, except Psi4Enable set to 0 due
to a known issue (not able to hit S0ix) on glados. The VR settings will
then need to be updated per the board VR design.

BRANCH=none
BUG=chrome-os-partner:48466
TEST=Build and booted glados

Change-Id: I42d360657ab7c47d66043f39b79540b69a9072d1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d06397c1c32136d1b6a1c1346ed722ad6926ce1a
Original-Change-Id: Ib0746cd84c2c8af29f53a65a0a7b85966c918869
Original-Signed-off-by: robbie zhang <robbie.zhang@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/317910
Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12984
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18 12:13:19 +01:00
Aaron Durbin df21440d68 intel/skylake: provide default VR configuration
FSP 1.8.0 will do nothing with the VR settings if VrConfigEnable is
non-zero. That behavior is not desired because it's not clear what
the behavior will be for various processor SKUs. Instead provide
default values for the VR config. Note that PSI3 and PSI4 are not
enabled for those defaults.

BUG=chrome-os-partner:48466
BRANCH=None
TEST=Built and booted glados.

Change-Id: I02cb5fbdd4549cc827a0b0e4006bc21da4593b55
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a68c53e0fdf15584270dfafc679a22319f497d17
Original-Change-Id: I82b1d1da2cfa3c83ccc6a981e30ffac6fb6c8c4b
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/318263
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12983
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18 12:12:12 +01:00
Duncan Laurie ae34cae4fe google/glados: Add pull-ups on LPC address lines and setup PCH_WP early
Copy changes from chell to add 20K pull-up to LPC address lines
and setup the PCH_WP signal early so it is set correctly in VBNV.

BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-glados coreboot

Change-Id: I3337cb9e5ee445471c7a0b61ee22869f66189b63
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c99dae3729636790c2ad457ec3271d2bd99fb1c4
Original-Change-Id: I7627ec263e710ce186cea15c805203395acf3e99
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/317244
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12982
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18 12:11:23 +01:00
Duncan Laurie ddd9f1a5a6 intel/skylake: Add devicetree setting for DDR frequency limit UPD
There is a UPD setting exposed by FSP that allows the DDR
frequency to be limited.  Expose this for devicetree.

BUG=chrome-os-partner:47346
BRANCH=none
TEST=tested by limiting DDR frequency to 1600 on chell EVT

Change-Id: I1f17b221d9fa4c2dd1e8c5f403deb0f2bc0493a7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 91f760ad19823225f7e5bd2dc690164ed253e220
Original-Change-Id: Ibcd4a65a9cfd7d32fbf2ba8843ab25da8e9cf28a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/317243
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12981
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18 12:09:37 +01:00
Duncan Laurie 63f8c0af4b intel/skylake: Add elog event for THERMTRIP
The THERMTRIP status bit is in GBLRST_CAUSE instead of
GEN_PMCON like the EDSv1 indicates.  Read this status bit
and add an elog event if THERMTRIP has fired.

BUG=chrome-os-partner:48438
BRANCH=none
TEST=tested on chell EVT after thermtrip fired

Change-Id: Icd52b753c7f3ab0d48095279f1255dd2dd08fd59
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b090c7897a8f99a685f523990235d83fafa063b2
Original-Change-Id: I5a287d7fdae2ba8ae8585cb9a4d4dd873393e1e6
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/317242
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12980
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18 12:08:47 +01:00
Duncan Laurie 970132f725 google/chell: Minor updates from EVT and FSP 1.8.0
- Add pullup on LPC address lines for leakage
- Configure PCH_WP early so it gets set properly in VBNV
- Disable SD card reader in favor of USB

BUG=chrome-os-partner:47346
BRANCH=none
TEST=build and boot on chell EVT

Change-Id: Ibac79c6cbef0515b1e8a513cfde5fee184e4c70a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ebd0c16a6009b74d3c6c36878c502fda9bb3020d
Original-Change-Id: If2bc4eb546a1aab50d3688b6e92f8c38214c9cca
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/317241
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12979
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18 12:08:15 +01:00
david 15144d5500 google/lars: Add VrConfig UPD parameters
Follow kunimitsu setting of
https://chromium-review.googlesource.com/#/c/313068/

BRANCH=none
BUG=chrome-os-partner:48459
TEST=Build and boot in lars

Change-Id: Iffa9e1307f478b1d72befd3e5af71e7d40bb55ef
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6c669014d0773d6790656dd6f957d2c860d00781
Original-Change-Id: I615d53a33ad8e750d4382e2a9ec397c5b6ff55e1
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/317222
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12978
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18 12:07:52 +01:00
david d4fd0a0fc1 google/lars: Correct the output for crossystem wpsw_boot
The write protect GPIO is not being configured early enough.
This is leading to coreboot reading incorrect value, and
writing the incorrect value in vboot shared file.
This is leading to "crossystem wpsw_boot" always returning 0
even with the write protect screw in place during boot.

BRANCH=none
BUG=chrome-os-partner:48292
TEST=Build and boot on lars

Change-Id: I28fbbd690ca6efb539422e9ba02f10e07cd35346
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d229ba9d8934dcb5f22b27ce0ad27601ec87d6ff
Original-Change-Id: I64f2497a6bb3a50b0f58c67e2ab6751c4836fd89
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/317130
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12966
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18 12:03:52 +01:00
Archana Patni 30f53cd397 skylake boards: csme: add p2sb device and hecienabled devicetree variable
The HeciEnabled decides the state of Heci1 at end of boot. Setting to 0
(default) disables Heci1 and hides the device from OS. It internally uses
the FSP Psf Unlock policy to disable the Heci1. It also adds the p2sb
device in the devicetree which is necessary for hiding and unhiding the
device.

BRANCH=none
BUG=chrome-os-partner:45618
TEST=build for kunimitsu.

CQ-DEPEND=CL:*238451

Change-Id: Ieba2ab3b4ac518cce8371069028170ba99aaf079
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cbefe9d6e9a981594534d346be67a5cd94483d05
Original-Change-Id: I8c95b5b9b28ba8441ca031f4e9ec523d913990d6
Original-Signed-off-by: Archana Patni <archana.patni@intel.com>
Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/311913
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12977
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18 04:42:51 +01:00
Martin Roth fd277d8f94 header files: Fix guard name comments to match guard names
This just updates existing guard name comments on the header files
to match the actual #define name.
As a side effect, if there was no newline at the end of these files,
one was added.

Change-Id: Ia2cd8057f2b1ceb0fa1b946e85e0c16a327a04d7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12900
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-18 04:07:53 +01:00
Damien Roth 4e7e987b24 console/: add missing license headers
These were copied from the linux kernel, so get the standard corboot GPL
v2 header.

Change-Id: I27ef3326cc42b7e005f94c8b4fd355012a89561d
Signed-off-by: Damien Roth <yves.r.roth@gmail.com>
Reviewed-on: https://review.coreboot.org/13023
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-18 03:44:01 +01:00
Martin Roth f4d015dbf8 commonlib/: Add missing license headers
These files are original to coreboot and get the standard
coreboot GPL header.

Change-Id: I19565b0d2424a6f37a95ab4d7b16742d23122d1e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12919
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-18 03:27:02 +01:00
Martin Roth 8e442dc09a arch/riscv: Add missing license headers
Most of these files are original to coreboot and get the standard
coreboot GPL header.

encoding.h and atomic.h are from the riscv codebase and have their
license.

Change-Id: I32506b0ecf88be2f5794dc1e312a6cd9b2a271ad
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12906
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-01-18 02:14:03 +01:00
Martin Roth 699af19359 arch/x86/Makefile.inc: Update symbol check macro
This was breaking the build on OS X, but also wasn't working correctly
under linux anymore either. It wouldn't print the illegal symbols
when it failed.

- Split the generation of the offenders file from the actual check for
offending symbols and just send all output to /dev/null.
- Rewrite the check for offending symbols in a way that works with OS X.

Tested by adding a global variable to romstage and verifying the
failure is shown correctly.  Verified that it works correctly with no
illegal variables.

Change-Id: I5b3ac32448851884d78c3b3449508ffe014119ab
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13018
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-18 01:47:17 +01:00
Pravin Angolkar 5d4735d140 intel/kunimitsu: Power gate Kepler device
This patch power gates the Kepler module
on skylake kunimitsu board. This is required
to save power since this is consuming over 500mw
of power in all active use cases.
The device can be powered on later by using the
kernel driver as required by setting the
kepler enable gpio high.

BRANCH=None
BUG=chrome-os-partner:45962
TEST=Build and Boot Kunimitsu and check lspci.
The Kepler device should not be listed.
Also power measurement of board should give
approximately 300mW of reduction in power.

Change-Id: I244a23385e20ef1431dc895536c8a47e1f5770d7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8d4fb7d01f32ac307a351c307b8461628c0e5414
Original-Change-Id: Idafa74d7ff14d67a5b1e635f783efd84b5a7399c
Original-Signed-off-by: Pravin Angolkar <pravin.k.angolkar@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/302277
Original-Commit-Ready: Naveenkrishna Ch <naveenkrishna.ch@intel.com>
Original-Tested-by: Pravin K Angolkar <pravin.k.angolkar@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12964
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18 01:18:38 +01:00
Rishavnath Satapathy 285b44f723 intel/kunimitsu: Enable TPM PIRQ
Enable the config option for TPM to use PIRQ instead of SERIRQ
and enable the MAINBOARD_HAS_LPC_TPM option.

BUG=chrome-os-partner:46335
BRANCH=none
TEST=tested this patch with TPM ACPI driver(tpm_tis.force=0)

Change-Id: I311cc7d2e70cc52a7e90f3c3c60d422b7b998789
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ad9450c342c752f87e3385a2acd5dd79b65cc75f
Original-Change-Id: Ib7b1b40c296fce80d5366bd19e7ff20d7161db95
Original-Signed-off-by: Rishavnath Satapathy <rishavnath.satapathy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/316287
Original-Commit-Ready: Pravin K Angolkar <pravin.k.angolkar@intel.com>
Original-Commit-Ready: Naveenkrishna Ch <naveenkrishna.ch@intel.com>
Original-Tested-by: Pravin K Angolkar <pravin.k.angolkar@intel.com>
Original-Reviewed-by: Pravin K Angolkar <pravin.k.angolkar@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12963
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18 01:07:18 +01:00
Naresh G Solanki 06b0098c5b intel/kunimitsu: add nhlt support
Provide an option for including the NHLT blobs within the
kunimitsu mainboard directory while also adding the ACPI NHLT
table generation that the current hardware supports.

Kunimitsu does support two audio codec, ADI and MAXIM,
hence use AUDIO_DB_ID to read correct codec and craete
NHLT table, this will also help to load only one amplifier ASL
for machine driver consumption.

BUG=chrome-os-partner:44481
BRANCH=None
TEST=Built and booted kunimitsu board. Audio worked
with both ADI and MAXIM audio card.
CQ-DEPEND=CL:316352

Change-Id: Ic9b9af83a0229fdf5f1cb019245ae65ad9d2f06c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2db85062d65c5e831da297588aa4abb18d6ed1bb
Original-Change-Id: I3b08f3f23b334799a81cde81a30d6f231cc8583f
Original-Signed-off-by: Naresh G Solanki <Naresh.Solanki@intel.com>
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/315450
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12959
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18 00:45:45 +01:00
Archana Patni 7846e34c02 intel/skylake: disable heci1 if psf is unlocked
This patch adds support for disabling the heci1 device
at the end of boot sequence. Prior to this, FSP would have
sent the end of post message to ME and initiated the d0i3 bit.

This uses the Psf unlock policy and the p2sb device to disable
the heci1 device, then lock the configuration and hide the device.

BRANCH=none
BUG=chrome-os-partner:45618
TEST=build for kunimitsu or glados board. set the hecienabled policy
to 0 and check for heci 1 device status in kernel lspci.

CQ-DEPEND=CL:*238451

Change-Id: I26b145231f8ed0c140af42d378b222e857d9aff6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fe184b8baf1bea9bcd0af1841785a4d763af9358
Original-Change-Id: I3b435491aeea0f2ca36b7877e942dc940560e4dd
Original-Signed-off-by: Archana Patni <archana.patni@intel.com>
Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/311912
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12976
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-17 22:54:17 +01:00
Subrata Banik df13c31ed6 intel/skylake: During RO mode after FSP reset CB lose original state
CB used to clear recovery status towards romstage end after FSP
memory init. Later inside FSP silicon init due to HSIO CRC mismatch
it will request for an additional reset.On next boot system resume
in dev mode rather than recovery because lost its original state
due to FSP silicon init reset.

Hence an additional 1 reset require to identify original state.
With this patch, we will get future platform reset info during romstage
and restore back recovery request flag so, in next boot CB can maintain
its original status and avoid 1 extra reboot.

BUG=chrome-os-partner:43517
BRANCH=none
TEST= build and booted Kunimitsu and tested RO mode

Change-Id: Ibf86ff2b140cd9ad259eb39987d78177535cd975
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 40ddc21a97b318510116b7d5c4314380778a40f7
Original-Change-Id: Ia52835f87ef580317e91931aee5dd0119dea8111
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/302257
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12975
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-17 22:52:02 +01:00
david e28846a0e8 google/lars: Enable TPM PIRQ
Enable the config option for TPM to use PIRQ instead of SERIRQ
and enable the MAINBOARD_HAS_LPC_TPM option.

BUG=none
BRANCH=none
TEST=tested this patch with TPM ACPI driver(tpm_tis.force=0)

Change-Id: I761d623d1064b8030f2703500d174259bb20ca79
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2f7bdb1091b7dd62a3c0b4a2272ab9f56fd7acc9
Original-Change-Id: Id1a867980d2e28a1f328aa36bed3c846b2137bec
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/317471
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12974
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-17 21:43:29 +01:00
david 6a370748cb google/lars: Enable 20K PU on LPC_LAD 0-3
At S0, S0ix and S3 LPC LAD signals are
floated at 400~500mV.

BRANCH=none
BUG=chrome-os-partner:48331
TEST=Build and boot on lars

Change-Id: I5582007e5caaf444740fa71c9761c27614aafee2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b855fd5834056a3f7d4aef91d634066006990a38
Original-Change-Id: I3a54f9f83f055e433cc1fea38169437ee7f9188f
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/317071
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12965
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-17 21:30:11 +01:00
Patrick Rudolph 7e513d1d04 intel/sandybridge/raminit: fix ODT setting
Count DIMMs on current memory channel instead of all memory channels.

The current code is only able to correctly handle the following memory
configurations:

One DIMM installed in either channel.
Four DIMMs installed, two in each channel.
Two DIMMs installed, both in the same channel.

For systems that have any other configuration the DRAM On-Die-Termination
setting is wrong.
For example:

Two DIMMs installed, one in each channel.

Test system:
* Gigabyte GA-B75M-D3H (Intel Pentium CPU G2130)

Change-Id: I0e8e1a47a2c33a326926c6aac1ec4d8ffaf57bb6
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/12892
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-01-17 18:51:40 +01:00
david 441be59ae0 google/lars: Remove/Disable Wake on lan
Remove the WakeConfigWolEnableOverride to disable WOL override
configuration in the General PM Configuration B (GEN_PMCON_B) register

BRANCH=none
BUG=none
TEST=Build and boot on lars

Change-Id: I48d3b706517b6ea6bda44800f61bb11da64503fb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: eab69f2d725df739e5e0e5901a581ad58732cdf9
Original-Change-Id: I42c5a87150638171526ee67f194c1cd9d155203b
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/317080
Original-Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12962
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-17 00:04:00 +01:00
Subrata Banik d91b1dfabb google/lars: add nhlt support
Provide an option for including the NHLT blobs within the
lars mainboard directory while also adding the ACPI NHLT
table generation that the current hardware supports.

BUG=chrome-os-partner:44481
BRANCH=None
TEST=Built and booted lars board.
Audio worked with MAXIM audio card.

Change-Id: I1b7836c685ebbe1498f3dbaa2eb64d5e0d4faabb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 401f1a7b23dca19712517ed1588e1390769d1271
Original-Change-Id: I6a937872a9e10d2c5ea15d5952d23e98416df092
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/316092
Original-Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12961
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-16 23:33:45 +01:00
Martin Roth 27d71da71a vendorcode/intel/.../skylake: Update FspUpdVpd.h to v1.8.1
This corresponds with the changes that have already gone into the
soc/intel/skylake chip.h file and is needed to get skylake platforms
building again.

Change-Id: I15bfee4eff50d6632659953ec8f97a39d8810db3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13022
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-16 21:04:04 +01:00
Martin Roth 5d6929b1d7 intel/skylake: Fix uninitialized variable warning
I don't think the warning is valid, because we already verify
that num_channels is 2 or 4 as soon as we enter the function.
Adding the default case makes the compiler happy.

Fixes warning:
src/soc/intel/skylake/nhlt/dmic.c: In function 'nhlt_soc_add_dmic_array':
src/soc/intel/skylake/nhlt/dmic.c💯2: error: 'formats' may be used
uninitialized in this function [-Werror=maybe-uninitialized]
return nhlt_endpoint_add_formats(endp, formats, num_formats);
^

Change-Id: Idc22c8478ff666af8915d780d7553909c3163690
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13021
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-16 21:03:30 +01:00
Stefan Reinauer c5dfdc5992 mainboard: Drop abuild.disabled files for Skylake boards
Make sure the latest & greatest Intel targets actually
build in our build system.

intel/sklrvp is still failing for reasons unrelated to the rest
of the skylake boards.  Leaving that disabled for now.

Change-Id: Ie784628a57257cea30e5e47074648198b884f6db
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12857
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2016-01-16 19:12:02 +01:00
Rizwan Qureshi 67ea2fb449 intel/kunimitsu: remove/disable Wake on lan
remove the WakeConfigWolEnableOverride to disable WOL override
configuration in the General PM Configuration B (GEN_PMCON_B) register

BRANCH=none
BUG=none
TEST=Build and booted in kunimitsu

Change-Id: Ia523e7956c06c9f4a60e0a2296f771cc3c70bc25
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 12a07eebfb8fa4ee8013fbbb12283a0b429cacfd
Original-Change-Id: I2be6c5b0114e4c7d8a7b9ceb59ee32f28f61769f
Original-Reviewed-on: https://chromium-review.googlesource.com/316717
Original-Commit-Ready: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Tested-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12958
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-16 12:01:23 +01:00
david 2672ee3e3a google/lars: Add new configuration parameters
Follow kunimitsu setting of
https://chromium-review.googlesource.com/#/c/313309/

BRANCH=none
BUG=none
TEST=Build and boot on lars.

Change-Id: I77a4454b3702dc58dc70a7b981b25a656e97f534
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9c390322b4c770a0206549257dd34d1ef1242cc3
Original-Change-Id: I612e799433a396a6cce5742adb6de72a305b5df1
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/316270
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/12954
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-16 12:01:00 +01:00
Subrata Banik 0ab8e00aeb google/lars: Disable SD 3.0 Controller [D30:F6]
LARs design don't have SD Connector over native SD Controller.

BUG=chrome-os-partner:48190
BRANCH=None
TEST=Build & boot LARs. Use "lspci" doesn't list 0x1E:06
device in list.
CQ-DEPEND=CL:315420

Change-Id: Idff7243a6aaf4b8d5f49e4bf215a77131f716485
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ca769138b97b404598c4a6bfa6c2ff5c1c3ec896
Original-Change-Id: I71416ac89a8c91ab272d6737d1b46c8045567e17
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/315423
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12947
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-16 12:00:03 +01:00
Subrata Banik 086730b062 intel/skylake: Add kconfig option to skip Native SD Controller
Skylake Core boot should have configurable option to skip
PCH based SD 3.0 Controller from customer/reference design.

Addition to that no unused or unnecessary should list under
device view.

BUG=chrome-os-partner:48190
BRANCH=None
TEST=Build & boot Kunimitsu and LARs.

Change-Id: Ie17fd6db01e0cabcdf605017509d809b54509a0d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 99ac17b723125822368539d0562aa35119e520fb
Original-Change-Id: I98a48f45ef442246227fd54ea021b53f824954c5
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/315420
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12946
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-16 11:59:40 +01:00
Rizwan Qureshi 3fc42772bc intel/kunimitsu: Add VrConfig UPD parameters
Cofigure VR settings for kunimitsu

BRANCH=none
BUG=chrome-os-partner:45387
TEST=Build and booted in kunimitsu

CQ-DEPEND=CL:311317

Change-Id: Ib2afe7694d2a807cea1befa73349bd21a3e7d909
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c3548d7cb3a00826377e819f20d07167b4eb2c65
Original-Change-Id: I6b80f509bc0ab6f65f26eec0651a3b44fb38fbf9
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313068
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12945
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-16 11:59:01 +01:00
Rizwan Qureshi 2b1e8b3c3d intel/skylake: Add VrConfig UPD parameters from coreboot
Adding VrConfig UPDs and assign values to those from devicetree

BRANCH=none
BUG=chrome-os-partner:45387
TEST=Build and booted in kunimitsu

CQ-DEPEND=CL:310192

Change-Id: Ifce9dfacabc742b55266c48459c56c69b1f22236
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b34a3cc77afc8795abb64972f8169986c30c2acd
Original-Change-Id: Ifa960e718ed77db729f1fc4e2c00c9b305093e04
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/311317
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12944
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2016-01-16 11:58:31 +01:00
Rizwan Qureshi b6319c1121 intel/skylake: Enable SkipMpInit token
This patch helps to enable SkipMpInit token of FSP SiliconInit UPD

BRANCH=none
BUG=chrome-os-partner:44805
TEST=Build and booted in kunimitsu with SkipMpInit enabled from CB.

CQ-DEPEND=CL:310869

Change-Id: I43377e4b8adadf42091a9387883363fdfbab4c1b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b7962273fd1a591cfe9a658f49ebc7d23bcad577
Original-Change-Id: I977d2d39c283d74f1aa9033c8aa60dc652735019
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/310192
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12943
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-16 11:56:26 +01:00
Martin Roth 19d9fe9ebc intel/skylake: Init variable so GCC knows it's set
Even though the data32 variable was getting written by
pch_pcr_read(), GCC still flagged it as being used while
uninitialized and failed the build.

Note that pch_pcr_read() may only set 1 or 2 bytes of data32 in the
successful path, depending on the size of the read.

Change-Id: Icd6e80d06b9bf4af506d62d55ffe4c5e98634b2b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12860
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Ben Gardner <gardner.ben@gmail.com>
2016-01-15 22:41:11 +01:00
Damien Zammit 647e385187 sb/intel/i82801gx: Fix sata AHCI for desktop NM10/ICH7
Tested on Intel D510MO
Before this patch, I was unable to get the SATA controller into AHCI
mode.  That is, I could never see PCI ID 8086:27c1 appearing on the bus.
With sata_ahci set, controller now goes into AHCI mode and works. 8086:27c1

Tested on X60 with AHCI enabled 8086:27c5 (AHCI mode for mobile ich7)
No regressions detected.

Change-Id: I4a3eabb5773106a0825fa2f30ee400fbfe636c7f
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/12923
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-01-15 20:46:03 +01:00
Rizwan Qureshi fb87998150 intel/kunimitsu: Add new configuration parameters
Add new configuration parameters eg. #SLP_S3 assert width

BRANCH=none
BUG=chrome-os-partner:44075
TEST=Build and booted on kunimitsu, verified that CB is doing
 the Lockdowns which were previously done by FSP.

CQ-DEPEND=CL:310869

Change-Id: I782df49bbf73c121b191f0661907173c4fd29b64
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: de0742869b1b148597d3714a3bc29a0dc08642aa
Original-Change-Id: I2b4041cdc22a29e79d2ff7f2cc49f51f80da5567
Original-Reviewed-on: https://chromium-review.googlesource.com/313309
Original-Commit-Ready: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Tested-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12942
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15 20:40:45 +01:00
Rizwan Qureshi e64f794f3a intel/skylake: More UPD params are added for PCH policy in FSP
Some more PCH Policy UPD Parameters are added in FSP.
Lockdown config moved from FSP to coreboot.
Removing settings in devicetree.cb which are zero.

BRANCH=none
BUG=none
TEST=Build and booted on kunimitsu, verified that CB is doing
  the Lockdowns which were previously done by FSP.

CQ-DEPEND=CL:*237842, CL:310191

Change-Id: I3dcf3a5340f3c5ef2fece2de5390cde48db4d327
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e8bdb35897b640d271adcaed266030367f060553
Original-Change-Id: Ia201672565c07b2e03d972b2718512cd4fcbb95c
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Signed-off-by: Naresh G Solanki <Naresh.Solanki@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/310869
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12941
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2016-01-15 20:40:14 +01:00
Barnali Sarkar b57772d2bf intel/skylake: Update UPD parameters as per FSP 1.8.0
Some MemoryInit UPD parameters have been moved to
SiliconInit in FSP 1.8.0. This patch has the respective
changes in coreboot for this.

BRANCH=none
BUG=none
TEST=Build and booted in kunimitsu

CQ-DEPEND=CL:*237423, CL:*237424

Change-Id: Ic008d22f96fb5f14965e5b5db15e05fb39dd52d3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 573c1d8325cd504213528030ecf99559402b5118
Original-Change-Id: I71b893aa7788519ed2ef15f3247945ffcbbbcf4d
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/310191
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12940
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15 20:40:05 +01:00
pchandri ff25b7532c intel/kunimitsu: Enable 20K PU on LPC_LAD 0-3
At S0, S0ix and S3 LPC LAD signals are
are floated at 400~500mV.

BRANCH=chrome-os-partner:48331
BUG=None
TEST=Build and Boot kunimitsu

Change-Id: I2e2654ac89f8e0c8d6ab1af31d0bd5a0d4c43db8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6f4b902e220dcde73df56970208c45fe3148b70e
Original-Change-Id: I597d4816d09d0cfd9b0ec183a9273551aed8688a
Original-Signed-off-by: pchandri <preetham.chandrian@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/316529
Original-Commit-Ready: Preetham Chandrian <preetham.chandrian@intel.com>
Original-Tested-by: Preetham Chandrian <preetham.chandrian@intel.com>
Original-Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Preetham Chandrian <preetham.chandrian@intel.com>
Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-on: https://review.coreboot.org/12957
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15 12:03:55 +01:00
Subrata Banik fbc4609265 intel/skylake: Add GPIO ACPI Apis.
GPIO ASL APIs to get GPIO Value.
Need such APIs to read GPIO config settings.
Example: Kunimitsu need to read AUDIO_DB GPIO
to identify codec select.

BUG=chrome-os-partner:44481
BRANCH=none
TEST=build and boot on Kunimitsu.

Change-Id: If56bb7b3eae08e1949d372850a6426dfde5aadd0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4983ba835a8da2baf578b035ae482755983c1ecb
Original-Change-Id: Ia40d86c8d4b14857fa8822677b3f7d393a35b677
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/316352
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12956
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15 12:03:15 +01:00
david b7a42d388b google/lars: Set DPTF critical temperature to 99C
DPTF may power off the system when it starts if the CPU temp is >90C.
Since TJmax is 100C set the critical threshold to just below that value.

BRANCH=none
BUG=none
TEST=Build and boot on lars.

Change-Id: I3abf946ae09c3c691480e468d0c1d74730dc6c06
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7c2230009edb840e88a20c2d8a87f942c09b6bf3
Original-Change-Id: Iee1a3596dbbe934f68637f012c02c078c3751eeb
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/316102
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/12955
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15 12:01:29 +01:00
david 228aae589c google/lars: Disable kepler device
Disable kepler device, it is removed and was not used on proto anyway.

BUG=none
BRANCH=none
TEST=build and boot on lars proto

Change-Id: I137b82b8dca23f5b40adcc6a056e77a4ff54d4d5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 44d63453a9b31331d13d05f8f86d4218af0f0aa1
Original-Change-Id: Ib0892bf93b1d0cda1c0143d2b16cd58aeda83131
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/315950
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/12950
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15 12:00:59 +01:00
Subrata Banik 4d27c42604 google/lars: Add support for MAX98357A audio amplifier
Adding support for Maxim 98357A audio amplifier.
Removed SSM4567 support from LARs.

BUG=chrome-os-partner:44481
BRANCH=None
TEST=Build & boot on LARs.
Verify audio playback works using MAXIM amplifiers.

Change-Id: I2cd8b20e936319b434017b6dd73d4739684d21d3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 76cbc20826c884194a144f6b6bc644900e5d475d
Original-Change-Id: I1156096b6aa367c0b8d8e3952d92f0eb5cf2820f
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/314543
Original-Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12960
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15 11:59:41 +01:00
Arindam Roy 3b43fa9086 intel/kunimitsu: Correct the output for crossystem wpsw_boot
The write protect GPIO is not being configured early enough.
This is leading to coreboot reading incorrect value, and
writing the incorrect value in vboot shared file.
This is leading to "crossystem wpsw_boot" always returning 0
even with the write protect screw in place during boot.

BUG=chrome-os-partner:48292
BRANCH=None
TEST=Boot with the write protect screw in place. Issue
crossystem wpsw_boot. It should show 1.

Change-Id: I3a333a4dcce31be9afe28cf11b127090cc7b9421
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 462dd0229c2d3b81cd34bdd2e36bea844f58586c
Original-Change-Id: Ib7e0539845575b32322e243e89b81ffee077eb81
Original-Signed-off-by: Arindam Roy <arindam.roy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/316009
Original-Commit-Ready: Arindam Roy <rarindam@gmail.com>
Original-Tested-by: Arindam Roy <rarindam@gmail.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12952
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15 11:56:34 +01:00
david da6666b050 google/lars: Update the PL1 value as TDP
Currently, the Power Limit 1 (PL1) value is 6W which is
low for high performance KPIs. This patch updates PL1
value as TDP. SKL-U has 15W TDP.

BRANCH=none
BUG=none
TEST=Build and booted on lars.

Change-Id: Ic1313385e0aa1760b473a34c853a95c76257eecf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a47faee53e08da81602b485937621fd49eb2ddbf
Original-Change-Id: I7c91dcdc82525a6d2b706f8f504ba48601097ef7
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/316370
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/12953
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15 11:55:57 +01:00
Wisley e5bf90ac03 google/chell: Fix the P/N number for samsung K4E6E304EE-EGCF
modify the P/N in samsung K4E6E304EE-EGCF SPD from K4E6E304ED-EGCE to
K4E6E304EE-EGCF

BRANCH=none
BUG=chrome-os-partner:48299
TEST=build chell and use gooftool to probe and P/N match

Change-Id: Ie560e5c0d4b9a3cfb34c3856911930fb8159764e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: dabe5eaa8abf54f4e4a5492062adca6ef9b4634d
Original-Change-Id: Ie8d44ac6032e5213928bfae2a2ac5877d4193d62
Original-Signed-off-by: Wisley <wisley.chen@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/316100
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12951
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15 11:55:37 +01:00
Rohit Ainapure 02c1f86213 intel/kunimitsu: Add support for MAX98357A audio amplifier
Adding support for Maxim 98357A audio amplifier.

BUG=chrome-os-partner:44481
BRANCH=None
TEST=Build & boot on Skylake kunimitsu Fab4 with MAXIM codec.
Verify audio playback works using MAXIM.

Change-Id: I4f020ccae540b02d5d533704a52cebb7805715fe
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c0a81300e02e917500fa3c0241c95dd795abaf04
Original-Change-Id: I8875c9a55f09b1ec353203cfcb2186dc5fd66542
Original-Signed-off-by: Rohit Ainapure <rohit.m.ainapure@intel.com>
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/309894
Original-Tested-by: Rohit M Ainapure <rohit.m.ainapure@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12949
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15 11:54:55 +01:00
Aaron Durbin 3a749710cf google/chell: add nhlt support
Provide an option for including the NHLT blobs within the
glados mainboard directory while also adding the ACPI NHLT
table generation that the current hardware supports.

BUG=chrome-os-partner:44481
BRANCH=None
TEST=Built and booted. Headphones, speakers, and mic on camera
     emits and creates sound albeit not the greatest.

Change-Id: Iaf910041453695b7125b254ca5d71e8ccbd0b02f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ea77d326ba1c33b100c34066ed361a55dfa14ce3
Original-Change-Id: I5d93c3a7fa4cf68ba91f1398b4bd04504a28fef2
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/315520
Original-Tested-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12948
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15 11:54:16 +01:00
Aaron Durbin 5a18a0cb20 google/glados: add nhlt support
Provide an option for including the NHLT blobs within the
glados mainboard directory while also adding the ACPI NHLT
table generation that the current hardware supports.

BUG=chrome-os-partner:44481
BRANCH=None
TEST=Built and booted. Headphones, speakers, and mic on camera
     emits and creates sound albeit not the greatest.

Change-Id: I6e36c0a99a73cdcb2bf6ccfbfc886a594f989a39
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5b0383a93f054011dd7c18519ece4e6f1944366d
Original-Change-Id: I6f8bd15c72fa89756382af99bddb6cb6abe89905
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/313794
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12939
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15 11:51:13 +01:00
Aaron Durbin ed8a723f42 intel/skylake: add nhlt support
The use of a NHLT table is required to make audio work
on the skylake SoCs employing the internal DSP. The table
describes the audo endpoints (render vs capture) along with
their supported formats. These formats are not only dependent
on the audio peripheral but also hardware interfaces. As such
each format has an associated blob of DSP settings to make
the peripheral work. Lastly, each of these settings are provided
by Intel and need to be generated for each device's hardware
connection plus mode/format it supports. This patch does not
include the dsp setting blobs.

The current supported connections:
- digital mic array 2 channel
- digital mic array 4 channel
- Maxim 98357 amplifier
- ADI ssm4567
- NAU88L25 headset codec

BUG=chrome-os-partner:44481
BRANCH=None
TEST=Built glados. Speakers, headphones, and mic on camera decently
     worked.
CQ-DEPEND=CL:*239598

Change-Id: If1a9be97573b9b160893944661790cac7df26fca
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1f5514e27811c500732de97e1cc7edeced2607e7
Original-Change-Id: Ib42e895f00e7605cb30ce24d9b8dd00bf68a7477
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/313998
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12938
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15 11:50:25 +01:00
Aaron Durbin 9420a5205c lib: NHLT ACPI table support
Intel's SST (Smart Sound Technology) employs audio support
which may not consist of HDA. In order to define the topology
of the audio devices (mics, amps, codecs) connected to the
platform a NHLT specification was created to pass this
information from the firmware to the OS/userland.

BUG=chrome-os-partner:44481
BRANCH=None
TEST=Tested on glados. Audio does get emitted and some mic recording
     works.

Change-Id: I8a9c2f4f76a0d129be44070f09d938c28a73fd27
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2472af5793dcffd2607a7b95521ddd25b4be0e8c
Original-Change-Id: If469f99ed1a958364101078263afb27761236421
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/312264
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12935
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15 11:48:07 +01:00
Sumeet Pawnikar 047363f6f1 intel/kunimitsu: Update the PL1 value as TDP
Currently, the Power Limit 1 (PL1) value is 6W which is
low for high performance KPIs. This patch updates PL1
value as TDP. SKL-U has 15W TDP.

BRANCH=None
BUG=None
TEST=Built and boot on kunimitsu. Check for the PL1 value over
sysfs interface
"/sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw".
Load the system with Aquarium 1000 Fish, average FPS should be
meeting target 60 with this change.

Change-Id: I8e083192e8018edc2cf8b88530df1e05ede10bde
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: eb9aa00a4271875b5471c33883aa7da022f1cb0e
Original-Change-Id: I0c61fe1a9f76a9cf9a306240fb66d4c081d2bb5e
Original-Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/314416
Original-Commit-Ready: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Tested-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/12934
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15 11:47:52 +01:00
david 1f35fdde71 google/lars: Disable eMMC HS400 capability
BUG=chrome-os-partner:48017
BRANCH=none
TEST=Verify eMMC is working fine.

Change-Id: If02d969029a9eb8d05148ee958fd34225c8a88fe
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: dca385c2bbf11c9eb79fd0761b2b335f8fdff491
Original-Change-Id: I371036426f17530409b46af285b18f4522739ee7
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313912
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/12618
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15 11:47:44 +01:00
Martin Roth 9df9e93914 arch/x86: add missing license headers
These were mostly written as part of the coreboot project, so get
the standard coreboot license header.

memmove.c came from the linux kernel, so also gets the standard
coreboot v2 license header, but gets the added attribution that it
was derived from the linux kernel.  Unlike many coreboot files,
this file may not be re-licensed as GPL V3.

Change-Id: I1fdc26b543e059f7a42d4b886f7222f4c74b959d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12916
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-14 23:37:06 +01:00
Divya Sasidharan 1ff0f54f03 soc/braswell: Add CPUID for D0 stepping
Original-Reviewed-on: https://chromium-review.googlesource.com/309122
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Tested-by: Hannah Williams <hannah.williams@intel.com>

Change-Id: Ia24dbeb6b23ccbbb380843a4684def578cde168a
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-on: https://review.coreboot.org/12727
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-14 23:09:47 +01:00
Martin Roth edb937acd6 ec/: add missing license headers
thermal.asl was written as part of the coreboot project, so gets
the standard coreboot license header.

ec_commands.h came from the chrome ec tree, so gets the BSD license
from that tree as mentioned in the header that has been replaced.

Change-Id: I514138fd4ed236105998b25d1d2d8eb8441cf91d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12918
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-14 22:52:51 +01:00
Martin Roth 1766b1ea9d acpi/: add missing license header
These were mostly written as part of the coreboot project, so get
the standard coreboot license header.

Change-Id: Ief13339647d3172e65bb18e6dcb54312a5c9472e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12917
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-14 22:52:11 +01:00
Martin Roth a7cf7b7776 arch/x86/include: add missing license headers
These were all written as part of the coreboot project, so get
the standard coreboot license header.

Change-Id: I51e1e504b3bc7be2a00c9356d8775b87f2a1db5a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12912
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-14 22:48:17 +01:00
Subrata Banik 45a221de79 soc/braswell: Fix P-state table
Incorrect bus-core-ratio been used to generate P-state table

Original-Reviewed-on: https://chromium-review.googlesource.com/290681
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I4a34ec80ff3f2ed46dc074c9f8fe06756db8b357
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/12731
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-14 19:17:01 +01:00
Martin Roth baf00e6b28 intel/skylake/pcr.c: error out on invalid size in pcr read/write
The read and write routines take a number of bytes to write, which
should be 1,2, or 4.  We now return an error if an invalid size
is specified.

Change-Id: I93344bc0837c3715fc7660503f405c8878eb711c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12936
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-01-14 19:15:58 +01:00
Nico Huber 3cbe62fe37 mb/lenovo/x200: Add panel power sequence values
Values are taken from the vendor BIOS of my X200s. Notable effect:
Stops display from flashing during native graphics init / Linux mode
setting.

Change-Id: Ie5d9efc010a78dd46317b6bbdb7bfacc2c9d2cbf
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/12886
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-14 19:08:44 +01:00
Nico Huber b851cc69d6 nb/intel/gm45: Backport configuration of panel power timings
Register settings are the same as on newer chips (compare sandy-
bridge), just at different locations.

Change-Id: Iea0359165074298a376e0e2ca8f37f71b83ac335
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/12885
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-14 19:07:45 +01:00
Nico Huber c3571da263 nb/intel/gm45: Drop unnecessary panel power handling
Skip everything but the final setting of PP_CONTROL, i.e. triggering
the power up. The settings with PANEL_UNLOCK_REGS are useless as no
lockable registers were touched in between. Also the loop waiting for
the panel power up to finish was a no-op as the registers with the
power timings were never filled (see follow-up commits).

Change-Id: Ife27dcafdf197b2246c4e69f2bf7a3a6765d1d82
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/12884
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-14 18:57:44 +01:00
Alexander Couzens f8970f53ef mainboard/lenovo: reserve century byte
The century byte is used by most RTC (default 0x32@nvram).
Even the century byte can disabled via ACPI it's more safe to reserve
it's space. Because some RTC will act with that byte anyhow.
Some OS overwrite it when syncronize the RTC.

Change-Id: I078c0c57215ccb925afa85b9d067f15268801ec9
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/11853
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-01-14 17:58:29 +01:00
Martin Roth cf77d28ff7 arch/arm64: add missing license headers
These were all written as part of the coreboot project, so get
the standard coreboot license header.

Change-Id: I4fccc8055755816be64e9e1a185f1e6fcb2b89ae
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12911
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-13 22:58:17 +01:00
Martin Roth e44adfa5de arch/arm: add missing license headers
These were all written as part of the coreboot project, so get
the standard coreboot license header.

Change-Id: I74438e8032c84f4190ef49f306969f7157234001
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12910
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-13 22:54:02 +01:00
Martin Roth a20ac2f7b3 tree: drop last paragraph of GPL copyright header from new files
This continues what was done in commit a73b93157f
(tree: drop last paragraph of GPL copyright header)

Change-Id: Ifb8d2d13f7787657445817bdde8dc15df375e173
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12914
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-13 20:35:40 +01:00
Martin Roth 02ec8feb2c intel/skylake platforms: Add MAINBOARD_HAS_LPC_TPM in Kconfig
Because these platforms haven't been getting build testing, they've
missed out on some of the improvements that the other platforms have
gotten.

Enable MAINBOARD_HAS_LPC_TPM so that they will build.

Change-Id: I5e44135b6dfa800fa14e5b08c3e3e5921d50b082
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12865
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-13 19:56:50 +01:00
Patrick Rudolph a696ae7e30 intel/northbridge/sandy: raminit code cleanup
Remove redundant call to dram_mrscommands().

Change-Id: I157915b4432093c556b538433e3337db1e9c525f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/12891
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-13 17:58:52 +01:00
Nico Huber 498e315988 [WIP] mb/roda/rk9: Enable CONFIG_HAVE_ACPI_RESUME
Change-Id: Ifa7dd593f70921a99d937104960e26100de28089
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/12421
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-13 17:53:27 +01:00
Martin Roth cbe38923d9 northbridge/intel/x4x: clean up includes
- Don't redefine D0F0_PCIEXBAR_LO, use the #define in x4x.h
- Move TPMBASE and TPM32() definitions into iomap.h
- Use "" style include for x4x.h in nortbridge files.
- Move includes of .h files out of x4x.h and into the c files that need
them.
- Protect function definitions in bootblock.

Change-Id: I3fdb579235c5446733a0ffba05fffe1a73381251
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12849
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-13 17:52:46 +01:00
Martin Roth 5933814e27 amd/cimx/sb800/pci_devs.h: Update guard #define name
Change-Id: Ieae41cab97293831a0c49c3b472b9e6c62ba36c6
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12899
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-01-12 22:24:52 +01:00
Martin Roth 5559e8935e intel/skylake: Remove check for Microcode loaded by ME
This method of reporting has been removed from the current Skylake
ME binaries so is no longer needed.

Change-Id: I774982146c19f37418f5aee29ae8883fcd3d0c8c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12854
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-12 22:24:09 +01:00
Matt DeVillier 8e6b0a2ae2 google/guado: initial upstream migration
Migrate google/guado (Asus Chromebox CN62) from Chromium tree to upstream,
using google/auron and google/panther as refs.

TEST=built and booted guado with full functionality

Change-Id: If7a500fb408197a61c9619b9d5ea1458d1f4d702
Tested-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/12800
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-12 22:20:28 +01:00
Nico Huber ee352cdcca nb/intel/gm45: Convert gma.c to `if (IS_ENABLED(` style
Change-Id: Ifae3822b6c28832f6aa05a4ffd8f02067a923f2c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/12883
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-12 13:50:11 +01:00
Martin Roth 229d427c12 fsp1_1: Remove #if protection in header - It's not needed
There's nothing in these files that needs to be hidden if
GOP support is disabled.  Removing this allows skylake to
build when GOP support is turned off.

Change-Id: I2a4f47cd435f48668311719f388b502ae77eca99
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12859
Tested-by: build bot (Jenkins)
Reviewed-by: York Yang <york.yang@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2016-01-10 23:38:23 +01:00
Marian Tietz 7c6c4df68c lenovo/x220: Enable USB 3 controller
Since only X220 with i7 have the USB3 controller this was
probably overlooked.

Before this patch lspci on Linux would not show the NEC USB 3 controller
as well as the PCI bridge it is behind. After, both the bridge and the
NEC controller can be found in the output:

    05:00.0 USB controller: NEC Corporation uPD720200 USB 3.0 Host Controller
	(rev 04)

Change-Id: I5e7e3f0c7d023f6206a7bec42a39f8955a3d9331
Signed-off-by: Marian Tietz <mtcoreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/12882
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2016-01-10 18:48:12 +01:00
Martin Roth fecc24af04 vendorcode/amd/agesa/f15tn: Fix out of bounds read on on memory voltage
I think this has a fairly low likelyhood of happening, but if AGESA
can't determine the voltage of the memory, it assignes a value of 255
to the variable that it later uses to read from an 3-value array.  There
is an assert, but that doesn't halt AGESA, so it would use some random
value.  If the voltage can't be determined, fall back to 1.5v as the
default value.

Fixes coverity warning 1294803 - Out-of-bounds read

Change-Id: Ib9e568175edbdf55a7a4c35055da7169ea7f2ede
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12855
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-08 17:21:59 +01:00
Martin Roth b95a074586 fsp_baytrail: Add additional PCI space above 4GB
This just tells the OS that it can use the 16GB of address space
at the 48GB mark for PCI.  This is the upper 16GB of Bay Trail's 36 bit
physical address space.

This could be hardcoded into the UMEM definition, but doing it this way
makes it more plain what it's doing, and allows for modification
to put it just above the top of upper memory, similar to what is done
with the standard PCI region above the top of low memory.

Change-Id: Id6208c3712e5d94d62a83c4ac69e8ffd0e19f4ad
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12791
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: York Yang <york.yang@intel.com>
2016-01-08 02:44:15 +01:00
Martin Roth 481a19cf99 intel/braswell: Disable IFD & ME by default so abuild can build
The Braswell IFD & ME blobs aren't published in the 3rdparty repo, so
disable them by default for now.

Change-Id: If68ff1f37fbf7afb2f9eb1e5d9942afcf40ab1e3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12828
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-07 23:04:31 +01:00
Stefan Reinauer 9dbdf520d8 mainboard: Drop abuild.disabled files for Braswell boards
Make sure the latest & greatest Intel targets actually
build in our build system.

Change-Id: I479ad473c260fc914d224cb58f4be1837aff2502
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/12463
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-07 23:01:39 +01:00
Martin Roth 2ed0aa258f Correct some common spelling mistakes
- occured -> occurred
- accomodate -> accommodate
- existant -> existent
- asssertion -> assertion
- manangement -> management
- cotroller -> controller

Change-Id: Ibd6663752466d691fabbdc216ea05f2b58ac12d1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12850
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-07 22:57:02 +01:00
Paul Menzel 2e0d9447db src/vendorcode/amd: correct spelling of MTRR
Change-Id: I7576591b42fa62da2b3bd74f961fb297b85e250d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/4806
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-07 17:40:45 +01:00
Stefan Reinauer f8532b16be f14: Increase AP stack to 8k on 64bit
This has been broken out from http://review.coreboot.org/#/c/10581/

Change-Id: Ia6153115ff75e21657fa8c244c9eb993d0d63772
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://review.coreboot.org/11025
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-07 17:39:13 +01:00
Martin Roth 24ca41d074 google/cyan, intel/strago Kconfig: Only ask to display SPD once
Change-Id: Ic3df9bf7d7f3c4c39789f3f496bcb7fc2ee50931
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12827
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07 17:34:26 +01:00
Martin Roth d59d1b61da intel/fsp1_1: Disable GOP support by default
Since the GOP drivers aren't published in the 3rdparty blobs repo yet,
disable the GOP support for now so that abuild can build these
platforms.

Change-Id: Ic98671c163b433ebde89c8bf240ef4b2be393586
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12829
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07 16:54:54 +01:00
Timothy Pearson 6dc53b485a mainboard/asus/kgpe-d16: Enable romstage microcode spinlocks
Change-Id: I93687efc5405359286d3197f0e59ec3b118c5100
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12809
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-07 16:53:00 +01:00
Timothy Pearson c764c7488b cpu/amd/microcode: Introduce CBFS access spinlock to avoid IOMMU failure
When microcode updates are enabled, this fixes an issue identical
to that described in GIT hash 7b22d84d:
 * drivers/pc80: Add optional spinlock for nvram CBFS access

Change-Id: Ib7e8cb171f44833167053ca98a85cca23021dfba
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12063
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-07 16:52:31 +01:00
Timothy Pearson bfa19e1e47 cpu/amd/fam10h-15h: Add tsc_freq_mhz() function
The AMD Family 10h/15h processors use a TSC that increments at
the P0 core frequency.  Allow coreboot to query the TSC frequency.

Change-Id: I73ead4fd4af18991452d59985b667a54689778cd
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12834
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-01-06 17:46:21 +01:00
Aaron Durbin 12c55eda11 Revert "x86: Align CBFS on top of ROM"
This reverts commit 65e33c08a9.
This was the wrong logic to fix the master header.

Change-Id: I4688034831f09ac69abfd0660c76112deabd62ec
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12824
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-06 17:44:54 +01:00
Martin Roth f812c44f00 intel/braswell: Build in both C0 and 'other' vbios
The Braswell CPU seems to have two different Video BIOS roms, one for
the C0 revision, and one for other revisions.  Build them both into
the coreboot image, and let coreboot sort out which one should be used
at runtime.  This should allow one rom to be used for all revisions.

The initial reason for this patch was that the Kconfig symbol
C0_DISP_SUPPORT didn't exist, and was causing issues.  This
seems like the best way to eliminate the need for that symbol.

Change-Id: I5b9f225c0daf4e02fda75daf9cd07bb160bf0e0f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12826
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-06 17:41:49 +01:00
Aaron Durbin cbb6c75061 commonlib: Add function to hash contents of a CBFS region.
Provide a common routine to hash the contents of a cbfs
region. The cbfs region is hashed in the following order:
1. potential cbfs header at offset 0
2. potential cbfs header retlative offset at cbfs size - 4
3. For each file the metadata of the file.
4. For each non-empty file the data of the file.

BUG=chrome-os-partner:48412
BUG=chromium:445938
BRANCH=None
TEST=Utilized in chromeos cros_bundle_firmware as well as at
      runtime during vboot verification on glados.

Change-Id: Ie1e5db5b8a80d9465e88d3f69f5367d887bdf73f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12786
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2016-01-06 01:12:04 +01:00
Patrick Georgi 3e6303ebe2 commonlib/cbfs: Add type ids for empty files
We will soon need to handle empty files.

Change-Id: Ia72a4bff7d9bb36f6a6648c3dd89e86593d80761
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/12785
Tested-by: build bot (Jenkins)
2016-01-06 01:11:54 +01:00
Aaron Durbin ca0a67624b commonlib: Prepare code to be included in cbfstool builds.
Some of the files need to be adjusted so that they can be used
both in cbfstool as well as coreboot proper. For coreboot,
add a <sys/types.h> file such that proper types can be included
from both the tools and coreboot. The other chanes are to accomodate
stricter checking in cbfstool.

BUG=chrome-os-partner:48412
BUG=chromium:445938
BRANCH=None
TEST=Built on glados including tools. Booted.

Change-Id: I771c6675c64b8837f775427721dd3300a8fa1bc0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12784
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-06 01:11:32 +01:00
Aaron Durbin 295d58bda8 commonlib: Add common cbfs parsing logic to coreboot and cbfstool.
To continue sharing more code between the tools and
coreboot proper provide cbfs parsing logic in commonlib.
A cbfs_for_each_file() function was added to allow
one to act on each file found within a cbfs. cbfs_locate()
was updated to use that logic.

BUG=chrome-os-partner:48412
BUG=chromium:445938
BRANCH=None
TEST=Utilized and booted on glados.

Change-Id: I1f23841583e78dc3686f106de9eafe1adbef8c9f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12783
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-06 01:11:19 +01:00
Aaron Durbin 990ab7efe5 commonlib: Add function to compute relative offsets from two region_devices.
Provide a helper function which returns the relative offset
between 2 region_devices that have a parent-child child relationship.

BUG=chrome-os-partner:48412
BUG=chromium:445938
BRANCH=None
TEST=Utilized and booted on glados.

Change-Id: Ie0041b33e73a6601748f1289e98b6f1f8756eb11
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12782
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-06 01:11:15 +01:00
Timothy Pearson 77133afe31 sb/amd/sr5650: Correctly locate CPU MMCONFIG resource
The code committed in GIT hash
 * 1eaaa0 southbridge/amd/sr5650:Add MCFG ACPI table support
did not correctly locate the CPU MMCONFIG resource, leading to failures
with operating systems and firmware (e.g. SeaBIOS) when the PCI
extended configuration space option was activated.

Due to the southbridge routing not being set up, MMCONFIG accesses were
targetting DRAM and therefore the PCI devices were not being configured.
The failure normally manifests as a system hang immediately after PCI
configuration starts.

Search for the CPU MMCONFIG resource on all domains below the root
device.

Change-Id: I0df2f825fef2de46563db87af78d0609ab3d8c5a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12821
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-04 16:59:21 +01:00
Kyösti Mälkki bb85f9eb73 Revert "AMD OemS3Save: refactor for Merlin Falcon"
This reverts commit d3deecdd9c.

Do not mix open-source AGESA and binary PI trees. Once you have
working S3 support for binaryPI platforms, add the adapted
oem_s3.c file as northbridge/amd/pi/oem_s3.c instead.

Change-Id: I7c981d0023a5c0225e046f9c0104acfa07436b79
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/12282
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-04 11:18:04 +01:00
Vladimir Serbinenko 42d55e0caf sb/intel/bd82x6x: Add missing PCIIDs for variants .
Change-Id: I917b8167a028aa9412b0cc6dedf8f09a1d1fae7f
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/12820
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-01-03 21:22:41 +01:00
Nico Huber 5aaeb27de9 nb/intel/gm45: Export low-power and (SFF) options
Make the low-power and small form factor (SFF) options overridable
from romstage main. Also disable both options by default. That's ok
as there aren't yet any in-tree users of the GS45 chipset. As a nice
side-effect, this adds X200s support to the lenovo/x200 port.

Change-Id: I94373851262e6d424cf4885ceca7260c31bc9f61
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/12814
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-31 17:45:09 +01:00
Nico Huber 0a207399ce lenovo/x200: Revise onboard IRQ routing
All southbridge interrupt pin and routing registers (D*IP and D*IR)
are left at their default values (see ICH9 datasheet) and this file
just has to reflect them.

Change-Id: I687262556d918311757fda9afda9ebfdd7edf947
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/12813
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-12-31 17:43:38 +01:00
Ted Kuo 08debacad1 superio/it8772f: Add register to set the default value of FAN speed
Original-Signed-off-by: Ted Kuo <tedkuo@ami.com.tw>

Change-Id: I70d7b572e9ae030136a39fb6fa933f486d559aef
Original-Reviewed-on: https://chromium-review.googlesource.com/262832
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Original-Commit-Queue: Ted Kuo <tedkuo@ami.com.tw>
Original-Tested-by: Ted Kuo <tedkuo@ami.com.tw>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/12799
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-31 17:40:17 +01:00
Ted Kuo 4e8f23b896 superio/it8772f: Add switch to enable HWM (Hardware Monitor)
Set up External Temperature to read via thermal diode/resistor
into TMPINx register by setting thermal_mode switch.

Original-Signed-off-by: Ted Kuo <tedkuo@ami.com.tw>

Change-Id: I0e8621b92faa5c6246e009d2f852c8d4db484034
Original-Reviewed-on: https://chromium-review.googlesource.com/260545
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Original-Tested-by: Ted Kuo <tedkuo@ami.com.tw>
Original-(cherry picked from commit 973e2d393f2595b756f8aa20f6fbe3b6e045621a)
Original-Reviewed-on: https://chromium-review.googlesource.com/262340
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/12798
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-31 17:39:47 +01:00
Ionela Voinescu 4f3d400a30 imgtec/pistachio: disable default RPU gate register values
The RPU Clock register defaults to on for all clocks.
This is modified to OFF, and the MIPS clock control modified to ON,
by default. This is because the linux kernel will manage the
clocks at all times, but the RPU can only disable clocks if the WIFI
module has been loaded.

Change-Id: I155fb37afd585ca3436a77b97c99ca6e582cbb4f
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12773
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-31 17:36:06 +01:00
Ionela Voinescu 3218e794ba imgtec/pistachio: memlayout: update GRAM size
GRAM is 421056 bytes. The end of the SRAM region (GRAM plays the role
of SRAM) was placed at a 4K aligned address, resulting in a size of
408KB.

Change-Id: I9fa32ab818d600e7447bcac895e4b8c438f2f99d
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12772
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-31 17:35:40 +01:00
Ionela Voinescu 88357548a2 imgtec/pistachio: I2C: fix base address for I2C clock setup
The base address for the I2C dividers (DIV1 and CLOCKOUT)
was erroneously set to the toplevel clock controller base
address and not to the correct peripherals clock controller
base address.

Change-Id: I66bbc1e741bcf6251babee7ddd6376d49d7cb3d1
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12771
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-31 17:34:48 +01:00
Ionela Voinescu 56e64598a2 imgtec/pistachio: identity map SOC registers region
This region must be mapped uncached. This is necesary for an
U-boot payload which will obtain all register base addresses
as physical addresses from the device tree and will use them
as such.

Change-Id: Ib5041df7d90c6ef61b7448a18dd732afbd9489ca
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12770
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-31 17:34:28 +01:00
Ionela Voinescu 7100cf2b40 imgtec/pistachio: Add SOC_REGISTERS memory region
When used with a U-boot payload it will need this region
identity mapped also, so we're defining it in preparation
for that functionality.

Change-Id: I27cee5b58cb899433b52bd06df07b5f2105212af
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12768
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-31 17:32:24 +01:00
Ionela Voinescu 1136447a37 imgtec/pistachio: Use SYS PLL in integer mode
Use SYS PLL in integer mode by default to reduce jitter.
DSMPD_MASK is defined and can be used to switch to fractional mode.

Tested on pistachio bring up board.

Change-Id: Ie6d2aca71c7af86b0993c804329e6d03e26ff754
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12767
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-31 17:31:32 +01:00
Damien Zammit cbe7a8e100 gigabyte/ga-g41m-es2l: Add mainboard
Board uses x4x native raminit

Board boots into Debian 8 with full graphics

IRQ9: nobody cared, gets disabled
(PIC needs IRQ settings?)

VGA:
- VGA native init works in grub with analog connector
- Fails to boot with both channels of ram populated

Change-Id: I7417813456817529b8cbaace45cefe47467d0a82
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/11306
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-30 22:21:01 +01:00
Damien Zammit 4b513a618d northbridge/intel/x4x: Native raminit
Passes memtest86+ with either one or two sticks of 2GB ram
but memory map needs a hole at 0xa0000000 to 0xc0000000

Change-Id: Ib34d862cb48b49c054a505fffcba1c17aeb39436
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/11307
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-30 22:20:47 +01:00
Damien Zammit 9074cec9b9 superio/it8718f: Add missing PNP info
Change-Id: Id6d50d4d6af31e43f851645f09383121755291f6
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/12815
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-30 22:00:10 +01:00
Stefan Reinauer d09a881988 drivers/xgi/common: Fix XGI_SetGroup2
This code looks like it was created from a disassembly of some
other driver. Attempt to fix it, without hardware or documentation.

CID 142909: Operands don't affect result (CONSTANT_EXPRESSION_RESULT)

Change-Id: I9b9cadf2acdba73913aad6bbe0d14ad64a652915
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/12774
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-12-30 20:30:17 +01:00
Martin Roth da1ca20ac3 Kconfig: move fmap description file prompt into the mainboard menu
The FMD is board-specific, so it makes sense to have it in the
mainboard menu.

Change-Id: I52fba5ced869d51d10065f8c9ebd258d3a1d4156
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/12805
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-30 20:23:20 +01:00
Alexandru Gagniuc 8a13743569 x86 chipsets: Link non-code flow CHIPSET_BOOTBLOCK_INCLUDE files
Non-code flow assembly stubs do not have to be included in
bootblock.S, now that we have more freedom in bootblock linking.
Rather than bringing these stubs to the config system, just link them
in the bootblock.

Note that we cannot fully remove CHIPSET_BOOTBLOCK_INCLUDE at this
point, as some intel SOCs use this stub for code flow.

objdump -h build/cbfs/fallback/bootblock.debug on a few random boards
confirms that the appropriate sections are still included in the
final binary.

Change-Id: Id3f9ece14e399c1cc83090f407780c4a05a076f0
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: https://review.coreboot.org/11856
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-30 18:34:08 +01:00
Nico Huber 65e33c08a9 x86: Align CBFS on top of ROM
Since the introduction of the new (interim?) master header, coreboot
searches the whole ROM for CBFS entries. Fix that by aligning it on top
of the ROM.

Change-Id: I080cd4b746169a36462a49baff5e114b1f6f224a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/12810
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-29 21:45:23 +01:00
Damien Zammit 62c0276f94 device/pnp: Ability to set vendor specific logical device config
According to the PNP ISA v1.0a spec, config registers in the range of
0xf0 up to 0xfe are vendor defined and may be used for any purpose.
Config register 0xff is reserved and is defined as such.

Currently, only vendor specific registers 0xf0, 0xf1, 0xf4, and 0xfa
are able to be set using the PNP_MSCx bit flag masks.

This patch adds support for all 15 vendor specific config registers,
and updates the existing superio pnp_info to use them where appropriate.

Change-Id: Id43b85f74e3192b17dbd7e54c4c6136a2e59ad55
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/12808
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-29 18:17:01 +01:00
Damien Zammit 43a1f780ff northbridge/intel/x4x: Intel 4-series northbridge support
Boots to console on Gigabyte GA-G41M-ES2L

Ram initialization *not* included in this patch
VGA native init works on analog connector

Change-Id: I5262f73fd03d5e5c12e9f11d027bdfbbf0ddde82
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/11305
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-29 18:03:33 +01:00
Ionela Voinescu e7a336ac29 mips: add coherency argument to identity mapping
In order for a U-boot payload to work properly the soc_registers
region (device registers) needs to be mapped as uncached.
Therefore, add a coherency argument to the identity mapping funcion
which will establish the type of mapping.

Change-Id: I26fc546378acda4f4f8f4757fbc0adb03ac7db9f
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12769
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-29 18:02:15 +01:00
Ionela Voinescu 90d12351fd mainboard/google/urara: change SYS PLL to 700MHz
This requires changes the interface that sets up the system
PLL to support a given reference devider value and given
feedback value.
Also, this requires a change in the dividers used for UART,
USB, I2C setup.

Change-Id: I98cf7c655dbb3e95b8fcee3c7f468122021c70b5
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12765
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-27 20:55:21 +01:00
Duncan Laurie 8d2b49f1f7 soc/intel/broadwell: Add back support for EHCI debug setup
The EHCI debug device setup code was removed from broadwell in
commit 49ee5ef: http://review.coreboot.org/11874

However the generic device setup code is in the southbridge/common/intel
directory while broadwell is in the soc directory so this is not used.
Add it back to the broadwell soc to fix undefined reference compile
errors with 'pci_ehci_dbg_dev' and 'pci_ehci_dbg_enable'.

This was tested to compile and produce romstage and ramstage output on a
google/samus board.

Change-Id: Ia93825a1e21a770f6c82d0989cb97980a5c700d6
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/12794
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-12-27 17:45:06 +01:00
Duncan Laurie 791d0580b8 broadwell: Fix SATA Gen3 DTLE configuration registers
The port0 and port1 registers were swapped, which meant it did
not work to apply the DTLE settings to the correct SATA port.

This was tested on an unreleased mainboard but is verified with
the documentation to be the correct register addresses now.

Change-Id: Ifb8890a563a741129ec8ddf72e73ab021c7d33da
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/12793
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-12-27 17:42:58 +01:00
Duncan Laurie 9d08c4a5fd broadwell: Fix CONFIG_SPI_CONSOLE usage
Locking down the SPI controller with a specific opcode menu kills
the SPI console.  Skip this when the SPI console config option is
enabled.

This was tested using an em100 and google/samus board to ensure
the console output does not stop at the finalize step.

Change-Id: Ie460f583214b47544e92d4afa8ef862563a11e36
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/12792
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-12-27 17:42:46 +01:00
Martin Roth d890b45520 ACPI: Add hack to avoid IASL warning when reading back registers
Upcoming versions of IASL give a warning about unused methods.  This
adds an operation after the read to use the local variable and avoid
the warning.

The warning can be completely disabled on the command line, but as it
can find real issues, my preference is to not do that.

Fixes warnings:
dsdt.aml 640: 		           Store (CTMP, Local0)
Warning  3144 - Method Local is set but never used ^  (Local0)

Change-Id: If55bb8e03abb8861e1f2f08a8bcb1be8c9783afe
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12704
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-26 20:53:49 +01:00
david 80ef7b778e IT8772F: Clean up it8772f includes and add a LED API
- Remove it8772f c includes
- Add a new LED API, it8772f_gpio_led
- Stumpy: using it8772f_gpio_led

BUG=chrome-os-partner:28232
BRANCH=Guado
TEST=emerge-guado coreboot chromeos-bootimage

Change-Id: I08de52515d3c1e7e85d1761c09a0cebffda7dda3
Signed-off-by: David Wu <David_Wu@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/241813
Tested-by: David Wu <david_wu@quantatw.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Commit-Queue: David Wu <david_wu@quantatw.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/12797
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-12-26 20:51:29 +01:00
Martin Roth 0fa4f6f23d cpu/allwinner/a10: Fix I2c speed calculation
Looking at the A10 datasheet, N should go in bits 2:0, but
was being cleared by shifting it left by three bits, then
anding it with 7.

Fixes coverity warning:
CID 1241888 (#1 of 1): Wrong operator used (CONSTANT_EXPRESSION_RESULT)
operator_confusion: (n << 3) & (7U /* 7 << 0 */) is always 0 regardless
of the values of its operands. This occurs as the bitwise second operand
of '|'.

Change-Id: I17e71a73adf37a62607e8e5865b1da749d7278aa
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12779
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-12-25 21:51:23 +01:00
Martin Roth c89099641e soc/intel/fsp_baytrail: Make sure i2c bus is < 7
Baytrail has I2c Busses 0 to 6, so is supposed to error out
if the I2c driver is called with 7 or greater.  Due to an off-by-one
error it could be called with bus 7.

Fixes coverity warning:
CID 1287074 (#1 of 1): Out-of-bounds read (OVERRUN)
3. overrun-local: Overrunning array base_adr of 7 4-byte elements at
element index 7 (byte offset 28) using index bus (which evaluates to 7).

Change-Id: I7caec60298cf27bd669796e0e05e4a896f92befd
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12781
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2015-12-22 23:07:20 +01:00
Martin Roth a4c5740752 drivers/intel/fsp1_0/fsp_util.c: Fix indentation
- Also update post code comment to keep under 80 characters.

Change-Id: Id0fd0ee5660f2628fe33188855bebb6e3eea8d2e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12780
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2015-12-22 23:06:44 +01:00
Ionela Voinescu 721f2998a5 imgtec/pistachio: DDR2, DDR3: DLL reset set
Bit 8 of the MR register is automatically set by the PHY
during memory initilization but having it set in the
register leads to a more clear understanding.

Tested on Pistachio bring up board; DDR2 and DDR3 are
initialized properly.

Change-Id: Ie6953e2a96ba2961521b372d280f362ee1c52b94
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12764
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-21 02:06:12 +01:00
Ionela Voinescu 6b95406ff3 imgtec/pistachio: DDR2, DDR3: DQS gate early
Switching on DQS Gate Early and DQS Gate Extension with
500R DQS/DSQN Resistors. This setup was recommended by
Synopsys.

Tested on Pistachio bring up board; DDR2 and DDR3 are
initialized properly.

Change-Id: I6cd3888d506effe71f5d535367525af2e51f6ba3
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12763
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-21 02:05:17 +01:00
Ionela Voinescu f6d3bd4815 imgtec/pistachio: increase CBFS cache
Increase CBFS cache size to allow for a bigger payload.

Change-Id: I47404ba9bbe95f6610189b971504019c0a1a81f0
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12762
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-21 02:04:21 +01:00
Martin Roth 2b2ff7fa6a soc/intel/broadwell: Init var before use, only use when needed
root_port_init_config() pcie.c wasn't initializing a variable before
passing its pointer to pch_iobp_exec(). pch_iobp_exec() wrote the
uninitialized value into a register.
In theory, the register would only be used if data was being written,
and pch_iobp_exec()  was being used to read the data, not write it, so
this change shouldn't have any practical effect.

Fixes coverity error:
CID 1293134 (#1 of 1): Uninitialized scalar variable (UNINIT)

Change-Id: I5d17863d904c6b1ceb30d72b94cd7a40c8fbb437
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12778
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
2015-12-20 02:41:57 +01:00
Timothy Pearson 1eaaa0e446 southbridge/amd/sr5650: Add MCFG ACPI table support
As the southbridge largely controls the PCI[e] configuration space
this patch moves the resource allocation from the northbridge
to the southbridge when the extended configuration space region
is enabled.

Change-Id: I0c4ba74ddcc727cd92b848d5d3240e6f9f392101
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12050
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-12-18 19:51:44 +01:00
Timothy Pearson 5f2bf6d02d mainboard/asus/kgpe-d16: Enable CBFS spinlocks
Change-Id: I8f6226d3e74ac5c7f29f708128a7502ced1287bf
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12062
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-18 19:48:52 +01:00
Timothy Pearson 7b22d84d55 drivers/pc80: Add optional spinlock for nvram CBFS access
When enabling the IOMMU on certain systems dmesg is spammed with I/O page faults like the following:
AMD-Vi: Event logged [IO_PAGE_FAULT device=00:14.0 domain=0x000a address=0x000000fdf9103300 flags=0x0030]

Decoding the faulting address:
0x000000fdf9103300
        fdf91x          Hypertransport system management region
              33        SysMgtCmd (System Management Command) = 0x33
              3         Base Command Type = 0x3: STPCLK (Stop Clock request)
               3        SMAF (System Management Action Field) = [3:1] = 0x1
               1        Signal State Bit Map = [0] = 0x1

Therefore, the error appears to be triggered by an upstream C1E request.

This was eventually traced to concurrent access to the SP5100's SPI Flash controller by
multiple APs during startup.  Calls to the nvram read functions get_option and read_option
call CBFS functions, which in turn make near-simultaneous requests to the SPI Flash
controller, thus placing the SP5100 in an invalid state.  This limitation is not documented
in any public AMD errata, and was only discovered through considerable debugging effort.

Change-Id: I4e61b1ab767b1b7958ac7c1cf20eee41d2261bef
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12061
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-18 19:47:01 +01:00
Stefan Reinauer 5a3f1e54d5 cpu/samsung/exynos5250: Move update-bl1.sh to 3rdparty/blobs/
The binary is taken from blobs, so the script should live over
there, too.

Change-Id: I3cc0aabc846c352ccf5cb348132b320a37f273a6
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/12725
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-12-18 19:06:11 +01:00
Werner Zeh 1f7395bb4d siemens/mc_tcu3: Set GPIO_S0_SC[75] to output
The usage of the pin has changed and therefore this pin needs
to be set up as output and drive low initially.

Change-Id: Ie3eb9cc703f7f73d59fad52ea9e514997d84606a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/12754
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-12-18 10:48:22 +01:00
Denis 'GNUtoo' Carikli d18f81be85 google/veyron: Add commercial board names in Kconfig.name
The correspondence between engineering code names and
commercial names can be found on chromium.org website at:
https://www.chromium.org/chromium-os/developer-information-for-chrome-os-devices

This it to make the names more relevant:
towiki (in util/board_status/to-wiki/towiki.sh) will pick such
names, which end up in the supported board list at:
http://www.coreboot.org/Supported_Motherboards

Change-Id: I2d705672d7202964fea3f62a5bd61a231d3f14c0
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: https://review.coreboot.org/12652
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2015-12-17 21:53:48 +01:00
Denis 'GNUtoo' Carikli 3747ba16c7 Kconfig: Fix CONFIG_GDB_STUB dependencies
If we select CONFIG_GDB_STUB without CONFIG_SERIAL:

build/console/console.romstage.o: In function `__gdb_hw_init':
[...]src/include/console/uart.h:74: undefined reference to `uart_init'
build/console/console.romstage.o: In function `__gdb_tx_byte':
[...]/src/include/console/uart.h:75: undefined reference to `uart_tx_byte'
build/console/console.romstage.o: In function `__gdb_tx_flush':
[...]/src/include/console/uart.h:76: undefined reference to `uart_tx_flush'
build/console/console.romstage.o: In function `__gdb_rx_byte':
[...]/src/include/console/uart.h:77: undefined reference to `uart_rx_byte'

Note that CONFIG_GDB_STUB should also work trough usbdebug,
But due to the lack of testing, it has been disabled when added.
This commit gives more information on the issue:
f2f7f03 console: Add console for GDB

Change-Id: I9accf8189dfd2c4ae379c03649d2e5863183457b
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: https://review.coreboot.org/12708
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-17 21:35:26 +01:00
Denis 'GNUtoo' Carikli e87e73edba google/veyron: Indicate which boards are laptops.
This is to make towiki pick that information, to make
these boards end up in the laptop list at:
http://www.coreboot.org/Supported_Motherboards

Change-Id: Ibf8bf4bf6566080a34687e36675d4c4c8b89f334
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: https://review.coreboot.org/12716
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-17 21:30:08 +01:00
Stefan Reinauer c32e80d604 Drop src/cpu/ indirection for MIPS
Change-Id: I406166e650e07851ab1b293450fa29da8af075d9
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/12724
Tested-by: build bot (Jenkins)
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2015-12-17 21:25:31 +01:00
Ionela Voinescu 2e8d4ed794 soc/imgtec/pistachio: add implementation for system reset
Implement system reset by calling the watchdog soft reset.
Following the soft reset, the SoC will reset to the same logic
state and therefore have the same effect as a hard (power-on)
reset except for:
 - watchdog scratch registers will be unaffected (hard reset
   will clear them)
 - the real time clock will be unaffected

BUG=none
TEST=tested on Pistachio bring up board

Change-Id: I1332c2249c756f6d8574fc5c407de52f88e60f08
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12755
Tested-by: build bot (Jenkins)
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2015-12-17 21:13:57 +01:00
Stefan Reinauer 3bdd45e714 soc/imgtec/pistachio: Implement hard_reset()
Verified boot needs hard_reset() now, so offer a dummy implementation
for the Imagination chip. Sorry, I don't have the specs for this chip
anymore to make a real implementation, but I would like to keep this
code from bit rotting.

Change-Id: I15aa47f7d248b99901a2ac0e65a46b43d7718717
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/12723
Tested-by: build bot (Jenkins)
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2015-12-17 21:13:35 +01:00
Julius Werner 74babffccb vendorcode: google: chromeos: Remove old fmap.c file
This file became obsolete when FMAP code moved to src/lib/ and is no
longer built by any Makefile. Let's remove it to avoid confusing people.

Change-Id: I55639af28f9f3d4c4cb0429b805e3f120ecc374e
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12753
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2015-12-17 19:55:26 +01:00
Martin Roth ffcd9393a4 soc/intel/fsp_baytrail: Adjust root port INT routing
Adjust the root port INT routing based on Bay Trail spec:
Document Number: 538136, Rev. 3.9

Table 241. Interrupt Generated for INT[A-D] Interrupts
             INTA  INTB  INTC  INTD
Root Port 1 INTA# INTB# INTC# INTD#
Root Port 2 INTD# INTA# INTB# INTC#
Root Port 3 INTC# INTD# INTA# INTB#
Root Port 4 INTB# INTC# INTD# INTA#

Change-Id: I22a8c0bc6ad731dfb79385d6e165f1ec0a07507d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12684
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Ben Gardner <gardner.ben@gmail.com>
2015-12-17 18:08:52 +01:00
Ben Gardner 6fc544d3d4 intel/fsp_baytrail: change indent to use tabs
Change-Id: If0d0a15442738bab0e34f1b05513e7f8e8fa9afc
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/12698
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-16 04:53:54 +01:00
Martin Roth 35272fd237 northbridge/intel ACPI: Remove unused Local method
The remainder of the divide operation was being placed into a Local,
but was never being used, causing an IASL warning.  Since this
field is optional, just remove the Local.

Fixes IASL warning:
dsdt.aml 640:Divide (Multiply (CTDN, 125), 100, Local0, PL2V)
Warning  3144 - Method Local is set but never used ^  (Local0)

Change-Id: I0b43ef638b1bc3e1163c45f31f8da57aa0d39e22
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12706
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2015-12-16 04:49:30 +01:00
Ben Gardner 6b07cba70f x86/smbios: Return index 0 for empty strings
Section 6.1.3 (Text Strings) of the SMBIOS specification states:
  If a string field references no string, a null (0) is placed in that
  string field.

Change smbios_add_string() to do that.

Change-Id: I9c28cb89dcfe2c8ef2366c23ee6203e15b7c2513
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/12697
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-16 01:20:00 +01:00
Hannah Williams 03d4ae7684 lib: Fix strncmp
strncmp continues to compare the characters in the input strings past any
null termination it may encounter. Null termination check is added.

Reviewed-on: https://chromium-review.googlesource.com/314815
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Hannah Williams <hannah.williams@intel.com>
Tested-by: Hannah Williams <hannah.williams@intel.com>
(cherry picked from commit ca7022752115eddbcb776f0c0d778249555ddf32)
Reviewed-on: https://chromium-review.googlesource.com/315130

Change-Id: Ifc378966dcf6023efe3d32b026cc89d69b0bb990
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/12721
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-12-16 01:14:22 +01:00
Ben Gardner fa6014a6ec intel/fsp_baytrail: rename include folder baytrail to include/soc
This is to match the layout of the non-fsp baytrail to make comparisons
easier and possibly remove duplicate files.

Change-Id: I9a94842d724ab3826de711d398227e7bdc1045ff
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/12686
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-16 01:10:06 +01:00
Martin Roth 1e1c7ac3b4 southbridge/amd/sb600: Update HPET base address with #define
The SB600 code had the base address of the HPET hardcoded throughout.
It looks like the plan was to have it be updated in ACPI if needed,
but this wasn't ever implemented.  The variable names being used to
do this update were the same, causing an IASL warning.  Because of
this, the operation to update the HPET address actually did nothing.
This was fine, because it didn't actually need to be updated.

- Replace all that code with a #define.
- Add and update some comments in the same area.

Fixes IASL warning:
dsdt.aml   1505:       Store(HPBA, HPBA)
Warning  3023 -                      ^ Duplicate value in list (Source is the
same as Target)

Change-Id: I9ba5fe226a4a464e0045ce7d3406898760df5e5a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12705
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-12-16 00:56:08 +01:00
Ben Gardner 49bbfcd5d3 intel/fsp_baytrail: Fix PCI_DEV_PIRQ_ROUTE macro ending
The macro PCI_DEV_PIRQ_ROUTE ends with a comma and escaped newline.
Ending a macro with an escaped newline is always wrong.
The final comma is not necessary, as all uses of PCI_DEV_PIRQ_ROUTE()
properly separate calls with a comma.

I haven't investigated whether this is causing a real issue, but it should
be leaving gaps in struct baytrail_irq_route.pcidev.

The non-FSP baytrail does not have this issue.

Change-Id: If6782176068b07cb3bc819c00d1cdb1b618bcea8
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/12696
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2015-12-16 00:53:48 +01:00
Alexander Couzens b619f44c67 build system/x86: depend on directories before touch /empty targets
$(objgenerated)/empty would touch files before the directory
is created on parallel builds.

Thanks to reproducible-builds.org for hitting this bug.

Change-Id: I7565e9fe130b4e9deaf1c7b9d568ff90b00dda52
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/12717
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-16 00:43:22 +01:00
Stefan Reinauer 747d0f898b soc/samsung/exynos5250: Implement hard_reset()
Implement hard_reset() as power_reset() to make
vboot happy.

Change-Id: I16831055bd6ba8a8c95836fcf31f29c068153fcc
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/12722
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
2015-12-16 00:41:03 +01:00
Stefan Reinauer 490006bf7d intel/skylake: Work around ROMCC optimization bug
On Skylake systems, the bootblock fails to compile with the following
error message:

bootblock_simple.c:6.1:
0x13930e0 copy       Internal compiler error: non dominated rhs use point
0x13a3f70?
Aborted (core dumped)

The option -fno-simplify-phi works around the issue, but will cause the
code to use more registers, hence we also need to enable -mcpu=p4 (see
intel/truxton mainboard for another example of where this has been done
in the past)

Change-Id: Iea1a1ba18d76c7323bb626c5f4b0032e4ee04a86
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/12719
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-16 00:31:23 +01:00
Aaron Durbin 07a1b281a8 x86 acpi: remove ALIGN_CURRENT macro
The ALIGN_CURRENT macro relied on a local variable name
as well as being defined in numerous compilation units.
Replace those instances with an acpi_align_current()
inline function.

Change-Id: Iab453f2eda1addefad8a1c37d265f917bd803202
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12707
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-15 20:12:01 +01:00
Timothy Pearson ecd4cfcb86 mainboard/asus/kgpe-d16: Enable romstage spinlocks
Change-Id: Iac1adbeacdcded7faff2443b78a491cbb8a90fe8
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12628
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-15 16:43:09 +01:00
Timothy Pearson 44d5342835 src/console: Add x86 romstage spinlock option and printk spinlock support
This paves the way for AP printk spinlock on AMD platforms

Change-Id: Ice42a0d3177736bf6e1bc601092e413601866f20
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/11958
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-15 16:41:13 +01:00
Martin Roth a09bb426d4 google/oak: Move CHROMEOS specific Kconfig objects under CHROMEOS
The symbols CHROMEOS_VBNV_EC, EC_SOFTWARE_SYNC, and VIRTUAL_DEV_SWITCH
should only be selected if CHROMEOS is selected.

Change-Id: I07ef631d63be53cf99a6bf61d0e91b88728dbba3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12659
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-15 01:14:27 +01:00
Timothy Pearson 16ff807ba6 amd/[nb/fam10|sb/sr5650]: Minor cosmetic changes
Change-Id: Ia9cb4fe4f46327e38648f89da0ffce647fb118d3
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12712
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-13 02:20:12 +01:00
Patrick Georgi 8a3592eec3 build system: Switch to fmap based firmware layout
We still add a master header for compatibility purposes, and the default
layouts don't cover anything non-coreboot (eg. IFD regions) yet.

The default layouts can be overridden by specifying an fmd file, from
which the fmap is generated.

Future work:
- map IFD regions to fmap regions
- non-x86: build minimalistic trampolines that jump into the first cbfs
  file, so the bootblock can be part of CBFS instead of reserving a
  whole 64K for it.
- teach coreboot's cbfs code to work without the master header
- teach coreboot's cbfs code to work on different fmap regions

Change-Id: Id1085dcd5107cf0e02e8dc1e77dc0dd9497a819c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/11692
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2015-12-11 11:40:18 +01:00
Aaron Durbin 929b60267c fsp1_1: supply fsp version to mrc_cache API
The memory init code needs to match the saved mrc data. To
ensure that invariant holds supply the FSP version when
using the mrc cache API.

BUG=chrome-os-partner:46050
BRANCH=None
TEST=Built and booted on glados. Verified version mismatch checking
     works.

Change-Id: I3f6dd19cb15a18761d34509749adafc89a72ed2d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12701
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-11 00:20:08 +01:00
Aaron Durbin bc6e7c0905 mrc_cache: add version field
In order to allow for updateable memory init code on intel x86
platforms one needs to ensure the saved mrc data matches the code
consuming the data. To that end add a version field to the saved
data structure.

BUG=chrome-os-partner:46050
BRANCH=None
TEST=Built and booted on glados. Suspended and resumed. Also verified
     version mismatch path.

Change-Id: Ie86db1750af5d9bff6446999b0d04b60612f8d29
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12700
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-11 00:20:02 +01:00
Martin Roth a606598150 ati/ragexl: Change .h #defines named CONFIG_ to CFG_
The CONFIG_ prefix should be reserved for Kconfig symbols.

Change-Id: I1d3141e0f5f9e1161bc7f88158af8a5d5780829c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12564
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2015-12-10 16:46:23 +01:00
Martin Roth f79062f478 soc/mediatek/mt8173: SPI_ATOMIC_SEQUENCING depends on SPI_FLASH
Don't select SPI_ATOMIC_SEQUENCING unless SPI_FLASH is being used.

warning: (... SOC_MEDIATEK_MT8173) selects SPI_ATOMIC_SEQUENCING
which has unmet direct dependencies (SPI_FLASH)

Change-Id: I93e9a7102d1d0ef62565110b5b3b677da8d0c72b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12657
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-10 16:37:05 +01:00
Martin Roth ae1bab3c9d emulation/qemu-arm7: Fix Kconfig symbols for stage compilers
These had typos ARM_STAGE_ARM7 instead of ARCH_STAGE_ARM7

Change-Id: Iffe8fecb3e52a50ff02b774478a10c353093688b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12660
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-10 16:36:04 +01:00
Martin Roth 3e41ee9847 ACPI: Fix IASL Warning about unused method for _S3 check
According to the ACPI Spec for CondRefOf, the result argument is
optional.  In all of these locations, it was getting set but not
used, creating a warning in new versions of IASL.  Since it's
an optional argument, just remove it.

dsdt.aml 640:              If (CondRefOf (\_S3, Local0))
Warning  3144 - Method Local is set but never used ^  (Local0)

Change-Id: I758d198c33e585a6a4ad2c1c70f2370a01af5138
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12693
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-10 16:32:56 +01:00
Martin Roth f77516cb6d ACPI: Work around IASL warning reading/writing same register
The newer versions of IASL are unhappy when an operator
has the same object as both source and destination.

The warning can be completely disabled with a command
line argument, but in general, I'd really rather not
just disable warnings.

The bits in this register are write 1 to clear, so reading and
writing the same register is what we want to do.  Instead, store
it in a temporary register then write it in a second operation.

Fixes warning:
dsdt.aml   1396:  Store(PWST, PWST)
Warning  3023 -                 ^ Duplicate value in list
(Source is the same as Target)

Change-Id: I52d73d4431db237be83016d67cd397f31b53d9c6
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12691
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-10 16:32:21 +01:00
Martin Roth 91d9cbc2fb ACPI: Fix IASL Warning about unused method for _OSI check
According to the ACPI Spec for CondRefOf, the result argument is
optional.  In all of these locations, it was getting set but not
used, creating a warning in new versions of IASL.  Since it's
an optional argument, just remove it.

dsdt.aml     22:   if(CondRefOf(\_OSI,Local1))
Warning  3144 -                           ^
Method Local is set but never used (Local1)

Change-Id: I07f49ac5a3708838d1c4a7216dfb11acc415c881
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12692
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-10 16:31:35 +01:00
Martin Roth 5a98bf2c0a ACPI: Fix IASL Warning about unused method for _TZ checks
According to the ACPI Spec for CondRefOf, the result argument is
optional.  In all of these locations, it was getting set but not
used, creating a warning in new versions of IASL.  Since it's
an optional argument, just remove it.

dsdt.aml 640:              If (CondRefOf (^GBUF, Local0)) {
Warning  3144 - Method Local is set but never used ^  (Local0)

Change-Id: Iddf46a4faab19019882847917397eee0614302b9
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12695
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-10 16:31:14 +01:00
Martin Roth 10f7f5044e ACPI: Fix IASL Warning about unused method for GBUF check
According to the ACPI Spec for CondRefOf, the result argument is
optional.  In all of these locations, it was getting set but not
used, creating a warning in new versions of IASL.  Since it's
an optional argument, just remove it.

dsdt.aml 640:              If (CondRefOf (^GBUF, Local0)) {
Warning  3144 - Method Local is set but never used ^  (Local0)

Change-Id: Ie2f46808e92c309a63ba7661bcbd77402a08366a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12694
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-10 16:30:50 +01:00
Ben Gardner fad2313400 intel/fsp_baytrail: Remove code for nonexistant BBAR
The BBAR register (BIOS Base Address Configuration Register) defined in
the ICH9 datasheet does not exist in the Bay Trail E3800 datasheet.
Accessing it seems harmless, but should likely be avoided.

Change-Id: I5d9a6a1ccead84c8996796f516a2bdc5f248cfef
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/12671
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-10 08:25:47 +01:00
Aaron Durbin 7e7a4df580 lib: remove assets infrastructure
Now that only CBFS access is supported for finding resources
within the boot media the assets infrastructure can be removed.
Remove it.

BUG=chromium:445938
BRANCH=None
TEST=Built and ran on glados.

Change-Id: I383fd6579280cf9cfe5a18c2851baf74cad004e9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12690
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-10 04:44:09 +01:00
Aaron Durbin 6d720f38e0 cbfs/vboot: remove firmware component support
The Chrome OS verified boot path supported multiple CBFS
instances in the boot media as well as stand-alone assets
sitting in each vboot RW slot. Remove the support for the
stand-alone assets and always use CBFS accesses as the
way to retrieve data.

This is implemented by adding a cbfs_locator object which
is queried for locating the current CBFS. Additionally, it
is also signalled prior to when a program is about to be
loaded by coreboot for the subsequent stage/payload. This
provides the same opportunity as previous for vboot to
hook in and perform its logic.

BUG=chromium:445938
BRANCH=None
TEST=Built and ran on glados.
CQ-DEPEND=CL:307121,CL:31691,CL:31690

Change-Id: I6a3a15feb6edd355d6ec252c36b6f7885b383099
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12689
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-10 04:43:58 +01:00
Martin Roth 9ed54f99c7 mohonpeak/Kconfig: Fix whitespace issues
Auto-indent did me wrong, and I didn't notice it.

Change-Id: I5a736cf53a3bdbe57b28b2d6a55befd341d8dfd8
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12655
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-12-09 16:18:14 +01:00
Timothy Pearson 0a105cd067 sb/amd/sb700: Enable watchdog timer for OS use
Change-Id: Ib0281139cafe74a22a24a377b3fdec1c59e934f3
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12687
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-09 16:17:48 +01:00
Patrick Georgi e7cd0f889e google/oak: define flash size
We never defined the flash size for this board, so the (too small)
default was used. Instead, adopt the size given in depthcharge's fmap
description.

Change-Id: I63782922ee05a9595d6c0de56750460ebb67aec6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/12674
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-12-09 09:20:50 +01:00
Zheng Bao a962e062cb amdfwtool: Hide the prefix of target
Make the definitions of rules compliant with
others.

Change-Id: Ieef3a9c3fae5beaa1ea3e14e890cfb9145090c3b
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/12685
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-09 02:17:33 +01:00
Zheng Bao 1fa2809561 AMD/bettong: Add missing uart.c for UART
Change-Id: Ie49732c6874f2b443e314eb3412ddee054d9c0bb
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/12669
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-09 02:17:08 +01:00
Timothy Pearson 72c83a8e23 sb/amd/sr5650: Allow resource allocator to assign bus numbers
At some point in the past disconnected PCIe bridges were completely
disabled to work around a hang on bridge probe.  This hang was
resolved at some point, and the disconnected PCIe bridges should
be enabled to receive a bus number per the RPR.

This resolves a slew of warnings in the Linux boot log regarding
invalid bridge configurations for disconnected bridge devices.

Change-Id: Ic26e2d62ec5ddb9f22275c2afec7d560326263c7
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12673
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-12-08 22:08:54 +01:00
Martin Roth c7c30a8400 vendorcode/google/chromeos: Only select ELOG if SPI_FLASH is available
ELOG requires SPI_FLASH, so don't bother selecting if if SPI_FLASH isn't
available.

Change-Id: I080ac47e74aba820c94409d4913647abee215076
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12661
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-08 17:14:13 +01:00
Martin Roth d7ad21aa5c intel/strago: Remove CONFIG_ from CONFIG_GOP_SUPPORT inside Kconfig
The CONFIG_ is only used for Kconfig symbols outside of Kconfig.  If
used inside Kconfig, you'd end up with CONFIG_CONFIG_GOP_SUPPORT when
it was used in the C code.

Change-Id: I572323ef08fdd937d33ded1c27a418b3ad856147
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12664
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-08 17:13:52 +01:00
Martin Roth 9c073ed2fd console: Allow ARM64 platforms to select bootblock console
Change-Id: I09943aafe29f6e7a2a878e7b6141661982dfc645
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12658
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-08 17:13:18 +01:00
Martin Roth db557477a2 soc/intel/common: Remove USE_FMAP - symbol doesn't exist
The USE_FMAP Kconfig symbol doesn't exist, so remove things that are
depending on it not being enabled.

Change-Id: I1946f5d13a762ab07744a1d9a6cb754433e6701d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12663
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-08 16:45:58 +01:00
Francis Rowe 66d0f11115 lenovo/t500: Add clone of Lenovo T400
The existing code for the Lenovo T400 works without changes on the
Lenovo T500.  Same HDA verbs are provided by Lenovo BIOS on both
laptops.

Change-Id: I300408a8a0ed00476aee6061925befc2822fb505
Signed-off-by: Francis Rowe <info@gluglug.org.uk>
Reviewed-on: https://review.coreboot.org/10545
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-08 16:44:40 +01:00
Martin Roth 55b147ddef soc/intel/skylake: Remove obsolete Kconfig symbols
CPU_MICROCODE_IN_CBFS was renamed to SUPPORT_CPU_UCODE_IN_CBFS in commit
66e0c4c8 (cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFS)
Both CPU_MICROCODE_IN_CBFS and SUPPORT_CPU_UCODE_IN_CBFS were present,
so just remove CPU_MICROCODE_IN_CBFS.

SMM_MODULES was removed in
commit 44cbe10f (smm: Merge configs SMM_MODULES and SMM_TSEG)

Change-Id: Icdd4fcc5a3a97aee443742aaab3df92b53ff4589
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12662
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-08 16:25:44 +01:00
Patrick Georgi 704662a4b9 qemu-x86: Enable SMP support
QEMU can do this for a while now.

Change-Id: I3a5027a7afc9dd18463d26cb42fe68747a89f6b0
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: https://review.coreboot.org/12656
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-12-08 15:54:27 +01:00
Martin Roth 6215b88aee northbridge/amd/agesa/agesawrapper.c: Fix Kconfig symbols
The Kconfig symbols were missing an underscore, so were not getting
evaluated properly.

Change-Id: I619cf3f44f44f9c9699482d64164d3db28cd4c8f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12559
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-12-08 00:11:18 +01:00
Zheng Bao e1e9ed37da AMD/bettong: Remove the useless period (trivial)
It seems that no one add period in Kconfig.

Change-Id: Ie9c585a8e6f1a73036b92b2873dc19284d82dc39
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/12668
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2015-12-08 00:01:53 +01:00
Martin Roth b790fe944d intel/littleplains: Update with recent changes to mohonpeak
- Change SEABIOS_MALLOC_UPPERMEMORY to using PAYLOAD_CONFIGFILE.
- Add saved seabios .config with CONFIG_MALLOC_UPPERMEMORY unset.
- Remove fixed microcode location.

Change-Id: I8b723edf6d6b5542f118e9e0e1aee8104d9cde86
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12635
Tested-by: build bot (Jenkins)
Reviewed-by: David Guckian <david.guckian@intel.com>
2015-12-08 00:01:26 +01:00
Martin Roth b9de78beb6 intel/common/firmware: Add option to configure SPI for EM100
Add a Kconfig option to set the firmware descriptor to allow EM100 use.

Change-Id: If5d7cd6ad671f0328ee5be0b5e660dbc837fcac3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12637
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-12-08 00:01:03 +01:00
Timothy Pearson 369b561315 mainboard/asus/kgpe-d16: Use I/O PCI access in bootblock
The existing code incorrectly used standard PCI access
calls in the bootblock.  Use the I/O PCI access calls
as the normal PCI access mechanisms have not yet been
set up.

Also ensure the recovery jumper GPIO has been set to
input mode before reading it.

Change-Id: Id626d01526427004b2404e4d9b44d7c987d172d1
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12651
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-12-07 17:06:31 +01:00
Ben Gardner d347f6cb0b fsp_baytrail: Add missing newline to eMMC Mode log
Change-Id: Icd697053c2ea1a2ac42bdd045134d223d93d5403
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/12623
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-06 18:50:30 +01:00
Martin Roth eca844b949 pcengines/apu1: Supply _HID object for ACPI GPIO devices
The _HID was present for the top level BTNS and LEDS Devices, but
was missing in the individual devices.

The alternative would be to supply the GPIO being used as an _ADR
object, but since it looks like the driver already has another
method of handling that, it isn't required.

Fixes these IASL warnings:
dsdt.aml   1522:   Device (BTN1)
Warning  3141 -              ^ Missing dependency
(Device object requires a _HID or _ADR in same scope)
dsdt.aml   1567:   Device (LED1)
Warning  3141 -              ^ Missing dependency
(Device object requires a _HID or _ADR in same scope)
dsdt.aml   1576:   Device (LED2)
Warning  3141 -              ^ Missing dependency
(Device object requires a _HID or _ADR in same scope)
dsdt.aml   1587:   Device (LED3)
Warning  3141 -              ^ Missing dependency
(Device object requires a _HID or _ADR in same scope)

Change-Id: I67c48084a6ee2a104ffff2b5a986d24a51ee49e1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12582
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-06 18:49:26 +01:00
Martin Roth 49fdf3f957 intel/fsp_rangeley: change non-existent config options to #defines
Kconfig symbols CONFIG_ACPI_INCLUDE_PMIO and CONFIG_ACPI_INCLUDE_GPIO
were never added to the coreboot codebase when the Rangeley code was
brought in from Sage.  These symbols disabled ACPI code that was unused
because it caused dmesg warnings due to conflicts with drivers trying to
claim the same addresses as the ACPI code.  Because it could be used on
some other platforms, it was left in instead of being completely
removed.

- Change the Kconfig symbol names to simple #defines in the mainboard
code.
- Add the #defines along with comments to the reference platform.
- Hook everything together in dsdt.asl
- Update new mainboard littleplains the same way.

Change-Id: I1f62157c6e447ea9b7207699572930e4711fc3e0
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12552
Reviewed-by: David Guckian <david.guckian@intel.com>
Tested-by: build bot (Jenkins)
2015-12-06 18:46:47 +01:00
Martin Roth 7c38e1e8bc Remove #ifdef checks on Kconfig symbols
In coreboot, bool, hex, and int type symbols are ALWAYS defined.

Change-Id: I58a36b37075988bb5ff67ac692c7d93c145b0dbc
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12560
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-06 18:46:12 +01:00
Martin Roth 19fbdcc828 amd/pi/00660F01: Remove 'PER_DEVICE_ACPI_TABLES'
The PER_DEVICE_ACPI_TABLES Kconfig symbol is no longer used as it was
removed in commit 83f81cad (acpi: Remove monolithic ACPI)

Change-Id: Ie6ba252f6e7d33da9d4500f1201367f116e4c505
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12554
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-06 18:45:02 +01:00
Martin Roth ad4764dddd hp/pavilion_m6_1035dx: Fix IASL warning - Missing _HID object
- Add System board _HID object.
- Remove Kconfig default disabling IASL warnings as errors

Fixes warning:
dsdt.aml     64:  Device (MB) {
Warning  3141 -           ^ Missing dependency
(Device object requires a _HID or _ADR in same scope)

Change-Id: I4fa6ab2a6744d58ded8b0feb361e002d90e11474
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12532
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-06 18:43:36 +01:00
Martin Roth d49bbff8ff Rangeley: Change A, A, A, A INT routing to A, A, A, B
Devices that have their interrupt routing set to A, A, A, A don't get
any interrupt values assigned because that series evaluates to 0.  The
code that sets the interrupt values checks to make sure a value is set
by verifying that it's not 0.  On Bay Trail, these are all
single-function graphics devices, so by changing one of the unused
interrupt lines from A to any other value, it assigns the values
correctly.

This issue did not affect ACPI interrupt routing.

This is just a workaround, and the root issue still needs to be fixed.

Change-Id: I4e6fe56084cbe86b309da15d61b296f1936458ec
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12630
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-06 18:43:11 +01:00
Martin Roth cf752fe966 fsp_baytrail: Change A, A, A, A IRQ routing to A, A, A, B
Devices that have their interrupt routing set to A, A, A, A don't get
any interrupt values assigned because that series evaluates to 0.  The
code that sets the interrupt values checks to make sure a value is set
by verifying that it's not 0.  On Bay Trail, these are all
single-function graphics devices, so by changing one of the unused
interrupt lines from A to any other value, it assigns the values
correctly.

This issue did not affect ACPI interrupt routing.

This is just a workaround, and the root issue still needs to be fixed.

Change-Id: I78866e3e0079435037e457a4fb04979254b56ee2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12629
Tested-by: build bot (Jenkins)
Reviewed-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-06 18:42:03 +01:00
Martin Roth 242ee89f98 southbridge/intel/fspi89xx: Don't include common/firmware makefile
The folder southbridge/intel/common/firmware is already being included
so does not need to be added a second time here.

Change-Id: I60d795a60c772547278a5a5e0c9a023a93f90417
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12636
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-06 18:38:15 +01:00
Martin Roth ea7b636607 fsp_model_406dx: use external microcode .h files for rangeley
The microcode for the Rangeley chip is supplied as .h files in the
Rangeley FSP POSTGOLD4 package.

When the rangeley microcode gets put into the blobs directory, this
can be reverted and the binary file put into the makefile.

Change-Id: I30e7436f26a247bc9431f249becfa5fe8c581be7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12335
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-06 18:36:12 +01:00
Martin Roth c4fa3fdd3e intel/eagleheights: Fix IASL warnings
The eagleheights platform had 3 warnings:

The SIO device needs an _ADR object to specify the address in addition
to the operating region.

Not all the paths through the _OSC method returned a value.  According
to the ACPI spec (5.0 & 6.0), bit 2 needs to be set for an unrecognized
GUID.

dsdt.aml    341:   Device(SIO) {
Warning  3141 -            ^ Missing dependency
(Device object requires a _HID or _ADR in same scope)
dsdt.aml  140: Method (_OSC, 4)
Warning  3115 -          ^ Not all control paths return a value (_OSC)
dsdt.aml  140: Method (_OSC, 4)
Warning  3107 -          ^ Reserved method must return a value
(Buffer required for _OSC)

- Remove Kconfig default disabling IASL warnings as errors.

Change-Id: Iab52f19b96468e142b06430d99ba1d9f367d126e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12522
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-06 18:35:48 +01:00
Yidi Lin 762cdfaaa0 google/oak: Add timestamps in romstage
BUG=none
TEST=emerge-oak coreboot
BRANCH=none

Change-Id: Idf74265c9c1ab3a1a74fd18dfd289fccad25177e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 569c433886b19cd08d168e995bf34156c2ba6963
Original-Change-Id: I07fda6a0719d49e2c07249276ae2cc0b57fdfeda
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292660
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12610
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-04 21:52:59 +01:00
Biao Huang 0dd8315bcc mediatek/mt8173: Add APIs for PMIC GPIO control
BRANCH=chromeos-2015.07
BUG=none
TEST=verified on Oak rev3

Change-Id: Ied991f13b73e70b91cc267222f351b588df8df66
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4bc08ce28611d8b940642483c09614d2b8205c1f
Original-Change-Id: If78e154ff7f553f65aa44d370820cc8c7f829c96
Original-Signed-off-by: Biao Huang <biao.huang@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/297224
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12609
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-04 21:52:54 +01:00
henryc.chen 31ae314f0f mediatek/mt8173: Add mt6391 PMIC driver
BUG=none
TEST=emerge-oak coreboot
BRANCH=none

Change-Id: I2b9e1fc16183a29ba308313d347f2f0e948e96a7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ee56cab3b5c04838af80690c21d3aa160d71501a
Original-Change-Id: I2eaa0a406c29b7c9012e3c9860967fc3f27a48a5
Original-Signed-off-by: henryc.chen <henryc.chen@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292669
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12608
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-04 21:52:48 +01:00
Michael Tasche 446c5dcd14 esd/atom15: import esd atom15 board
This patch adds esd atom15 board with
Intel Atom E3815 SoC.

Change-Id: I430a40ad8ab3316d34ec5567329370f69db3f15e
Signed-off-by: Michael Tasche <michael.tasche@esd.eu>
Reviewed-on: https://review.coreboot.org/12632
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-04 18:58:26 +01:00
Michael Tasche 4d166f9380 intel/minnowmax: Fix IRQ connection for legacy uart at 0x3f8
The E38xx legacy uart fires IRQ4, not IRQ3.
PCI based IRQ A is switched from IRQ4 to IRQ3,
to get a working IRQ for the legacy uart.

Change-Id: Ibc8e824c92bf1b9a92594ddc5d8a06726c9f1744
Signed-off-by: Michael Tasche <michael.tasche@esd.eu>
Reviewed-on: https://review.coreboot.org/12622
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2015-12-04 18:58:02 +01:00
Timothy Pearson 69056d9452 northbridge/amd/amdht: Reduce excessive romstage array size
Change-Id: Ibcdf5d3927375da5cb72987ae83eaaa789ab9a70
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12573
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-04 18:45:00 +01:00
Martin Roth 1b304cc23c arch/x86/bootblock_normal: Update to use fewer registers
- Move initialization of entry to later in main.
- Make boot_mode an unsigned char - no need to use int.
- Remove unnecessary variable filenames.
- Only get and try to boot fallback once.

Change-Id: I823092c60dd8c2de0a36ec7fdbba3e68f6b7567a
Test: compiled.
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12574
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-04 18:39:29 +01:00
Julius Werner b29bd27b06 cbfs: Fix typo in cbfs_prog_stage_load()
The proper return value to signal an error from cbfs_prog_stage_load()
is -1, not 0.

Change-Id: Ie53b0359c7c036e3f809d1f941dab53f090b84ab
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12633
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2015-12-04 17:52:36 +01:00
Stefan Reinauer 1d05731e11 braswell/skylake: Add FspUpdVpd.h to fix compilation
Imported from cros repo 18ae19c

Change-Id: Ib88ac9b37d2f86d323b9a04cb17a5a490c61ff5b
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/12467
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Tested-by: build bot (Jenkins)
2015-12-04 17:26:26 +01:00
Sergej Ivanov cd920bf1c0 mainboard/biostar/am1ml: Force basic SPI read mode
This patch force AGESA to use basic SPI read mode.
Without it board hangs during spi configure if W25Q32 chip is used.

Change-Id: I3e17cd21702626be5061d2fc14adc0c22f167efb
Signed-off-by: Sergej Ivanov <getinaks@gmail.com>
Reviewed-on: https://review.coreboot.org/12580
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-04 17:07:59 +01:00
Martin Roth c6a8d2ca7b intel/mohonpeak: Change SEABIOS_MALLOC_UPPERMEMORY to config_seabios
Instead of the SEABIOS_MALLOC_UPPERMEMORY option, use a saved SeaBIOS
.config file to do the same thing.

Change-Id: I29110a382b7770329ef938876426e571fbbbb339
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12569
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-12-03 21:53:32 +01:00
CC Ma 86933f89c4 google/oak: Add board_id() and ram_code() implementation
BRANCH=none
BUG=none
TEST=Oak build pass

Change-Id: Ic2fd9b2ec0592d1f7195d72c60dab15961de0a9e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4d0b00a779b87b0b625cc2bccd8f7470b79e6410
Original-Change-Id: Id9f17d64e9e30946817b86ec8cdfe67ea3dbc798
Original-Signed-off-by: CC Ma <cc.ma@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292675
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12607
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03 14:23:33 +01:00
Yidi Lin 65873ca934 google/oak: Implement the code which reads GPIOs for ChromeOS.
BUG=none
BRANCH=none
TEST=emerge-oak corebootk

Change-Id: Ic1a0d640cac7fd98acd06d619736303fa449c0a1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ce465e8cbdf6465c072e476a91a400d78c959218
Original-Change-Id: Iade51db02f45264fdffe387e0563b60e637c0710
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292674
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12606
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03 14:23:29 +01:00
Biao Huang 9d48e1732a google/oak: Initialize the necessary pins
BRANCH=none
BUG=none
TEST=verified on Oak rev2 & rev3

Change-Id: I35776f5bdf54243236afba860ae8e9117a160cde
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b46bd9a079107ab78964f7e39582b3b5c863b559
Original-Change-Id: I6696972d07adbf3da5967f09c1638bb977c10207
Original-Signed-off-by: Biao Huang <biao.huang@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292673
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12605
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03 14:23:25 +01:00
Wisley 1a8e43e4e3 google/chell: update dptf TSR1 & TSR2 critial points
update dptf TSR1 & TSR2 critial points from 70 to 75
TSR1 & TSR2 are reach 68 degree that is close to 70 degree afer SVPT
test, change the point will avoid to trigger critial in our factory
run in test

BRANCH=none
BUG=none
TEST=build and boot chell DUT

Change-Id: Ie5b8b24d82e929a7bd254967b70b61fda2c8bd0a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cf29fee19edf425010cc76af95b7a8e73a3d82bb
Original-Change-Id: Idb9dd77432cfd246c1c612e52c6f945352e265ca
Original-Signed-off-by: Wisley Chen <Wisley.Chen@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313967
Original-Commit-Ready: Duncan Laurie <dlaurie@chromium.org>
Original-Tested-by: Chen Wisley <wisley.chen@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Chen Wisley <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/12604
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03 14:23:21 +01:00
Biao Huang 8c83c65ef3 mediatek/mt8173: Add GPIO driver
BUG=none
TEST=emerge-oak coreboot
BRANCH=none

Change-Id: I54755d81144b27cc9a674434609b2d99f1d486ec
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d88a3ed43ad32e245e54a9599fb8667ce288217b
Original-Change-Id: I1142091650c0de2207c7635031aa7edfe487ad88
Original-Signed-off-by: Biao Huang <biao.huang@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292672
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12603
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03 14:23:05 +01:00
Yidi Lin 5e2cfb5cbb mediatek/mt8173: move PRERAM_CBFS_CACHE from SRAM_L2C
L2C will be released after DRAM is initialized. Move PRERAM_CBFS_CACHE
from SRAM_L2C to ensure that it can be switched correctly.

BRANCH=none
BUG=chrome-os-partner47952
TEST=none

Change-Id: I255a0116148777d384dda43682365a5e2375cb5d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 19fcc170e57da514aee9e22289619729ddc2f792
Original-Change-Id: If3d9c1ef05dee0a10ee9151b63b8fd92cc9def51
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313888
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12602
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03 14:23:01 +01:00
Mary Ruthven a8aef3acbc cbfs_spi: Initialize spi_flash when initializing cbfs_cache
Most devices do not use SPI before they initialize CBMEM. This change
initializes spi_flash in the CBMEM_INIT_HOOK to initialize the postram
cbfs cache so it is not overwritten when boot_device_init is called
later.

BUG=chromium:210230
BRANCH=none
TEST=confirm that the first cbfs access can occur before RAM initialized
and after on panther and jerry.

Change-Id: If3b6efc04082190e81c3773c0d3ce116bb12421f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0ab242786a16eba7fb423694f6b266e27d7660ec
Original-Change-Id: I5f884b473e51e6813fdd726bba06b56baf3841b0
Original-Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/314311
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12601
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03 14:22:55 +01:00
Saurabh Satija 5b242f6307 intel/kunimitsu: Coreboot GPIO changes for FAB 4.
This patch adds GPIO mappings for PCH_BUZZER, AUDIO_DB_ID,
AUDIO_IRQ and BOOT_BEEP.

BUG=chrome-os-partner:47513
BRANCH=none
TEST=Built for kunimitsu but not verified on Fab 4.

Change-Id: I0172df3aa2a5c4bfc24422aa0bfb7e5f677d37c9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ba66bef6d402a1040f0f13bc828de400bc6371b7
Original-Change-Id: I1f2ed8fc283883a523a77e07de14ed90057b719b
Original-Signed-off-by: Saurabh Satija <saurabh.satija@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/311806
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/12600
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03 14:22:50 +01:00
Duncan Laurie 7a2963b86c google/glados: Disable kepler device
Disable the kepler device to save power and enable S0ix testing.
It has been disabled in the ME image and was not working anyway..

BUG=chrome-os-partner:40635
BRANCH=none
TEST=build and boot on glados

Change-Id: I6640c7a09d418ba4b4de6f16138c124436dd8758
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6490769a32539cb6ef429717f021519c152a4a54
Original-Change-Id: If6e384dd2218c6a110747a489329a59fa6433c02
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/313827
Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12599
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-12-03 14:22:42 +01:00
Duncan Laurie 4938feaee5 google/chell: Update mainboard for EVT
- Disable kepler device, it is removed and was not used on proto anyway.
- Enable GPP_D22 as GPO to control I2S2 buffer for bit-bang PDM.
- Disable HS400, this is breaking some devices on proto boards and
is being disabled to reduce risk for EVT build.
- Change Type-C USB2 port drive strength.

BUG=chrome-os-partner:47346
BRANCH=none
TEST=build and boot on chell proto

Change-Id: Icf31f08302c89b2e66735f7036df914c0a0b9e8c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d00abc12efa69a99e6b0272228f52fb29e6b9180
Original-Change-Id: I63bda0b06c7523df9af9aed9b82280133b01d010
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/313825
Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12598
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03 14:22:35 +01:00
Duncan Laurie 8996084f82 intel/skylake: Add ACPI device for audio controller
Add the audio controller device to ACPI and define the _DSM handler
to return the address of the NHLT table, if it has been set in NVS.

BUG=chrome-os-partner:47346
BRANCH=none
TEST=build and boot on glados and chell

Change-Id: I8dc186a8bb79407b69ef32fb224a7c0f85c05bc4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6b73fba375f83f175d0b73e5e70a058a6c259e0d
Original-Change-Id: Ia9bedbae198e53fe415adc086a44b8b29b7f611d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/313824
Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12597
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03 14:22:23 +01:00
Duncan Laurie 21cc96cacd intel/skylake: Remove unused code to add SSDT2
This code is doing nothing and is not needed.

BUG=chrome-os-partner:40635
BRANCH=none
TEST=build and boot on glados

Change-Id: I910d443f09a94de1ee0de03cda0577b8847b2de8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ac09fdd7673e5fceb8bfaf1076a8a91e54fc31af
Original-Change-Id: Id989c82853d5a5d5b750def073d34c39816a48d5
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/313823
Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12596
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03 14:17:56 +01:00
Duncan Laurie fb50983008 intel/fsp: Add post codes for FSP phases
Add post codes for the various FSP phases and use them as appropriate
in FSP 1.0 and 1.1 implementations.

This will make it more consistent to debug FSP hangs and resets.

BUG=chrome-os-partner:40635
BRANCH=none
TEST=build and boot on glados and chell

Change-Id: I32f8dde80a0c6c117fe0fa48cdfe2f9a83b9dbdf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3b616ff3c9d8b6d05c8bfe7f456f5c189e523547
Original-Change-Id: I081745dcc45b3e9e066ade2227e675801d6f669a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/313822
Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12595
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03 14:17:51 +01:00
Dhaval Sharma 590ac64d55 intel/fsp1_1: Add accurate print for full fsp version
Adding print for full fsp revision which includes:
0:7   - Build number
8:15  - Revision
16:23 - Minor version
24:31 - Major version

BRANCH=NONE
BUG=chrome-os-partner:46050
TEST=Built for kunimitsu and tested fsp revision is printed properly.

Change-Id: If2739e7cccd97e4b39da503a9d61222cde03bc95
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c49be46f8d2085a620abac74126de5c3b634e649
Original-Change-Id: I2223cce22fb3d39faa37902d415d5fdbe321add6
Original-Signed-off-by: Dhaval Sharma <dhaval.v.sharma@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/310173
Original-Commit-Ready: dhaval v sharma <dhaval.v.sharma@intel.com>
Original-Tested-by: dhaval v sharma <dhaval.v.sharma@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12594
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03 14:17:48 +01:00
david 1fc5d1f01a google/lars: SPD change for Proto board
Update Memory ID for Proto board
Update detection of single/dual channel memory to use SPD Index (Memory ID)
Remove boardid.h as it is no longer needed

BUG=None
BRANCH=None
TEST=Build and Boot Lars (Proto)

Change-Id: I100b0fec4bf555c261e30140109cb0f36576130c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 24a4fddf4f1a4441fca8783cfa451e220ff986d8
Original-Change-Id: I636e881cb3fb9a0056edea2bc34a861a59b91c8f
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313903
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/12593
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03 14:17:44 +01:00
Brandon Breitenstein a009158bf9 intel/kunimitsu: Updated Micron SPD data
Updated Micron SPD data to correct values

BUG=none
BRANCH=none
TEST=Tested on FAB 4 with Micron Dimm
CQ-DEPEND=CL:312546

Change-Id: Iffe2917f083e4de7944c7f249cbf55bd199f6282
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 00234d81df38139312145c89cbf38d8ac3af5735
Original-Change-Id: Ifcc85cd1aae61e02b820cb25733dfb0680410107
Original-Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313003
Original-Commit-Ready: Freddy Paul <freddy.paul@intel.com>
Original-Tested-by: Freddy Paul <freddy.paul@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12592
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03 14:17:39 +01:00
Brandon Breitenstein e1aceef955 intel/kunimitsu: FAB 4 update for Rcomp Target table
Changed index 3 to be an exception of the default Rcomp Value

BUG=None
BRANCH=None
TEST=Tested on FAB 4 SKU 1

Change-Id: I154c254835c4f6995183840cc241feeb9a448cdb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f08eba3cf623b5869a7bb03fb3b6ba084cdd1622
Original-Change-Id: I0fbcff2c3526c4ed7cf90088ca23b43774cb9f8f
Original-Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/312715
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Freddy Paul <freddy.paul@intel.com>
Reviewed-on: https://review.coreboot.org/12591
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03 14:17:34 +01:00
Brandon Breitenstein ad77bf9320 intel/Kunimitsu: FAB 4 SPD changes
Updated Memory IDs and SKU IDs for FAB 4
Updated detection of single/dual channel memory to use SPD Index (Memory ID)
Added spd files for new dimms
Removed boardid.h as it is no longer needed

BUG=None
BRANCH=None
TEST=Tested on FAB4 SKU1 and SKU3

Change-Id: I60403c0e636ea28797d94cff9431af921631323e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ce39dc3b0b9448635f878ce8c1aea5b4743594c4
Original-Change-Id: I870b3dfa2c4f358defb9263e759de477bb32e620
Original-Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/312546
Original-Commit-Ready: Freddy Paul <freddy.paul@intel.com>
Original-Tested-by: Freddy Paul <freddy.paul@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/12590
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03 14:17:30 +01:00
henryc.chen fb622cc471 mediatek/mt8173: Add PMIC wrapper driver
BUG=none
TEST=emerge-oak coreboot
BRANCH=none

Change-Id: Id1e9244e33e34c2c30d7c87cc277ecb7524dfb09
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b21abfdaac4eeb2b65d4c0269ca0b9beff4b5e2f
Original-Change-Id: I84de32de3a09e7857b0695759b49d4db5fde87ec
Original-Signed-off-by: henryc.chen <henryc.chen@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292668
Original-Commit-Ready: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12589
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03 14:17:17 +01:00
James Liao f9fad12875 mediatek/mt8173: Add PLL driver
Add PLL init code.

BRANCH=none
BUG=none
TEST=none

Change-Id: I2dcea8cdea1a3812bd8b84b7e8d961e7f8d4d953
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e6e2eecb2fad30db018685b61912103f5e2cd524
Original-Change-Id: Id67d8033f3b2a267a140d7d73daa5727bc032272
Original-Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292670
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12588
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03 14:17:12 +01:00
Yidi Lin 3d7b6069e1 mediatek/mt8173: Add a stub implementation of the MT8173 SoC
BUG=chrome-os-partner:36682
TEST=emerge-oak coreboot
BRANCH=none

Change-Id: I748752d5abca813a0469d3a76e4d40fcbeb9b959
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ece2f412d94f071a6f5f1dbed4dfaea504da9e1a
Original-Change-Id: I1dd5567a10d20840313703cfcd328bec591b4941
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292558
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12587
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03 14:17:08 +01:00
Mary Ruthven f82e8ab697 cbfs_spi: enable CBFS access in early romstage
Currently the CBFS mmap cannot be accessed at the beginning of romstage
because it waits until DRAM is initialized. This change first loads CBFS
into SRAM and then switches to using DRAM as the backing once it is
initialized.

BUG=chromium:210230
BRANCH=none
TEST=confirm that the cbfs can be access at the beginning and end of
romstage on different boards.

Change-Id: I9fdaef392349c27ba1c19d4cd07e8ee0ac92dddc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ccaaba266386c7d5cc62de63bdca81a0cc7c4d83
Original-Change-Id: Idabfab99765b52069755e1d1aa61bbee39501796
Original-Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/312577
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12586
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03 14:17:04 +01:00
Jimmy Huang 857829654c arch/arm64: introduce mmu to bootblock and romstage
We need mmu interfaces in these two stages for,
1. bootblock: to support mmu initialization in bootblock
2. romstage: to be able to add dram range to mmu table

BRANCH=none
BUG=none
TEST=build pass

Change-Id: I56dea5f958a48b875579f546ba17a5dd6eaf159c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cf72736bda2233f8e0bdd7a8ca3245f1d941ee86
Original-Change-Id: I1e27c0a0a878f7bc0ff8712bee640ec3fd8dbb8b
Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292665
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12585
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-12-03 14:16:55 +01:00
Jimmy Huang 9b423a77d1 arch/arm64: add DMA_COHERENT region macros to memlayout
BRANCH=none
BUG=none
TEST=build pass

Change-Id: Ia997ce97ad42234ab020af7bd007d57d7191ee86
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 604ac738e33fdfbaf093989ea13162c8506b9360
Original-Change-Id: I636a1a38d0f5af97926d4446f3edb91a359cce4c
Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292551
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12584
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03 14:16:43 +01:00
Stefan Reinauer cbce4de976 drivers/intel/fsp1_1: Don't hide build related options behind HAVE_FSP_BIN
The right thing to do is to hide them behind PLATFORM_USES_FSP1_1.
The only things that should depend on HAVE_FSP_BIN is the code
that actually adds the file to CBFS, and the path to the file in Kconfig.

Removing the HAVE_FSP_BIN check requires some default values
for two Kconfig variables.

Change-Id: I9b6c3ed0cdfb0e02421d7b98c488a66e39add947
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/12465
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-02 18:42:05 +01:00
Patrick Georgi 1cab0125cc build system: Add more files through cbfs-files instead of manual rules
verstage, romstage, and payload can be added through infrastructure now.

Change-Id: Ib9e612ae35fb8c0230175f5b8bca1b129f366f4b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/12549
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02 17:30:36 +01:00
Martin Roth c7b26c381c lippert/frontronner-af & toucan-af: Fix IASL warnings
Not all the paths through the _OSC method returned a value.  According
to the ACPI spec (5.0 & 6.0), bit 2 needs to be set for an unrecognized
GUID.

Fixes warnings for both platforms:
dsdt.aml 1143:  Method(_OSC,4)
Warning  3115 -          ^ Not all control paths return a value (_OSC)
dsdt.aml 1143:  Method(_OSC,4)
Warning  3107 -          ^ Reserved method must return a value
(Buffer required for _OSC)

Change-Id: Ibaf27c5244b1242b4fc1de474c371f54f930dcb6
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12530
Tested-by: build bot (Jenkins)
Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02 16:10:06 +01:00
Damien Zammit 74d165b18d mainboard/intel/d510mo: Add Intel D510MO mainboard
Board uses Pineview native raminit
Board boots from grub to linux kernel

VGA needs work, currently headless machine

Change-Id: I8e459c6d40e0711fac8fb8cfbf31d9cb2aaab3aa
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/10074
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02 00:39:03 +01:00
Damien Zammit 149c4c5d01 x86/smm: Initialize SMM on some CPUs one-by-one
We currently race in SMM init on Atom 230 (and potentially
other CPUs). At least on the 230, this leads to a hang on
RSM, likely because both hyperthreads mess around with
SMBASE and other SMM state variables in parallel without
coordination. The same behaviour occurs with Atom D5xx.

Change it so first APs are spun up and sent to sleep, then
BSP initializes SMM, then every CPU, one after another.

Only do this when SERIALIZE_SMM_INITIALIZATION is set.
Set the flag for Atom CPUs.

Change-Id: I1ae864e37546298ea222e81349c27cf774ed251f
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/6311
Tested-by: build bot (Jenkins)
Tested-by: BSI firmware lab <coreboot-labor@bsi.bund.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-12-02 00:38:45 +01:00
Damien Zammit 003d15cab4 northbridge/intel/pineview: Add native raminit
Does native ram init for Intel Atom D5xx 8086:a000 northbridge

Tested on Intel D510MO mainboard, board boots linux kernel

- Works fully with both dimms populated (2x2GB), memtest passes 100%
- Almost boots with only one dimm in one of the slots
  (suspect bad memory map with one dimm?)
- Reads garbage with only one dimm in other slot

Change-Id: Ibd22be2a959045e0a83aae2a3a0e877013f80711
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/12501
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-02 00:26:45 +01:00
Damien Zammit f7060f1d0f northbridge/intel/pineview: Add remaining boilerplate code for northbridge
This patch does *not* include native raminit

Change-Id: I3fb8146ef7fe2ad27c167ecd2fb0fd629f051cc1
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/12430
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-12-02 00:26:36 +01:00
Timothy Pearson 1a38374535 southbridge/amd/sb700: Fix boot hang when AHCI mode disabled
Existence of requested PCI device was not checked when enabling
IDE mode on the SP5100.  Fix incorrect PCI device ID and check
for device existence before attempting setup.

Change-Id: I726c355571b5c67c9a13995be2352601c03ab1e4
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12572
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-01 16:59:41 +01:00
Timothy Pearson 273384638b cpu/amd/fam10h-15h: Enable DFE on Family 15h HT3 links
Decision Feedback Equalization (DFE) is a form of dynamic
link training used to lower the overall error rate within
the coherent fabric.  Enable it on all capable HT links.

Change-Id: I5e719984ddd723f9e375ff1a9d4fa1ef042cf3eb
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12072
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-12-01 16:59:01 +01:00
Timothy Pearson f8549e88e2 cpu/amd/fam10h-15h: Fix link type detection and XCS buffer count setup
The existing code did not properly detect various link attributes
on Family 10h/15h processors.  With the addition of new HT3- and
IOMMU-specific code, proper detection has become critical to avoid
system deadlocks.

Fix and streamline link attribute detection.

Change-Id: If63dd97f070df4aab25a1e1a34df4b1112fff4b1
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12071
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-01 16:58:25 +01:00
Timothy Pearson 09830faa8d nb/amd/amdht: Fix XCS buffer count setup on AMD Family 15h CPUs
The existing code re-used the Family 10h XCS buffer setup on
Family 15h CPUs, which set incorrect values leading to random
system lockups.

Use the Family 15h XCS buffer setup shown in the BKDG.

Change-Id: Ie4bc8b3ea6b110bc507beda025de53d828118f55
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12070
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-01 16:56:31 +01:00
Timothy Pearson 346fcb2894 cpu/amd/fam10h-15h: Force iolink detect to either 1 or 0
Minor change to be more explicit about the binary state
of the iolink detect variable.

Change-Id: Ifd8f5f1ab28588d100e9e4b1fb0ec2525ad2f552
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12069
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-12-01 16:33:03 +01:00
Timothy Pearson 93107bebf6 nb/amd/amdfam10: Fix incorrect channel buffer count configuration
The secondary bus number set code incorrectly overwrote the link
buffer settings in F0x[F4,D4,B4,94].  Constrain the secondary
bus number set to the appropriate bits of the registers.

Change-Id: If70825449f298aa66f7f8b76dbd7367455a6deb1
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12068
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-01 16:32:25 +01:00
Timothy Pearson f1436e58d2 mainboard/asus/kgpe-d16: Enable GART by default
Change-Id: I73eb2425bbdb7e329a544d55461877d1dee0d05b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12067
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-01 16:31:47 +01:00
Timothy Pearson 5edc6695f8 nb/amd/mct_ddr3: Add Family 15h tristate enable codes
The Family 15h DRAM initialization did not set up the various
tristate enable codes in the MCT.

Add Family 15h tristate enable setup.  This fixes multiple
DIMMs on a single channel.

Change-Id: I0278656e98461882d0a64519dfde54a6cf28ab0f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12060
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-12-01 16:31:02 +01:00
Martin Roth d45a3477b7 amd/pi/00630F01: Drop HT3_SUPPORT
The Kconfig symbol CONFIG_HT3_SUPPORT is not implemented.

This mirrors commit c5163ed8 (AMD binaryPI: Drop HT3_SUPPORT)

Change-Id: I2682d3b620e2cee613c7421622a8c79db5ba3a86
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12556
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-12-01 16:28:07 +01:00
Patrick Georgi 6dc8570719 build system: strip quotes from CONFIG_CBFS_PREFIX in a single location
Instead of having to remember to strip the quotes everywhere so that
string comparisons (of which there are a few) match up, do it right at
the beginning.

Fixes building the image with a .config where CONFIG_CBFS_PREFIX
contains quotes.

Change-Id: I4d63341cd9f0bc5e313883ef7b5ca6486190c124
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/12578
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-12-01 09:05:07 +01:00
Martin Roth bd88fa0ef6 fsp_baytrail: Remove use of BAYTRAIL_SMM Kconfig symbol
The symbol BAYTRAIL_SMM was never valid (there's no config statment
initializing the symbol), but it was being selected and used
in the code.

Now that SMM is supported in fsp_baytrail, the code it was trying
to switch can be removed, and just set up for SMM.

Change-Id: I0fd4865a951734e728500e7baf593ff7eb556f73
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12553
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Ben Gardner <gardner.ben@gmail.com>
2015-11-30 23:52:51 +01:00
Timothy Pearson 309303884c nb/amd/amdmct/mct_ddr3: Use StopOnError to decrease training time
There is no need to continue testing a DCT configuration after
data errors have already been detected; this just wastes time
during boot.

Change-Id: I979e27c32a3e0b101590fba0de3d7a25d6fc44d2
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12066
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-30 19:39:31 +01:00
Marcin Wojciechowski 9586dc72db mainboard/intel: Add Little Plains
This adds a new mainboard: Little Plains for Intel's atom c2000
It was based on Mohon Peak board with some minor changes
This board is not available as standalone product
It is a managment board for
Intel Ethernet Multi-host Controller FM10000 Series
The FSP package is available from Intel: https://www.intel.com/fsp

Change-Id: I28127a858106ed35d26e235f0c6393c20ed14350
Signed-off-by: Marcin Wojciechowski <marcin.wojciechowski@intel.com>
Reviewed-on: https://review.coreboot.org/12503
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-30 18:00:50 +01:00
Timothy Pearson b4b298c449 mainboard/asus/kgpe-d16: Limit HT speed to 2.6GHz
The CPU <--> CPU HT wiring on this board has only been validated
to 2.6GHz.  While higher frequencies appear to function initially,
and in fact function when only one CPU package is installed, dual
CPU package systems will lock up after around 6 - 12 hours of uptime
due to presumed HT link errors at the higher (>= 2.8GHz) HT clocks.

If applications are not being used that stress the coherent fabric,
then the uptime before hang may be much longer.  Users attempting
to overclock the HT links are advised to "burn in test" the HT links
by running memtester locked to a node with no local memory installed.

Change-Id: I8fae90c67aa0e8b103e9b8906dea50d1e92ea5a9
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12064
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-30 05:29:47 +01:00
Timothy Pearson 16a3a7515a cpu/amd/family_10h-family_15h: Apply missing Family 15h errata fixes
Change-Id: I132874fe5b5a8b9a87422e2f07bff03bc5863ca4
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12065
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins)
2015-11-30 05:21:24 +01:00
Timothy Pearson 01b9f8e4c2 nb/amd/mct_ddr3: Use antiphase to better center DQS window
The BKDG recommends the use of an antiphase window detection
algorithm to ensure that the DQS data eye is properly centered.

TEST: Booted both with DIMMs known to move the data eye into the
prior clock phase and DIMMs known to keep the data eye in the
current clock phase.

Change-Id: I1d85fddd45197ca82dcaa46fe863e64589712d1f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12059
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-30 05:19:19 +01:00
Martin Roth 323c7db204 bachmann/ot200: Remove DRIVERS_I2C_IDREG Kconfig symbol
As far as I can tell the Kconfig symbol DRIVERS_I2C_IDREG never actually
existed in the coreboot codebase.  I didn't see anything that it might
have been a typo of.

Change-Id: Ib17de670e38e07ab4a4745143c42fa85da1754e1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12563
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2015-11-30 00:35:38 +01:00
Timothy Pearson 4502df12aa nb/amd/mct_ddr3: Fix odd rank data corruption
The odd rank of each DIMM could experience data corruption due to
incorrect DQS training.  Fix the DQS training algorithm by executing
the relevant portions of the training algorithm on the odd ranks.

Change-Id: Ibc51f5052d5189e45b3d9aa98ca8febbfe13f178
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12058
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-29 19:38:13 +01:00
Timothy Pearson df499b53c3 nb/amd/amdmct/mct_ddr3: Fix a minor RDIMM CS select error
Change-Id: I4cdfeec887813c17edcdee8858222414fb19b72c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12057
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-29 19:37:08 +01:00
Timothy Pearson 0eb163d5d3 nb/amd/amdmct/mct_ddr3: Ensure channel clock skew is properly set
Also fix incorrect Trfc[0-3] value on Family 15h.

Change-Id: Iafc233984ae1d44fe6a1cb5b109d36397cbd991a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12055
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-29 19:36:34 +01:00
Patrick Georgi 2ca8b31ff5 x86/smm: don't hide harmless declarations
Hiding them requires #if CONFIG_HAVE_SMI_HANDLER instead of
if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER))

Change-Id: Ib874cd98e195ad7437d05be1696004b29bf97a66
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: https://review.coreboot.org/12565
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-29 13:06:04 +01:00
Timothy Pearson 8528e39fba nb/amd/amdfam10: Work around sporadic lockups when CC6 enabled
The silicon in control of CC6 appears to contain minor bugs
and / or deviations from the BKDG; through trial and error
it was found that these issues can be worked around by reserving
the entire possible CC6 save region, regardless of currently
installed node count.

Change-Id: If31140651f25f9c524a824b2da552ce3690eae18
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12054
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-28 19:21:18 +01:00
Alexander Couzens 316170e22c baytrail: fix missing brackets around ir_base to fix IRQ routing
The missing brackets caused other registers, including the IO APIC
enable bit (EAN in OIC) to be overwritten. Bug introduced by
bde6d309 (x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer)

Change-Id: I1d5aa2af6d74405a1a125af6221ac0e635a6b693
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/12525
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-28 19:17:05 +01:00
Martin Roth 3bb9405494 ibase/mb899: Fix IASL warning and remark
- Add an empty Operating Region for the empty _REG method
- Move Named objects out of _CRS Method
- Remove Kconfig default disabling IASL warnings as errors

Fixes these items:
dsdt.aml 1449:  Method (_CRS, 0)
Remark   2120 -           ^ Control Method should be made Serialized
(due to creation of named objects within)
dsdt.aml 1458: Method (_REG, 2)
Warning  3079 -          ^ _REG has no corresponding Operation Region

Change-Id: I801a84468097687c91d6ee3f44cec06243355fac
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12531
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-27 18:10:36 +01:00
Martin Roth dde96fb2f1 soc/intel/common: Fix whitespace in Kconfig
Change leading spaces to tabs.

Change-Id: Ief138f5f68198578ba9dddb8fbdabbd9a0185a21
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12546
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-27 18:07:29 +01:00
Martin Roth 232df8b2d2 kontron/986lcd-m: Fix IASL warning and remark
- Add an empty Operating Region for the empty _REG method
- Serialize _CRS Method
- Remove Kconfig default disabling IASL warnings as errors

Fixes IASL Warning and remark:
dsdt.aml   1451:  Method (_CRS, 0)
Remark   2120 -             ^ Control Method should be made Serialized
(due to creation of named objects within)
dsdt.aml   1460:  Method (_REG, 2)
Warning  3079 -             ^ _REG has no corresponding Operation Region

Change-Id: I4aa59468a89c4013146ab34004476a0968c60707
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12521
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2015-11-27 18:07:09 +01:00
Jonathan A. Kollasch 20d9fb4692 amd/car: don't apply Fam10h/Fam12h Errata 343 fix to Fam0Fh
Fixes early fault problem on Fam0Fh introduced in
Change I8e01a4ab68b463efe02c27f589e0b4b719532eb5,
commit 991f18475c.

Change-Id: Id215d2822b78917939c28f7a922a94e02e5d15bf
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: https://review.coreboot.org/12528
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-11-26 23:17:08 +01:00
Timothy Pearson 905507c379 southbridge/amd/sb700: Fix drifting system clock
Change-Id: I1698c9b9b1840d254115821f3c0e76b7211e9056
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12052
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-26 10:46:04 +01:00
Timothy Pearson 56c8ef9a91 southbridge/amd/sr5650: Use correct PCI configuration block offset
Change-Id: I4277d1788d8f9a501399218544aa6d4d11349ccc
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12049
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-11-26 01:09:16 +01:00
Timothy Pearson 259549678b mainboard/asus/kgpe-d16: Add missing IOMMU setup
Change-Id: I9a00bdbcd47804b6d83c0231cd515773d02ff951
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12527
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-26 01:08:25 +01:00
Timothy Pearson eda407f4eb mainboard/asus/kgpe-d16: Add IOMMU nvram configuration option
Change-Id: I45b04e8fbdfc65603e1057f7b0e5a13d073fe348
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12048
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-26 01:07:59 +01:00
Martin Roth 601ea3d40e lenovo t400: Fix IASL warning and remark
If any path in a method returns a value, IASL expects that all paths
within that method will return a value.

Presumably, the ATPX would not need a return value if Arg0 is anything
other than 0, so just return a zero.

- Serialize ATPX method to make IASL happy.  This means that it can
only be used by one thread at a time.

Fixes these issues:
dsdt.aml   2581: Method (ATPX, 2, NotSerialized) {
Remark   2120 -            ^ Control Method should be made Serialized
(due to creation of named objects within)
dsdt.aml 2581: Method (ATPX, 2, NotSerialized) {
Warning  3115 -          ^ Not all control paths return a value (ATPX)

Change-Id: I14aeab0cebe4596e06a17cffc36cc01b953d7191
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12518
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-24 22:42:57 +01:00
Martin Roth c5fb1a2ea8 google/rambi: Fix IASL warnings _CRS must return a value
The Touchpad and Touchscreen _CRS methods do not return an interrupt
value if the I2c busses that the devices are on are not in PCI mode.

Previously they didn't return any value if they weren't in PCI mode.
This patch has them return an empty resource template.

Fixes these warnings:
dsdt.aml 2813: Method (_CRS)
Warning  3115 -          ^ Not all control paths return a value (_CRS)
dsdt.aml 2813: Method (_CRS)
Warning  3107 -          ^ Reserved method must return a value
(Buffer required for _CRS)

dsdt.aml 2832: Method (_CRS)
Warning  3115 -          ^ Not all control paths return a value (_CRS)
dsdt.aml 2832: Method (_CRS)
Warning  3107 -          ^ Reserved method must return a value
(Buffer required for _CRS)

Change-Id: I02a29e56a513ec34a98534fb4a8d51df3b70a522
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12519
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-24 22:41:57 +01:00
Martin Roth 8b954f5790 ec/quanta/ene_kb3940q: Fix ACPI Notice
Affects these mainboards:
- lenovo/g505s
- google/parrot
- hp/pavilion_m6_1035dx

Fixes IASL notice for this specific instance:
dsdt.aml   1952:  Method (_CRS, 0, NotSerialized)
Remark   2120 -             ^ Control Method should be made Serialized
(due to creation of named objects within)

Change-Id: Id297cdea35d43f51887f798a9983629343c2313a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12513
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-24 22:40:12 +01:00
Martin Roth d26c9d603e iwave/IWRainBowG6: Fix IASL warning and remark
- Add an empty Operating Region for the empty _REG method
- Serialize _CRS Method
- Remove Kconfig default disabling IASL warnings as errors

Fixes IASL Warning:
dsdt.aml   1362:  Method (_REG, 2)
Warning  3079 -             ^ _REG has no corresponding Operation Region

Fixes IASL remark:
dsdt.aml   1353:  Method (_CRS, 0)
Remark   2120 -             ^ Control Method should be made Serialized
(due to creation of named objects within)

Change-Id: Iff01613a6e3238469c1fcb8d74f5e98d18420aaf
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12515
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-24 22:38:24 +01:00
Martin Roth 6149233cce intel/soc/baytrail: Move MCRS ResourceTemplate out of _CRS method
Fixes these remarks:
Object is not referenced (Name is within method [_CRS])

The ACPI compiler is trying to be helpful in letting us know
that we're not using various fields in the MCRS ResourceTemplate
when we define it inside of the _CRS method.  Since we're not
intending to use those objects in the method, it shouldn't be an
issue, but the warning is annoying and can mask real issues.
Moving the creation of the MCRS object to outside of the CRS
method and referencing it from there solves this problem.

Change-Id: I54ab3ad9ed148fdd24e8615d83bc8ae668d1dbff
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12514
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-24 22:37:40 +01:00
Martin Roth 21dbc2fc3c ec/lenovo/h8: Fix IASL warnings
If any path in a method returns a value, IASL expects that all paths
within that method will return a value.

Presumably the MKHP method wouldn't get called unless there were a
pending event, but if no event is found, return a zero.

Fixes IASL warning:
dsdt.aml 1785: Method (MHKP, 0, NotSerialized)
Warning 3115 -           ^ Not all control paths return a value (MHKP)

This was the only IASL warning in most lenovo mainboards.

Change-Id: Id93dcc4a74bd4c18b78f1dde821e7ba0f3444da3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12517
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-24 22:34:34 +01:00
Martin Roth 56033a9f2d superio/smsc/mec1308: Fix IASL warnings
The SIO device needs to provide an _ADR object with the IO
address as well as the address in the OperationRegion.

ACPI provides two different Resource Descriptor Macros to describe the
I/O areas required for a device.  The FixedIO macro is only valid for
10-bit IO addresses.  Use the IO macro instead.

Thank you to recent IASL that allows for addition in the ASL file.  :)

Fixes these warnings:
dsdt.aml   2276: Device (SIO) {
Warning  3141 -           ^ Missing dependency
(Device object requires a _HID or _ADR in same scope)
dsdt.aml   2390:    FixedIO (0xa00, 0x34)
Warning  3060 -                 ^ Maximum 10-bit ISA address (0x3FF)
dsdt.aml   2394:    FixedIO (0xa00, 0x34)
Warning  3060 -                 ^ Maximum 10-bit ISA address (0x3FF)

Lumpy now compiles its ASL tables with no warnings.  Re-enable
Warnings as errors.

Change-Id: Id26e234eadaa3b966e8f769cb9f9fb7ea64fc9e3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12520
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-24 22:30:19 +01:00
Ben Gardner e597e63e49 FSP 1.0: Fix CAR issues - broken timestamps and console
FSP 1.0 has a fixed-size temporary cache size and address and the entire
cache is migrated in the FSP FspInitEntry() function.

Previous code expected the symbol _car_data_start to be the same as
CONFIG_DCACHE_RAM_BASE and _car_data_end to be the same as
_preram_cbmem_console.

FSP 1.0 is the only one that migrates _preram_cbmem_console.
Others leave that where it is and extract the early console data in
cbmemc_reinit(). Special handling is needed to handle that.

Commit dd6fa93d broke both assumptions and so broke the timestamp table
and console.

The fix is to use CONFIG_DCACHE_RAM_BASE when calculating the offset and
to use _preram_cbmem_console instead of _car_data_end for the console
check.

Change-Id: I6db109269b3537f7cb1300357c483ff2a745ffa7
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: http://review.coreboot.org/12511
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-24 21:21:43 +01:00
Martin Roth b9434aa853 intel/d945gclf: Fix IASL warning and remark
- Add an empty Operating Region for the empty _REG method
- Serialize _CRS Method
- Remove Kconfig default disabling IASL warnings as errors

dsdt.aml   1445:  Method (_CRS, 0)
Remark   2120 -             ^ Control Method should be made Serialized
(due to creation of named objects within)
dsdt.aml   1454:  Method (_REG, 2)
Warning  3079 -             ^ _REG has no corresponding Operation Region

Change-Id: I2b64609c929af62c2b699762206e5baf58fbdb8b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12523
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-24 21:05:45 +01:00
Ben Gardner f5fd4c99d5 lib/timestamp.c: only log "Timestamp table full" once
If the timestamp table gets corrupted (separate issue), the
timestamp_sync_cache_to_cbmem() function may add a large number of bogus
timestamp entries.

This causes a flood of "ERROR: Timestamp table full".  With logs going
to a serial console, this renders the system essentially unbootable.

There really isn't a need to log that more than once, so log it when the
last slot in the timestamp table is filled.

Change-Id: I05d131183afceca31f4dac91c5edc95cfb1e443f
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: http://review.coreboot.org/12506
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-24 21:01:25 +01:00
Nico Huber 1ef80141c0 soc/intel/braswell: Drop gfx_read_resources()
Drop the last remnant of vanished CONFIG_MARK_GRAPHICS_MEM_WRCOMB.

Could not build test google/cyan and intel/strago due to lack of UEFI
headers, OMG.

Change-Id: I0b9eac5c040d24bab2b85e9b63042b6aaa9879d9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/12338
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-24 20:59:18 +01:00
Zheng Bao 2286138561 AMD/bettong: Add UART support
The function delay in uart8250mem.c is not enough for hudson. I guess
there are some problems in lapic_timer(). I uploaded a patch to gerrit
to show the way to enable UART feature.
http://review.coreboot.org/#/c/12343/4

Currently the HUDSON_UART is unchecked by default. Select HUDSON_UART to
enable this feature.

The UART is test at BIOS stage.

Since it is not a standart UART device, the windows internal UART driver
doesnt support it. I guess we need a driver to use it on windows.

Change-Id: I4cec833cc2ff8069c82886837f7cbd4483ff11bb
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11749
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-24 20:57:47 +01:00
Timothy Pearson ab1e77fb01 northbridge/amd/amdmct/mct_ddr3: Add CC6 setup information messages
Change-Id: I17660ce5429431e08476b7bba15e381636b64c7d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12053
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2015-11-24 19:50:11 +01:00
Timothy Pearson c8e1073359 northbridge/amd/amdmct/mct_ddr3: Add DDR3 termination debug output
Change-Id: Iabd2e3e20b0e9719080f6bd7be2032c1749994dc
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12056
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-24 19:48:43 +01:00
Timothy Pearson 84216dca3a southbridge/amd/sb700: Fix mismatched FADT entries
Change-Id: Ifa0b61678fe362481891fc015cebe08485b66fc1
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12051
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-24 19:47:12 +01:00
Timothy Pearson ce3456dacd nb/amd/amdfam10: Fix gart setup not working on Fam15h processors
Change-Id: Ib78620c30502df6add9cc2ea1dbd4fb6dc89203e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12047
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-11-24 19:28:51 +01:00
Timothy Pearson 50001b80f5 northbridge/amd/amdht: Add isochronous setup support
The coherent fabric on all Family 10h/15h devices supports
isochronous mode, which is required for IOMMU operation.

Add initial support for isochronous operation.

Change-Id: Idd7c9b94a65f856b0059e1d45f8719d9475771b6
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12042
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-24 19:28:00 +01:00
Timothy Pearson 68130f506d amd/amdfam10: Control Fam15h cache partitioning via nvram
Add options to control cache partitioning and overall memory
performance via nvram.

Change-Id: I3dd5d7f3640aee0395a68645c0242307605d3ce7
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12041
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-24 19:27:43 +01:00
Timothy Pearson b174667534 northbridge/amd/amdfam10: Rename mislabeled iommu nvram option to gart
Change-Id: Ia24102e164eb5753ade3f9b5ab21eba2fa60836b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12046
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-24 19:03:24 +01:00
Stefan Reinauer 593f5c8a48 Unify OBJCOPY arguments throughout various x86 stages
Instead of having to have an ifeq() all across the code base,
use $(target-objcopy). And correct target-objcopy to a value
that objcopy actually understands.

Change-Id: Id5dea6420bee02a044dc488b5086d109e806d605
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11090
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-24 14:48:22 +01:00
Damien Zammit 62477931c8 northbridge/intel/pineview: Add minimal Pineview northbridge
Based on i945.  Tested on Intel D510MO mainboard,
board boots to UART console with this code.

Change-Id: I1d92a1aa6d6d767bda8379807dc26b50b9de75c9
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/10073
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-24 14:40:44 +01:00
Damien Zammit 0cf0805e92 cpu/intel/socket_FCBGA559: Add new socket for Atom D5xx
Tested on Intel D510MO board, boots to UART console.

Change-Id: I82a630c9836c099d0fcc62e019c20f328a75151d
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/10066
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-11-24 14:39:42 +01:00
Damien Zammit ef33e035e7 southbridge/intel: Use i82801gx code for NM10
It works as an ICH7 on Intel D510MO mainboard

Change-Id: Ib8c76c001dffee8f93e3d6aa3156d4413b2e842a
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/12431
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-24 14:38:51 +01:00
Timothy Pearson a8c6c7f30c southbridge/amd/sr5650: Hide clock configuration device after setup is complete
Change-Id: I043f2eb0993660d0a9351867eca1e73e0b2c37f1
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12045
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-11-23 23:03:34 +01:00
Timothy Pearson 44e4a4e4db southbridge/amd/sr5650: Add IOMMU support
Change-Id: I2083d0c5653515c27d4626c62a6499b850f7547b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12044
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-23 23:02:16 +01:00
Timothy Pearson ff8ccf05b0 arch/x86/acpi: Add IVRS table generation routines
Change-Id: Ia5d97d01dc9ddc45f81d998d126d592a915b4a75
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12043
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-23 23:00:30 +01:00
Timothy Pearson a52d5d1269 cpu/amd/fam15h: Set up Link Base Channel Buffer Count registers
Change-Id: I8d616a64a5a9cf0b51288535f5050c6866d0996b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12038
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins)
2015-11-23 22:58:19 +01:00
Timothy Pearson 5a0375a2f6 northbridge/amd/amdfam10: Add Family 15h cache partitioning support
Certain workloads may evict too many lines of other cores from the
L3 cache if configured as one monolithic shared cache region.

Forcibly partition L3 cache to improve performance.

Change-Id: Ie4e28dd886aaa1c586b0919c5fe87ef1696f47e9
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12036
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-23 22:55:28 +01:00
Timothy Pearson 121ef60666 northbridge/amd/amdfam10: Fix invalid NUMA table
The existing code generated an invalid NUMA table
that was rejected by Linux, leading to poor resource
allocation.  This was due to system MMIO resources
being inserted into the table when the table should
only contain DRAM resources.

Do not include system MMIO resources (i.e. resources
with an index less than 0x10) in the NUMA table.

Change-Id: I99c200382b52a99687daf266a84873d9ae2df025
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12035
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-11-23 22:54:19 +01:00
Ben Gardner acd47aeaa3 commonlib/cbmem_id.h: Add CBMEM_ID_HOB_POINTER to CBMEM_ID_TO_NAME_TABLE
fsp-based platforms have this ID, so give it a name.

Change-Id: Idce4dbb60b7b3581e18046e66183a7c91b17abd7
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: http://review.coreboot.org/12485
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-23 21:10:28 +01:00
Martin Roth c5bb7bd957 fsp1_0: Update Kconfig for symbols not depending on FSP binary
There were several symbols that were inside the 'if HAVE_FSP_BIN' that
don't really depend on having the FSP binary.  In theory, we should be
able to build a coreboot rom and add the FSP binary later.  This doesn't
always work in practice, but this is a step in that direction.

This also fixes a Kconfig warning for Rangeley.

Change-Id: I327d8fe5231d7de25f2a74b8a193deb47e4c5ee1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12461
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-23 18:49:54 +01:00
Martin Roth 40d073c3c5 google/rambi: Fix end comment in Kconfig
Change-Id: I3963d145f6d209e32256268259e93103c62809c5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12504
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2015-11-23 18:49:22 +01:00
Martin Roth 77c67b3d30 IASL: Enable warnings as errors
We've actually got more warnings now than when I first tested IASL
warnings as errors.  Because of this, I'm adding it with the option
to have it disabled, in hopes that things won't get any worse as we
work on fixing the IASL warnings that are currently in the codebase.

- Enable IASL warnings as errors
- Disable warnings as errors in mainboards that currently have warnings.
- Print a really obnoxious message on those platforms when they build.
***** WARNING: IASL warnings as errors is disabled!  *****
*****          Please fix the ASL for this platform. *****

Change-Id: If0da0ac709bd8c0e8e2dbd3a498fe6ecb5500a81
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10663
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-23 18:48:58 +01:00
Timothy Pearson 845b00ce33 amd/amdmct/mct_ddr3: Fix poor performance on Family 15h CPUs
Change-Id: Ib6bc197e43e40ba2b923b1eb1229bacafc8be360
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12029
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-23 18:36:44 +01:00
Stefan Reinauer 7e1465431a drivers/intel/fsp1_1: Don't include files from blobs / fsp directory
coreboot's binary policy forbids to store include files required to build
the host binaries in the blobs directory. Hence remove the infrastructure
to do so.

Change-Id: I66d57f84cbc392bbfc1f951d13424742d2cff978
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12464
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-23 17:17:49 +01:00
Stefan Reinauer 31fbb712fe drivers/intel/fsp1_1: Include rules.h in util.h
util.h uses ENV_* and hence needs to have rules.h

This is required for successful compilation of strago.

Change-Id: I0df35e90e2010aac43ef0a4d900f20c842d3bcb5
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12495
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-23 17:17:14 +01:00
Stefan Reinauer 991f18475c cpu/amd: de-duplicate MSR include files
Change-Id: I8e01a4ab68b463efe02c27f589e0b4b719532eb5
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12510
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-11-23 17:16:45 +01:00
Timothy Pearson baa1acde7b cpu/amd/fam10h15h: Set up SRI to XCS Token Count registers on Family 15h
Change-Id: Ic992efad11d8e231ec85c793cf1e478bea0b9d3e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12040
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-11-22 23:10:53 +01:00
Timothy Pearson aab3ad256a cpu/amd/family_10h-family_15h: Set up cache controls on Family 15h to improve performance
Change-Id: I3df571d8091c07ac1ee29bf16b5a68585fa9eed4
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12039
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-11-22 23:10:38 +01:00
Timothy Pearson 0d2fdeb36a amd/amdmct/mct_ddr3: Set prefetch double stride to improve performance
Change-Id: I34ad85388c6b71f0d44bee13afd663e0b84545cd
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12037
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-11-22 23:10:12 +01:00
Timothy Pearson eb295a3e69 nb/amd/amdmct/mct_ddr3: Force DRAM retraining on every boot
Stability issues have arisen on multiple Family 15h systems
when configuration restoration is enabled.  In all cases these
stability issues resolved by allowing the RAM to go through a
full training cycle.

Change-Id: I017e0dd5120110124d5b5d5276befef6f7740614
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12034
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-11-22 23:09:35 +01:00
Timothy Pearson 71b8f01b62 cpu/amd/family_10h-family_15h: Set up link XCS token counts on Family 15h
Change-Id: I4cf6549234041c395a18a89332d95f20a596fc3e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12033
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-11-22 23:09:23 +01:00
Timothy Pearson 99f80422f6 cpu/amd/family_10h-family_15h: Configure NB register 2
Change-Id: I55cfc96a197514212b2a4c344d3513396ebc2ad4
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12032
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-11-22 23:09:12 +01:00
Timothy Pearson 4dc6cabd36 northbridge/amd/amdfam10: Fix poor performance on Family 15h CPUs
Change-Id: I193749bc767b7c1139de7cd67622a7b03298009b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12031
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-11-22 23:09:01 +01:00
Martin Roth 167c03ad4a drivers/ti/tps65913: Set default values in Kconfig
Set default values for the hex and int kconfig symbols so they don't
come up as undefined.

Change-Id: Ib51272f35baa32fe5f3dc369c7f554c77bc2add1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12499
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-11-22 01:40:00 +01:00
Martin Roth ffa4054483 drivers/ams: Set default values in Kconfig
Set default values for the hex and int kconfig symbols so they don't
come up as undefined.

Change-Id: If104cbf7d84719a63fb80aa955efa8baa3953d09
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12498
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-11-22 01:39:44 +01:00
Martin Roth ac76ed9998 console: Add help for serial IO port selection
Add help and a comment about the serial IO port selection to give the
user better feedback when a port index is selected.

Change-Id: I4c1614be51aee0286308fbc5c24554e218120bf7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12487
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-21 03:42:33 +01:00
Ben Gardner b50d8fbb6e hexdump: Fix output if length is not a multiple of 16
hexdump currently rounds up length to a multiple of 16.
So, hexdump(ptr, 12) prints 16 hex digits, including 4 garbage bytes.
That isn't desirable and is easy to fix.

Change-Id: I86415fa9bc6cdc84b111e5e1968e39f570f294d9
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: http://review.coreboot.org/12486
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-11-21 03:41:53 +01:00
Ben Gardner 2d3d1b7eee baytrail: add C0 and D0 stepping decode
The E3800 with ordering code FH8065301487717 is stepping D0, value 0x11.
Add that so the debug log shows 'D0' instead of '??'.

Also, add the C0 stepping decode to fsp_baytrail.

Change-Id: Ibec764fcf5d3f448e38831786a071f5ab6066d67
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: http://review.coreboot.org/12488
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-11-21 03:41:34 +01:00
Paul Menzel 42b6265035 cpu/amd/car/post_cache_as_ram: Avoid trailing spaces
Looking at the coreboot console logs there are sometimes trailing
whitespaces in the output, for example, if writing `Done` was not
possible.

Adapt the code, that spaces are only added when needed.

Change-Id: Ia0af493ab62b6fab24e8a2629cf5fd67329e0af7
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/12357
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-21 03:41:04 +01:00
Martin Roth 4aac08afec chromeos: Fix Kconfig TPM warnings on systems with no LPC TPM
Put dependecies on CHROMEOS's selection of the  Kconfig symbols
TPM_INIT_FAILURE_IS_FATAL and SKIP_TPM_STARTUP_ON_NORMAL_BOOT to match
the dependencies on those symbols where they are defined in
src/drivers/pc80/tpm/Kconfig

The file that uses these only gets built in if CONFIG_LPC_TPM is
selected selected.

The warnings were:
warning: (CHROMEOS) selects TPM_INIT_FAILURE_IS_FATAL which has unmet
direct dependencies (PC80_SYSTEM && LPC_TPM)
warning: (CHROMEOS) selects SKIP_TPM_STARTUP_ON_NORMAL_BOOT which has
unmet direct dependencies (PC80_SYSTEM && LPC_TPM)

Change-Id: I7af00c79050bf511758bf29e3d57f6ff34d2a296
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12497
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-21 03:40:31 +01:00
Timothy Pearson 965704a962 amd/family_10h-family_15h: Fix poor performance on Family 15h CPUs
Change-Id: Ieb1f1fb5653651c98764de79636669802578d5f9
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12028
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-21 00:01:33 +01:00
Timothy Pearson caf0adac4f mainboard/asus/kgpe-d16: Update NB VDD upper voltage limit
Certain older Opteron processors use a higher (+1.2V) northbridge
voltage.  The existing code assumed the use of +1.1V northbridge
voltages and threw an alert when the older Opterons were installed.

Update the permissible NB voltage range to include both the 1.1V
and 1.2V Opteron processors.

Change-Id: I35c90f37d180f59c53d0d2bf3ff0eaf985b26da3
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12507
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-21 00:00:56 +01:00
Timothy Pearson fdf31cb9d9 northbridge/amd/amdht: Add comment for HT Freq write ordering
The BKDG is not correct regarding HT Freq write ordering;
indicate this in a comment to avoid confusion.

Change-Id: I37db191c144c81aba5d4a1e6291db5669a35a31a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12030
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-20 23:54:40 +01:00
Timothy Pearson 7c55f374d1 northbridge/amd/amdht: Add support for HT3 2.8GHz and up link frequencies
Change-Id: Ifa1592d26ba7deb034046fd3f2a15149117d9a76
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12027
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-20 23:49:38 +01:00
Timothy Pearson 5173bb7d9d cpu/amd/family_10h-family_15h: Fix incorrect revision detection
The revision detection code for AMD Family 10h/15h was modified
to use a 64-bit value instead of 32-bit in order to accomodate
additional processor revisions.  The FIDVID code was not updated
at that point, leading to incorrect revision use during FIDVID.

Change-Id: I7a881a94d62ed455415f9dfc887fd698ac919429
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12026
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-20 23:47:54 +01:00
Stefan Reinauer a40f64f7fb x86emu: Remove XFree86 CVS tags
They're not supported by git.

Change-Id: I8157cdc0f5f4072af588772680741b72d21a9223
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12494
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-20 20:43:54 +01:00
Stefan Reinauer d89736072f x86emu: Undefine _NO_INLINE
Never defined by the server.

Change-Id: If22727cf3953c2931d107146fb99b5997f8a13d5
Original-Reviewed-by: Eric Anholt <eric@anholt.net>
Original-Signed-off-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12493
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-20 20:43:44 +01:00
Stefan Reinauer 92a97f459f x86emu: Fix some set-but-not-used warnings.
Change-Id: Ide861733d721a21b77862076bf7ad70c7ee6a472
Original-Reviewed-by: Adam Jackson <ajax@redhat.com>
Original-Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12492
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-11-20 20:43:29 +01:00
Timothy Pearson 0f1553b89a nb/amd/amdfam10: Add HyperTransport probe filter support
All modern Opteron processors support the HT probe filter,
which helps to increase coherent fabric performance by
reducing the number of HT transactions per cache probe.

AMD recommends that the probe filter be enabled on all
systems with more than two nodes, and it does not hurt
to enable it on systems with 2 nodes.

Change-Id: I00a27a828260be8685ae622cfa5a4995add95a8e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12021
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-20 20:32:19 +01:00
Stefan Reinauer 5ff2502151 intel/skylake: Fix flash_controller.c compilation
Since this code is not currently being built by coreboot, it
failed compilation.

Change-Id: Ib8a0e1ebc76b7dca3dd785b09398b73abad46366
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12466
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-20 20:22:34 +01:00
Ben Gardner aa5f5b153f rules.h: Add ENV_STRING and use it in console_init()
Move the #ifdef chain to set the stage name to rules.h.

Change-Id: I577ddf2de4ef249a1a4ce627bb55608731a9f5ed
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: http://review.coreboot.org/12479
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-11-20 18:44:20 +01:00
jiazi Yang 9c6d2b8f4c google/veyron_mickey: Update LPDDR3 configuration
This makes the same changes to the LPDDR3 configuration that
were made for Samsung modules:
- Enable ODT function
- Change DS to 40  from 34.3

BUG=chrome-os-partner:47416
BRANCH=firmware-veyron-6588.B
TEST=Boot on mickey elpida board

Change-Id: If8c729188803dd854dbbe80539fb228636b5eb9f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b3eb8bc31b9727b67a6b53b4370315010d9d6379
Original-Change-Id: I2d54d3087ecd3536469866f30e4eb2d8b1acd5c1
Original-Signed-off-by: jiazi Yang <Tomato_Yang@asus.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/311153
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/311855
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/12484
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-20 18:21:36 +01:00
Pratik Prajapati b90b94d3ef intel: Add MMA feature in coreboot
This patch implements Memory Margin Analysis feature in coreboot.

Few things to note
(1) the feature is enabled by setting CONFIG_MMA=y in the config file
(2) coreboot reads mma_test_metadata.bin from cbfs during romstage and
gets the name of MMA test name and test config name. Then coreboot finds
these files in CBFS.
If found, coreboot passes location and size of these files to FSP via
UPD params.  Sets MrcFastBoot to 0 so that MRC happens and then MMA test
would be executed during memory init.
(3) FSP passes MMA results data in HOB and coreboot saves it in cbmem
(4) when system boots to OS after test is executed cbmem tool is used
to grab the MMA results data.

BRANCH=none
BUG=chrome-os-partner:43731
TEST=Build and Boot kunimitsu (FAB3) and executed MMA tests
Not tested on Glados

CQ-DEPEND=CL:299476,CL:299475,CL:299474,CL:299473,CL:299509,CL:299508,CL:299507,CL:*230478,CL:*230479

Change-Id: I0b4524abcf57db4d2440a06a79b5a0f4b60fa0ea
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4aba9b728c263b9d5da5746ede3807927c9cc2a7
Original-Change-Id: Ie2728154b49eac8695f707127334b12e345398dc
Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/299476
Original-Commit-Ready: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Tested-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: http://review.coreboot.org/12481
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-20 18:21:25 +01:00
Martin Roth 5cf5828c02 fsp1_0: Remove hardcoded microcode locations
These are no longer needed.

Test: Booted minnowmax.

Change-Id: Ie77040f3506464c614760bd4d30280c8113373bd
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12468
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-20 16:36:08 +01:00
Felix Held d2e8f6ad33 southbridge/amd: add support for Bolton FCH
The Bolton FCH needs different firmware files than the Hudson FCH.

A small patch to vendorcode is probably needed to make the XHCI controller work.

XHCI_DEVID in pci_devs.h is probably wrong for Hudson.

Change-Id: Ib81c0881979edcde717217dc89d8af415520d7e5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/9623
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-20 16:35:47 +01:00
Timothy Pearson e536a4d916 cpu/amd/fam10h-fam15h: Set northbridge throttle values
The existing code did not set the northbridge throttle
values on Family 15h, leading to sporadic and random
deadlocks in the crossbar per AMD notes.

Properly set the northbridge throttle values on Family 15h.

Change-Id: I6304b63708c65fedb9c2d46b8c862b7f0adf1102
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12025
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-11-20 16:30:08 +01:00
Werner Zeh 9b7bb4911d siemens/mc_tcu3: Clear checksums in hwinfo
Clear the precomputed checksums in hwinfo as they
will be updated in manufacturing process.

Change-Id: I952ca8f1ca32831c4b296de633c0d58da111ccba
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/12475
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-20 16:13:55 +01:00
WANG Siyuan 8b4f98a41f AMD Bettong: add README
This is the initial version of README.
AMD provides stable Bettong code in github. Add the link and bug fixed
list to README.

Change-Id: Ie8b761096fd1850afb9363ebb761aa4992b47643
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/11737
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2015-11-20 05:42:32 +01:00
WANG Siyuan 839d68f101 AMD Bettong: refactor PCI interrupt table
1. Use write_pci_int_table to write registers 0xC00/0xC01.
2. Add GPIO, I2C and UART interrupt according
"BKDG for AMD Family 15h Models 60h-6Fh Processors",
50742 Rev 3.01 - July 17, 2015
3. The interrupt valudes are moved from bettong/mptable.c.
All devices work in Windows 10.

Change-Id: Iad13bc02c84a5dfc7c24356436ac560f593304d7
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/11746
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2015-11-20 05:41:41 +01:00
Martin Roth f730e44baa google/veyron_danger & veyron_emile: Fix Kconfig warnings
These platforms needed to be adjusted to fix various Kconfig warnings.

Both platforms needed MAINBOARD_HAS_NATIVE_VGA_INIT because they're setting
MAINBOARD_DO_NATIVE_VGA_INIT.

veyron_emile needed a few symbols that depend on CHROMEOS to be moved
into a new config CHROMEOS section.  This matches the other CHROMEOS
platforms.

veyron_danger needed to select MAINBOARD_HAS_CHROMEOS before the
CHROMEOS symbol was set.

Change-Id: I8c7f594ba572a02513a68095c16314006fb4e379
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12462
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-11-20 00:29:19 +01:00
Martin Roth 267efa2bd0 google/lars & intel/kunimitsu: Fix Kconfig warnings
EC_SOFTWARE_SYNC depends on CHROMEOS, so move it into the CHROMEOS section.
This fixes the kconfig warning:

warning: (CHROMEOS && BOARD_SPECIFIC_OPTIONS ...) selects
EC_SOFTWARE_SYNC which has unmet direct dependencies
(MAINBOARD_HAS_CHROMEOS && CHROMEOS && VBOOT_VERIFY_FIRMWARE)

Change-Id: I459f48fd18c7568c4584df7d4aefa69dec3e4907
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12460
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-20 00:19:56 +01:00
Patrick Rudolph 9b51568897 nb/intel/sandybridge/raminit: Factor out code into toggle_io_reset
Found while doing code review.

Use a function to toggle IO reset signal.

Change-Id: I4cb0885ed9be763fbc4069e4d015a36a7183c823
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: http://review.coreboot.org/11916
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-11-19 21:43:31 +01:00
Hung-Te Lin b15a0d0a6f vendorcode/google/chromeos: Cache VPD data into CBMEM
There are few drawbacks reading VPD from SPI flash in user land, including
"lack of firmware level authority" and "slow reading speed".

Since for many platforms we are already reading VPD in firmware (for
example MAC and serial number), caching the VPD data in CBMEM should
will speed up and simplify user land VPD processing without adding
performance cost.

A new CBMEM ID is added: CBMEM_ID_VPD, referring to a structure containing
raw Google VPD 2.0 structure and can be found by the new LB_TAG_VPD in
Coreboot tables.

BRANCH=smaug
BUG=chrome-os-partner:39945
TEST=emerge-smaug coreboot chromeos-bootimage # and boots successfully.

[pg: lots of changes to make it work with what happened in upstream
since 2013]

Change-Id: If8629ac002d52abed7b480d3d06298665613edbf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 117a9e88912860a22d250ff0e53a7d40237ddd45
Original-Change-Id: Ic79f424a6e3edfb6c5d168b9661d61a56fab295f
Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/285031
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12453
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2015-11-19 21:37:47 +01:00
Douglas Anderson bca67fb7dc edid: Don't half parse (and wrongly print) more detailed timings
The EDID parsing code continued to update _some_ fields of the output
edid but not others if "did_detailed_timing" was already set.  It also
then went on to print out this halfway mix of modes each time, despite
the fact that it didn't really update everything.

Let's fix that.  We'll reduce code changes by using a temporary copy of
data in detailed_block() and then we'll copy it back if we decide we
should update.

BRANCH=none
BUG=chrome-os-partner:46998
TEST=No more bogus printouts

Change-Id: Idbfa233e0997244c22ef21c892c4473a91621821
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4d69999cdd7ce3cd2c9332ab3f22ea8eb4b6f2e9
Original-Change-Id: Ia72cac7fda2772f26477e43237678fa30feca584
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/309541
Original-Reviewed-on: https://chromium-review.googlesource.com/309609
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/12444
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-19 21:37:42 +01:00
Douglas Anderson 78e226cf36 edid: Use a better mode for 640x480
The hardcoded clock value for 640x480 was 25.175 MHz.  That's a valid
clock to use, but is quite hard to make a non-jittery clock from PLLs.
It's much easier to make 25.200 MHz, so let's do that.

The difference between the two modes is 59.9 Hz vs. 60 Hz and it seems
better to make a non-jittery 60 Hz rather than a very jittery 59.9 Hz.

BRANCH=none
BUG=chrome-os-partner:46256
TEST=Insignia monitor works, so do others

Change-Id: I8aa124d04a90f5dcf9cfa923ed3b693fbb4a06d8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e32ce13462101dc60cfed60b6948b7597e93525a
Original-Change-Id: Ia9804afe8011a915e4bec306e863d34ad7e27be5
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/309540
Original-Reviewed-by: Stphane Marchesin <marcheu@chromium.org>
Original-(cherry picked from commit 7f32c9f460991e5e3b947117d6ae4080e630a532)
Original-Reviewed-on: https://chromium-review.googlesource.com/309576
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/12443
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-19 21:37:39 +01:00
Douglas Anderson 9fa0760e97 edid: Don't set standard timings as supported if they're not
The set to say that a standard timing was supported was not properly in
the "if" test.  That meant that even when standard timings weren't
supported, we thought that they were.  That had the side effect of never
using the detailed mode.

BRANCH=none
BUG=chrome-os-partner:46998
TEST=Adafruit panel works now

Change-Id: Ide3ed6c5682840f808d854755dac58e9057e6bda
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c99d3ee8d163fc6be207c5a7df2a7aecd7af7849
Original-Change-Id: Ib67735219fd28516857d9b63f1ba156573f1bea3
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/309521
Original-(cherry picked from commit 4e4c2816e2239299bc02e3a57fb18056db62b56c)
Original-Reviewed-on: https://chromium-review.googlesource.com/309552
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/12442
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-19 21:37:33 +01:00
Douglas Anderson 14dd3701c3 edid: Remove useless parameter from detailed_cvt_descriptor()
The detailed_cvt_descriptor() function takes a parameter "out" for no
good reason.  Remove it.

BRANCH=none
BUG=chrome-os-partner:46998
TEST=Build and boot

Change-Id: I1042dba9ddf2b4b543bd07615013088be5055950
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5c3474c9b1f9fb73f44d64d3a0592f92339da2df
Original-Change-Id: I4d695a6dba6606d2132578ce0ab4cb612c83d0f4
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/309598
Original-(cherry picked from commit 39122e242e808d71a4e274e8a23e9a63f4984388)
Original-Reviewed-on: https://chromium-review.googlesource.com/309496
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/12441
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-19 21:37:27 +01:00
Timothy Pearson 48bfcdf006 mainboard/asus/kgpe-d16: Fix I/O link detection
Change-Id: Ibefc9dc2e1e0267389eb8d716408bae6026ce084
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12024
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-19 20:23:11 +01:00
Timothy Pearson 4530df431e northbridge/amd/amdmct/mct_ddr3: Move K10D configuration into separate file
Change-Id: Id45888f266fac7810a63fef43b8d7a0ee40cbf70
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12023
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-19 20:22:56 +01:00
Timothy Pearson 51cfbcddde cpu/amd/fam10h-fam15h: Bring HT register configuration in line with BKDG
The existing HyperTransport register configuration values were incorrect
in many spots.  Apply the correct values from the BKDG on Family 10h and
Family 15h processors.

Change-Id: I009b6f478340e2dbfcda2b4534473d4397f9ecef
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12022
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-19 20:22:08 +01:00
Patrick Rudolph 371d291df5 nb/intel/sandybridge/raminit: Comment the code
Add lots of comments for better documentation.

Change-Id: Ia203cb649857f979bb6c1c2d405b74f2ccc8f99d
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: http://review.coreboot.org/11915
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2015-11-19 20:20:42 +01:00
Martin Roth 7bc74ab25b device/device.c: remove warning for missing apic read resources
We have had the "APIC: 00 missing read_resources" messages
for many years. It's obviously not an error, and also doesn't
cause boot failures. Therefore, remove the message.

Change-Id: I7f99c5950a3457df04e7ef6edb456b70dba9680c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12471
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-11-19 14:46:43 +01:00
Michał Masłowski 9d0330f537 lenovo/r400: Add clone of Lenovo T400
The existing code for the Lenovo T400 works without changes on the
Lenovo R400.  Same HDA verbs are provided by Lenovo BIOS on both
laptops.

Change-Id: I1dadddd7250ab80a4c40c2435865d72e3e5d99c9
Signed-off-by: Michał Masłowski <mtjm@mtjm.eu>
Signed-off-by: Francis Rowe <info@gluglug.org.uk>
Reviewed-on: http://review.coreboot.org/8393
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-11-19 12:46:40 +01:00
Zheng Bao c64f21c02e AMD Hudson: Use amdfwtool to integrate firmwares.
Change-Id: Ie17a744b6ef4e5405b3dfcecc1deb6462220ec60
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/12435
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-19 04:12:25 +01:00
Felix Held df95b51ab6 pcengines/apu1: enable use of clkreq pins
only enable pcie gpp clocks when the corresponding clkreq pin is asserted

Change-Id: I7822d011bb94867d470c0194e6b652833c395cb2
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/12353
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-11-19 02:43:23 +01:00
Felix Held b06015b92e pcengines/apu1: disable unused clock outputs
disable unconnected FCH clock outputs to save some power

Change-Id: Ib3efebb8656392d58d762c23827168017d273de8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/12082
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-11-19 02:43:12 +01:00
Martin Roth 1455437c9e x86: Add Kconfig to disable early bootblock postcodes
The Intel cave creek chipset needs to have port 80 routing configured
before any post codes can be sent to port 80h.  Sending post codes out
before the routing is done will hang the system.

This patch allows us to disable the first couple of post codes that go
out before the routing can be configured.

The Kconfig symbol is selected by the cave creek chipset (fsp_i89xx).

Change-Id: I9bf41669ec32744f87a1ed2de011d31c72ea38da
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12422
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: York Yang <york.yang@intel.com>
2015-11-19 00:16:50 +01:00
Martin Roth 355dfda3f0 Remove dependency for HAS_PRECBMEM_TIMESTAMP_REGION
HAS_PRECBMEM_TIMESTAMP_REGION was dependent on COLLECT_TIMESTAMPS,
but should be allowed to be selected independently.  My thought is that
the code may only be used when collecting timestamps, the HAS prefix
signifies that this is a platform configuration option.

This fix could also be done by adding 'if COLLECT_TIMESTAMPS' everywhere
that 'select HAS_PRECBMEM_TIMESTAMP_REGION' is used

Change-Id: Iaf4895475c38a855a048dc9b82d4c97e5e3f4e5c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11338
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-18 23:22:11 +01:00
Ben Gardner 8420ad4b41 Kconfig: fix typo in description of the TRACE option
Change-Id: Icec6d047530e64228a3e71a636af4266ed5a73f0
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: http://review.coreboot.org/12457
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-18 22:48:09 +01:00
Marcin Wojciechowski 68b79cdda4 fsp1_0: Update rangeley to revision POSTGOLD4
Alignment of Intel Firmware Support Package 1.0 Rangeley
header and source files to the revision: POSTGOLD4
Detail changelog can be found at http://www.intel.com/fsp
FSP release date September 24, 2015

Change-Id: If1a6f95aed3e9a60af9af8cf9cd466a560ef0fe2
Signed-off-by: Marcin Wojciechowski <marcin.wojciechowski@intel.com>
Reviewed-on: http://review.coreboot.org/12418
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-18 22:09:54 +01:00
Timothy Pearson 0122afb609 cpu/amd/fam10h-fam15h: Update Fam15h APIC config and startup sequence
This fixes Family 15h multiple package support; the previous code
hung in CAR setup and romstage when more than one CPU package was
installed for a variety of loosely related reasons.

TEST: Booted ASUS KGPE-D16 with two Opteron 6328 processors
and several different RDIMM configurations.

Change-Id: I171197c90f72d3496a385465937b7666cbf7e308
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12020
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-18 17:14:48 +01:00
Zheng Bao 631c8a2690 AMD/Bettong: add FCH's GPIO, UART & I2C support
Merlin Falcon's FCH has GPIO, UART and I2C. All of them are controlled
by registers mapped at MMIO space.
This ASL code is used for Windows drivers.

TEST:
1. Boot Windows 8 or Windows 10.
2. Install AMD Catalyst driver.
3. AMD FPIO, UART and I2C can be found in device manager.
4. I2C passed Multi Interface Test Tool (MITT) test.

Change-Id: I7ffe3fe0046d9a078cc38176c29a8e334646a5a3
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11750
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2015-11-18 17:02:28 +01:00
ZhengShunQian 71c0aa29fa google/veyron_emile: retrieve the MAC address from vpd
Emile has a on board ethernet.

BUG=chrome-os-partner:47465
TEST=vpd -s ethernet_mac0=001122334455
     build and check the MAC address

Change-Id: I90ed0ed1253c804568fcdd3dd212bb062a48c836
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 99b275c594196de0811f68380e66c226d2649927
Original-Change-Id: I1690a1f39090c57c64d4965092c80eef9070babf
Original-Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/311900
Original-Commit-Ready: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/12452
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-18 16:29:19 +01:00
Douglas Anderson 7760a47892 google/veyron*: Pulse the i2c clock once if sda was low
On one particular TV the TV was holding SDA low when it came up.  It
would release the SDA when the SCL went low the first time.
Unfortunately the HDMI i2c port wouldn't transmit until the SDA was
released.

Let's detect this case and insert a bogus clock pulse to try to get the
other side to release SDA.

It's unclear why the kernel doesn't have this problem.

BRANCH=none
BUG=chrome-os-partner:46256
TEST=Insignia TV works now

Change-Id: Ic9d27eb69bdc9c5fb11a68258e0c755cdc8b79d7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 356ee7503f04e741a41be37ad573b588067b7114
Original-Change-Id: I4b6361877e0576cc4ea2f643f073f1aab660e434
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/309258
Original-Reviewed-by: Agnes Cheng <agnescheng@google.com>
Original-Commit-Queue: Agnes Cheng <agnescheng@google.com>
Original-Trybot-Ready: Agnes Cheng <agnescheng@google.com>
Original-Tested-by: Agnes Cheng <agnescheng@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/309546
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/12451
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-18 16:29:16 +01:00
david c494c7d68d google/lars: enable wakeup from S0ix using headset button
Kernel needs to set Audio IRQ as wake capable.

BUG=None
BRANCH=None
TEST=emerge-lars coreboot

Change-Id: Ib7f0fc52baa006d992a2f91a63417e3f76817634
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 32d82ac48c6f830fbb09b776d0adaf6b7a727416
Original-Change-Id: I3fd70ac99c623a99b07fa1a185ebace8c1fc3d69
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/312172
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12450
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-18 16:29:12 +01:00
david 2b7103cb0f google/lars: Enable wake from touch pad
This patch enables GPP_B5 as ACPI_SCI for wake.
It also defines touchpad wake device in ACPI with GPE0_DW0_05 for _PRW.

BUG=none
BRANCH=none
TEST=emerge-lars coreboot

Change-Id: I2b65f6a37783ecdbdbc32ebe613243e042c865e9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ec5b629f920984564f12f2c09458ed300d031f69
Original-Change-Id: I9bd2b3595ae833fa5d07d97a7cda4a29041be837
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/311890
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/12449
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-18 16:29:09 +01:00
Duncan Laurie 3db94686e5 google/chell: Turn on keyboard backlight in romstage
Use the keyboard backlight to provide indication that the system is
booting.  This is useful for determining that a system is in S0 and
is running BIOS code.

BUG=chrome-os-partner:47435
BRANCH=none
TEST=boot on chell and see keyboard backlight come on early

Change-Id: I43e699bcc2f34998d3d6ce33ce72c7b04b55c146
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a3a0147b6de681365a9c995175076d5f397016fb
Original-Change-Id: I2441c28431e71b13b70e6533e175d29ccfd8d7e9
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/312358
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12448
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-18 16:29:05 +01:00
Duncan Laurie 4aca1477cb google/chell: Set USB current limit to 2A
The GPIO for USBA_1_ILIM_SEL_L should be low to enable 2A charging
from the Type-A port.

BUG=chrome-os-partner:47172
BRANCH=none
TEST=emerge-glados coreboot

Change-Id: I1bbcdd467684e7c1372c8ca862d498fb6cbb966c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c8a8fbed6d0fd7aea0a41db2bde104fe7a05cabe
Original-Change-Id: I3b18cbb204cfa19e50f34ea9533018e286342513
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/312451
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12447
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-18 16:28:59 +01:00
Aaron Durbin d49d42f629 google/chell: disable power rails in sleep path
For the rails controllable by the host processor through
gpios turn them off in the sleep paths. The result is that
S3 and S5 will turn off those rails.

BUG=chrome-os-partner:47228
BRANCH=None
TEST=Built for chell.

Change-Id: I5843f13be43a6ec143600585a5a0c47563e533dd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ddd5860dc0cfee68ec2f77f4931665740bede08c
Original-Change-Id: Ife0e2fb11373dd129e20b914b45cd5b56c3493f7
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/312321
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/12446
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-18 16:28:49 +01:00
Aaron Durbin ce6c35699b google/glados: disable power rails in sleep path
For the rails controllable by the host processor through
gpios turn them off in the sleep paths. The result is that
S3 and S5 will turn off those rails.

BUG=chrome-os-partner:47228
BRANCH=None
TEST=Built and booted glados. Suspended and resumed.

Change-Id: I6d45683b64ca5f7c3c47e11f95951bd2d9abf31e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ed432e2b5535da6f872a53b76886d983f00b4e8e
Original-Change-Id: I94d7e0b00bf7e7da8dc59f299e41b72e8fcb64f4
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/312320
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/12445
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-18 16:28:46 +01:00
Nico Huber 8a44b0b18c mb/roda/rk9: Fix cbmem recovery on resume path
By calling cbmem_recovery() with `0`, we rewrote the cbmem table even
on the resume path. By that, we lost the OS' resume vector and ended up
loading the payload.

Change-Id: Ic24a12d4143d6924321b1d01f07a467c58c4e9ea
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/12420
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-18 15:12:42 +01:00
Patrick Rudolph aad34cda4b nb/intel/sandybridge: Fix PEG disablement
Fix regression introduced by:
3660c0fc65
"northbridge/intel/sandybridge: Enable PEG clock-gating on demand"

Issue observed:
GNU/Linux kernel crashes in earlyinit on systems without PEG devices.
The crash occurs on every boot in different functions.
There's no problem on systems with PEG enabled.

Test system:
 * Lenovo T530
 * Intel Core i5-3320M CPU
 * Fedora GNU/Linux 4.1
 * PEG disabled in devicetree

Problem description:
Tests shows that modifing PEG chicken bit or device enable bits
after setting BIOS_RESET_CPL causes random crashes in GNU/Linux.

Problem solution:
Disable PEG devices before setting BIOS_RESET_CPL.

Final testing results:
No more random kernel crashes.

Change-Id: I4a967c2d00d7d1e4426cf5abdd5f616c21557da7
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: http://review.coreboot.org/12112
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-11-18 15:09:56 +01:00
Patrick Rudolph 240766af02 nb/intel/sandybridge/northbridge: Initialize uma_memory_base in all cases
Issue observed:
Coreboot stops at: "Not enough MTRRs available!"

Test system:
* Gigabyte GA-B75M-D3H
* Intel Pentium CPU G2130
* ATI Radeon HD4780

Problem description:
In case the IGD does not claim VGA decode, the code path taken results
in an integer overflow as uma_memory_base isn't initialized.
The MTRR assignment will fail, because of invalid memory regions.

Problem solution:
Properly initialize uma_memory_base to prevent possible integer overflow.

Final testing results:
The system boots again with IGD not claiming VGA decode.

Change-Id: I025be23b1defb6155469a3eee66569e49a695e7f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: http://review.coreboot.org/11918
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-11-18 15:09:36 +01:00
Patrick Rudolph 9f1fbb9a30 northbridge/intel/sandybridge: Fix random raminit failures
Issue observed:
    Intel raminit works in about 50% of all test-cases on lenovo x220.

Problem solution:
    Prefer a smaller valid value over the measured one for
    initial timB timings.

Final testing result:
    Tests on x220 shows that the issue was resolved.
    The test system booted successfully ten times in a row.
    Tests on Gigabyte GA-B75M-D3H revealed no regressions.

Test system:
    * Intel Pentium CPU G2130
    * Gigabyte GA-B75M-D3H
    * DIMM: "Crucial 2GB 256Mx64 CT2566aBA160BJ"

Change-Id: I1a115a45d5febf351d89721ece79eaf43f7ee8a0
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11248
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-11-18 15:08:51 +01:00
Julius Werner 7dcf9d51e5 arm64: tegra132: tegra210: Remove old arm64/stage_entry.S
This patch removes the old arm64/stage_entry.S code that was too
specific to the Tegra SoC boot flow, and replaces it with code that
hides the peculiarities of switching to a different CPU/arch in ramstage
in the Tegra SoC directories.

BRANCH=None
BUG=None
TEST=Built Ryu and Smaug. !!!UNTESTED!!!

Change-Id: Ib3a0448b30ac9c7132581464573efd5e86e03698
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/12078
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-17 21:31:20 +01:00
Julius Werner d3634c108d rules.h: Add ENV_ macros to detect current architecture
This patch expands the existing ENV_<stage> macros in <rules.h> with a
set of ENV_<arch> macros which can be used to detect which architecture
the current compilation unit is built for. These are more consistent
than compiler-defined macros (like '#ifdef __arm__') and will make it
easier to write small, architecture-dependent differences in common code
(where we currently often use IS_ENABLED(CONFIG_ARCH_...), which is
technically incorrect in a world where every stage can run on a
different architecture, and merely kinda happened to work out for now).

Also remove a vestigal <arch/rules.h> from ARM64 which was no longer
used, and genericise ARM subarchitecture Makefiles a little to make
things like __COREBOOT_ARM_ARCH__ available from all file types
(including .ld).

BUG=None
TEST=Compiled Falco, Blaze, Jerry and Smaug.

Change-Id: Id51aeb290b5c215c653e42a51919d0838e28621f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/12433
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-11-17 21:31:07 +01:00
Martin Roth 0dc6a1e898 northbridge/intel/fsp_sandybridge: remove blank line
Remove a blank line introduced in commit 31f4d00c
(northbridge/intel: Add i89xx header file)

Change-Id: I27dadb27ad041f48520709ef499bde380c58265b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12387
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-11-17 16:46:49 +01:00
Alexandru Gagniuc 90ca3412ff src/console: Link die.c in bootblock without BOOTBLOCK_CONSOLE
Without BOOTBLOCK_CONSOLE any call to die() fails due to die() symbol
not being defined at link time. die() is not is dependent on the
console backend, and can function without it (the prink gets no-oped).

Change-Id: I6cecafb576c3b1e901f3927c777f6282174fb259
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/12356
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-17 16:28:25 +01:00
Martin Roth 0307e0a499 fsp_baytrail: use external microcode .h files
The microcode for Bay Trail that's in the blobs repo is for the
M and D chip variants only.  The fsp_baytrail directory is for
Bay Trail I chip variants, and will not boot if the M/D microcode
is used.  The microcode for the I variant is supplied as part
of the Bay Trail FSP package.

Change-Id: I5493deb1626dc3cf037053e13e092f5a1143a13a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12334
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-17 00:12:35 +01:00
Julius Werner 66a476ad5f arm64: Implement generic stage transitions for non-Tegra SoCs
The existing arm64 architecture code has been developed for the Tegra132
and Tegra210 SoCs, which only start their ARM64 cores in ramstage. It
interweaves the stage entry point with code that initializes a CPU (and
should not be run again if that CPU already ran a previous stage). It
also still contains some vestiges of SMP/secmon support (such as setting
up stacks in the BSS instead of using the stage-peristent one from
memlayout).

This patch splits those functions apart and makes the code layout
similar to how things work on ARM32. The default stage_entry() symbol is
a no-op wrapper that just calls main() for the current stage, for the
normal case where a stage ran on the same core as the last one. It can
be overridden by SoC code to support special cases like Tegra.

The CPU initialization code is split out into armv8/cpu.S (similar to
what arm_init_caches() does for ARM32) and called by the default
bootblock entry code. SoCs where a CPU starts up in a later stage can
call the same code from a stage_entry() override instead.

The Tegra132 and Tegra210 code is not touched by this patch to make it
easier to review and validate. A follow-up patch will bring those SoCs
in line with the model.

BRANCH=None
BUG=None
TEST=Booted Oak with a single mmu_init()/mmu_enable(). Built Ryu and
Smaug.

Change-Id: I28302a6ace47e8ab7a736e089f64922cef1a2f93
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/12077
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-16 21:53:43 +01:00
Timothy Pearson 29016ea3b4 northbridge/amd/mct_ddr3: Add registered and x4 DIMM support to Fam15h
The existing MCT support code did not perform any of the requisite
configuration to support registered or x4 DIMMs.  Add the needed
configuration per the BKDG for Family 15h.

Change-Id: I9ee0bb7346aa35f564fe535cdd337ec7f6148f2b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12019
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-16 18:04:59 +01:00
Timothy Pearson f682d0028c amd/amdmct/mct_ddr3: Partially fix up registered DIMMs on Fam10h
Sufficient support has been added to allow booting with registered
DIMMs on the KGPE-D16 in certain slots.  ECC support needs additional
work; the ECC data lanes appear to cause boot failures in some slots.

Change-Id: Ieaf4cbf351908e5a89760be49a6667dc55dbc575
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12017
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-16 17:55:57 +01:00
Stefan Reinauer 474ff3dee5 Revert "Drop SuperIO nuvoton/nct6779d"
This reverts commit 42444f6f53.

Change-Id: Ifaaaad715d94c3c9ff365745aa2e6ee546924f4f
Reviewed-on: http://review.coreboot.org/12328
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-16 17:44:54 +01:00
York Yang 72e33a75cb intel/fsp_baytrail: Load APs microcode in baytrail_init_cpus
Load microcode to APs when performing baytrail_init_cpus. The updated
fsp1_0 driver calls TempRamInit API with a dummy microcode, so FSP
will not handle the microcode load.

Change-Id: I7b7c0f43da0d149048ae5a8fd547828f42de04fd
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: http://review.coreboot.org/12095
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-16 17:43:18 +01:00
York Yang f41ad02c83 intel/fsp_baytrail: Load BSP microcode in bootblock
Load microcode to BSP in bootblock so later on the FSP TempRamInit call
can be success. The updated fsp1_0 driver calls TempRamInit API with a
dummy microcode, so FSP will not handle the microcode load. If BSP is
not loaded a microcode before calling TempRamInit API, the call will
fail with the error No Valid Microcode Was Found.

Change-Id: I1fbe68e14e5a24d8f2da70603cd2f03675b9ca81
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: http://review.coreboot.org/11896
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-16 17:42:56 +01:00
York Yang 3ecfdbde14 intel/fsp1_0: Use dummy microcode when calling FSP TempRamInit
Pass in dummy microcode when calling FSP TempRamInit API. FSP will not
do the microcode load and leave the work to coreboot.
Ensure that BSP has been loaded a microcode before calling TempRamInit
API, otherwise FSP will return error that No Valid Microcode Was Found.
Change has been verified on fsp_baytrail and will be applied to rangeley.

Change-Id: I8247c0503c8eb3d1c8eaa059632fb3a11c9daae9
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: http://review.coreboot.org/11895
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-11-16 17:42:36 +01:00